JPH02187988A - Dram refresh controller - Google Patents

Abstract

PURPOSE:To prevent the deterioration of the performance of a system by calculating the number of clocks corresponding to a real time of a refresh interval time by clock frequency information. CONSTITUTION:In a clock frequency information input part 2A, a frequency of a clock signal CK supplied by a frequency measuring circuit 21 is measured, and in which range the measured frequency exists is compared by a comparing and selecting part 22, and one of signals V1-V4 is set to '1'. Subsequently, from real time information from a refresh interval time storage part 1 and frequency information of the signal CK, the number of clocks of the signal CK is calculated and stored in a clock number store part 4, and a counter circuit 5 inputs the number of clocks of the store part 4 by a control signal CNT, and a refresh interval time being near an optimum one is obtained. In such a way, a refresh interval conforming to a system can be without correcting a program, therefore, the deterioration of the performance of the system can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a DRAM refresh controller, and particularly to a DR controller that controls and outputs a refresh request signal for refreshing data stored in a DRAM.
Relating to AM refresh controller.

[Conventional technology]

The DRAM refresh controller outputs refresh requests to the CPU and path arbiter.
This is done by a counter built into the DRAM refresh controller. That is, each time the counter counts a certain value, the DRAM refresh controller outputs a refresh request signal.

This constant value is the number of pulses of the clock signal (hereinafter referred to as the number of clocks) in the refresh interval.

Therefore, the actual time of the refresh interval is determined by the number of clocks in the refresh interval and the operating frequency of the clock signal. Generally, the refresh interval time can be set by the user using software for each system used.

Conventionally, in this type of DRAM refresh controller, the refresh interval time has been set by directly writing the value of the number of clocks corresponding to the refresh interval into a register inside the DRAM refresh controller.

For example, when it is desired to set the refresh interval time to 10 μs, the number of clocks is set to 80 when the operating frequency is 8 MHz.

[Problem to be solved by the invention]

In the conventional DRAM refresh controller described above, when setting the refresh interval, the clock number is directly written into the register by the program, so once it is set for a system that operates with a clock signal of a certain frequency, The refresh interval tarotsku number is
Generally, for systems operating under a different, lower frequency, the actual time of the refresh interval becomes larger and must be reset again, and the program that sets the number of clocks for the refresh interval must be modified. There is a drawback.

Also, in order to avoid resetting the number of clocks for the refresh interval, setting the number of clocks to match the lowest frequency that is expected to be used may result in unnecessary refresh cycles in systems operating at high frequencies. This has the disadvantage that it occupies the bus, leading to a considerable drop in performance depending on the system used.

An object of the present invention is to provide a DRAM refresh controller that can set the number of refresh interval clocks to a value suitable for the system without modifying the program, and can prevent system performance from deteriorating. be.

[Means to solve the problem]

The DRAM refresh controller of the present invention includes DR
a refresh interval time storage unit that stores the time interval for refreshing data stored in the AM as real time information; a clock frequency information input unit that inputs frequency information of a supplied clock signal; and a clock frequency information input unit that inputs frequency information of a supplied clock signal. a conversion unit that calculates the number of pulses of the clock signal for the refresh time interval from frequency information of the refresh time interval and real time information of the refresh time interval; and a clock number storage unit that stores the pulse number calculated by the conversion unit. a counter circuit that counts the number of pulses of the clock signal by the number of pulses stored in a clock number storage section according to a control signal and outputs a count end signal; and after outputting the control signal, inputs the count end signal. and a control section that outputs a refresh request signal in accordance with the count end signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

The refresh interval time storage unit 1 is composed of registers,
A time interval for refreshing data stored in a DRAM is set and stored using optimal real time information.

The clock frequency information input section 2 inputs data ``0'' and ``1'''.
The switches 81 to S4 are equipped with switches 81 to S4 to change the frequency information of the supplied clock signal CK.
is set and input to the converter 3.

The conversion section 3 calculates the number of pulses of the clock signal CK (hereinafter referred to as (referred to as clock number)
Calculate.

The clock number storage section 4 is composed of a register, and stores information on the number of clocks calculated by the conversion section 3.

In accordance with the control signal CNT, the counter circuit 5 inputs information on the number of clocks stored in the clock number storage section 4, starts counting pulses of the clock signal CK, counts the number of clocks, and issues a count end signal CE. Output.

After outputting a control signal CNT for instructing the start of counting, the control unit 6 receives a count end signal CE, and outputs a refresh request signal RRQ in accordance with the count end signal CE.

FIG. 2 is a block diagram showing a specific example of the conversion section 3 of this embodiment.

This converting unit 3 includes a shifter 6 and a dot shifter 31 that shift the real time information of the refresh interval time expressed in binary number stored in the refresh interval time storage unit 1 by 6 bits in the right direction (in the direction of the lower bits), and a dot shifter 31, respectively. 1-bit shifters 32A to 32c, which shift one bit at a time, and these 6-bit shifters 31.
Transfer gates 33A to 33 that switch the output signals of
The configuration includes D.

Next, the operation of this embodiment will be explained.

First, the refresh interval time storage section 1 stores the optimum real time of the refresh interval time expressed in binary numbers in units of lns. This real time is, for example, 4000ns (
In binary notation it is '111110100000°').

The clock frequency information input section 2 inputs frequency information of the supplied clock signal CK by turning on/off the switches S, to S4. The switches 81 to S4 are turned on and off when the frequency of the tarock signal CK is, for example, 2 to 4 MH.
If the frequency is 4 to 8 MHz, only the switch S1 is turned on, if the frequency is 8 to 15 MHz, only the switch S3 is turned on, and if the frequency is 15 MHz or higher, only the switch S4 is turned on. .

In the converter 3, first, the 6 and shifter 31
Binary number'' of real time 4000 ns stored in refresh interval time storage unit 1 11111010oooo
” to the right by 6 bits and transfer gate 33A
and 1 is supplied to the shifter 32A.

The 1-bit shifter 32A shifts the output signal of the 6-bit shifter 31 by 1 bit to the right and transfers it to the transfer gate 33.
B and 1 bit shifter 32a, and 1 bit shifter 32n shifts the output signal of 1 bit shifter 32A to the right by 1 bit shifter 32n.
The 1-bit shifter 32° shifts the output signal of the 1-bit shifter 32e by 1 bit to the right and supplies it to the transfer gate 33D.

The transfer gate 33A supplies the signal supplied when the switch S4 is on to the clock number storage unit 4, and similarly, the transfer gates 33a to 33o clock the signal supplied when the switches S and ~S1 are on, respectively. It is supplied to the number storage unit 4.

Now, assuming that the frequency of the supplied clock signal CK is 6 MHz, switch S2 is turned on and information on the frequency of the clock signal CK is input. The transfer gate controlled by this switch S2 is 33c, and the output signal of the 1-bit shifter 32B is supplied to this transfer gate 33c.

In other words, the binary number “111110” with a real time of 4000 ns
100000” shifted right by (6+1+1) bits “000000001111°° 15° in decimal notation
The clock number ' is stored in the clock number storage section 4.

Therefore, the counter circuit 5 receives the 6MHz clock signal CK.
Counts the pulses of “15°” and outputs the count end signal C.
Outputs E. The count time of the counter circuit 5 at this time is (1/6 MHz)×15=2500 (ns>).

Control unit 6 outputs refresh request signal RRQ in accordance with count end signal CE.

Also, the frequency of the supplied clock signal CK is 16MH
When changed to z, switch S4 is turned on.

At this time, the output signal of the 6-bit shifter 31 is transmitted to the clock number storage section 4 via the transfer gate 33A.

The clock number at this time is “000000111” in binary
110''' is "62" in decimal notation, so the count time of the counter circuit 5 is (1/16 MHz) x 62 = 3875 (ns).

In this way, the switch S of the clock frequency information input section 2
By inputting information on the frequency of the clock signal CK in steps 1 to S4, it is possible to obtain a nearly optimal refresh interval time.

FIG. 3 is a block diagram showing a second embodiment of the invention.

In this embodiment, the clock frequency information input section 2A is configured to include a frequency measurement section 21 and a comparison selection section 22, and a first
Unlike the embodiment described above, the clock number can be set automatically without requiring the operation of the switches Sl to S4.

In this clock frequency information input section 2A, first,
The frequency of the clock signal CK supplied by the frequency measurement circuit 21 is measured, and then the comparison and selection section 22 compares the range in which the measured frequency falls, and outputs the signals v1 to V4.
One of them is set to 1''.Other operations are the same as in the first embodiment.

In these embodiments, in order to simplify the circuit, the frequency of the clock signal CK is divided into four ranges to convert the actual refresh interval time into the number of clocks. It is not limited.

〔Effect of the invention〕

As explained above, the present invention stores the refresh interval time in real time, inputs the frequency information of the supplied tarock signal, and uses this frequency information to determine the number of clocks corresponding to the real time of the refresh interval time. By calculating the number of pulses of the tarokk signal by this number of clocks and outputting the refresh request signal,
It is possible to set a refresh interval suitable for the system without modifying the program, which has the effect of preventing system performance from deteriorating.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
This figure is a block diagram showing a specific example of the converting section of the embodiment shown in FIG. 1, and FIG. 3 is a block diagram showing a second embodiment of the present invention. 1... Refresh interval time storage unit, 2.2A...
Clock frequency information input section, 3... Conversion section, 4...
Clock number storage unit, 5... Counter circuit, 6... Control unit, 21... Frequency measurement circuit, 22... Comparison selection circuit, 31... 6-bit shifter, 32A to B2c...
・1 bit shifter, 33^~33o...-transfer gate, 81~S4...switch.

Claims (1)

[Claims] a refresh interval time storage section for storing time intervals for refreshing data stored in the DRAM as real time information; a clock frequency information input section for inputting frequency information of a supplied clock signal; and a clock frequency information input section for inputting frequency information of a supplied clock signal. a conversion unit that calculates the number of pulses of the clock signal for the refresh time interval from frequency information of the refresh time interval and real time information of the refresh time interval; and a clock number storage unit that stores the pulse number calculated by the conversion unit. a counter circuit that counts the number of pulses of the clock signal by the number of pulses stored in a clock number storage section according to a control signal and outputs a count end signal; and after outputting the control signal, inputs the count end signal. A DRA characterized in that it has a control section that outputs a refresh request signal in accordance with the count end signal.
M refresh controller.