JPH08235057A - Microprocessor - Google Patents

Abstract

PURPOSE: To reduce the hardware scales of peripheral circuits of a microprocessor. CONSTITUTION: The registers 102-1 to 102-n and the registers 103-1 to 103-n which can freely set the starting and ending addresses of address spaces consisting of the corresponding modules are arranged againt the modules 2-1 to 2-n of a ROM, a RAM, etc. The selection signals c1 to cn are transmitted for selection of the corresponding modules when the address to which a CPU 101 wants to have an access is included in an address range that is set by the set address value of those registers. A microprocessor 1 contains a function to select the modules and therefore the hardware scales of peripheral circuits of the microprocessor 1 can be reduced. Furthermore, the address spaces of the microprocessor 1 can be effectively used owing to arrangement of such registers that can optionally set the starting and ending addresses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor for accessing an address space composed of a plurality of modules connected to the outside.

[0002]

2. Description of the Related Art Generally, a microprocessor has an R
OM (Read Only Memory), RAM
(Random Access Memory) and a plurality of external modules, and various operations are executed by a circuit that reads a program stored in the ROM. The external module supplies data necessary for calculation and receives data resulting from the calculation from the microprocessor. The RAM is used to store the data of the calculation result and hold the data taken in from the external module.

Data acquisition and data output from these ROM, RAM and a plurality of external modules are all executed via the address bus and data bus of the microprocessor.

A technique relating to memory access control in a microprocessor is disclosed in Japanese Patent Application Laid-Open No. 62-217343. As shown in FIG. 3, the memory 2 is divided into memory blocks for each predetermined address range, and the most significant bit or a plurality of bits of the address signal sequentially output from the microprocessor 1 are branched and input. Selection signal 51 for selecting a memory block
.. to 54, and an address conversion setting switch 6 for switching the setting mode of memory block selection.

That is, the microprocessor 1 disclosed in the publication has the address conversion unit 5 as a peripheral circuit. Then, the memory 2 is divided into memory blocks for each predetermined address range, and the address conversion unit 5 decodes the address from the microprocessor 1 to select each memory block. Here, a 64 Kbyte memory area is divided into four 16 Kbyte memory blocks.

The most significant bit or a plurality of bits of the address bus are branched and input to the address conversion unit 5 to generate selection signals 51 to 54 for the divided memory blocks. Data is written in and read from one of the divided memory blocks by the selection signals 51 to 54.

Further, the address conversion unit 5 is provided with a switch unit 6 for switching the setting mode of the address conversion, and by switching the setting mode, selection switching of the memory block is executed without changing the address from the microprocessor 1. are doing.

[0008]

However, in the above-mentioned prior art, since the microprocessor has the address conversion circuit for generating the selection signal for accessing the memory from the microprocessor, the memory block to be accessed is accessed. If the number of bits increases, the number of address bits branched to the address conversion unit increases, and the hardware scale increases.

Further, in the block division according to the conventional technique, since each memory block has a uniform address range, the address range of each memory block is determined by the address range of the maximum area block. Therefore, depending on the memory block, more memory area than necessary may be allocated, and in such a case, there is a drawback that the utilization efficiency of the memory decreases.

Here, in order to arbitrarily set the address range of the memory block for each block, it is necessary to branch all address bits and input them to the address conversion unit. In such a case, there is a drawback that the scale of the hardware also becomes large.

The technique disclosed in Japanese Patent Application Laid-Open No. 2-264339 relates to the improvement of the debug environment and cannot solve the above-mentioned drawbacks.

Further, the technique disclosed in Japanese Utility Model Laid-Open No. 59-151331 is to arbitrarily change the initial address, and the above-mentioned drawback cannot be solved.

The present invention has been made in order to solve the above-mentioned drawbacks of the prior art, and an object thereof is to provide a microprocessor capable of reducing the scale of hardware of peripheral circuits.

[0014]

A microprocessor according to the present invention is a CPU for accessing an address space composed of a plurality of externally connected modules.
And a start address setting register capable of setting a start address of an address space formed by a corresponding module provided corresponding to each of the plurality of modules, and provided corresponding to each of the plurality of modules. The end address setting register in which the end address of the address space formed by the corresponding module can be freely set, and when the address to be accessed by the CPU is included in the address range defined by the set address values of these registers And a sending means for sending a selection signal for selecting a module.

[0015]

There is provided a start address setting register and an end address setting register in which the start address and the end address of the address space formed by the corresponding modules respectively corresponding to a plurality of modules can be freely set. When the address to be accessed by the CPU is included in the address range of the set address values of these registers, a selection signal for selecting the corresponding module is transmitted.

[0016]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a microprocessor according to the present invention.

In the figure, a microprocessor 1 according to an embodiment of the present invention is provided with an address bus corresponding to external modules 2-1 to 2-n (n is a positive integer, the same applies hereinafter) such as ROM and RAM. Start address setting registers 102-1 to 102-1 having the same bit configuration as the number of bits of
02-n and n end address setting registers 103-1 to 10-10 provided corresponding to the external modules 2-1 to 2-n and having the same bit configuration as the number of bits of the address bus.
3-n is included. These registers 10
2-1 to 102-n and 103-1 to 103-n are assumed to be capable of freely writing set values from the CPU 101 under software control.

Further, the microprocessor 1 according to the present embodiment has the register 102-1 which corresponds the value of the address bus.
102-n and 103-1 to 103-n, and n comparators 104-1 to 104-n for respectively comparing with the respective set values,
It is configured to include output ports 108-1 to 108-n for outputting selection signals (select signals) c2 to cn which are comparison results by the comparators 104-1 to 104-n.

In such a configuration, n start address setting registers 1 from the CPU 101 using the data bus a.
02-1 to 102-n and end address setting register 1
A start address and an end address for each external module are set in each of 03-1 to 103-n. The set start addresses d1 to dn and end addresses e1 to en are input to the comparators 104-1 to 104-n.

Here, focusing on the comparator 104-1,
As shown in FIG. 2, the comparator 104-1 includes comparator circuits 105 and 106 for detecting the magnitude of the address value, and a NAND gate 107.

First, the comparison circuit 105 compares the value of the input start address d1 with the value of the address bus b. As a result of the comparison, when the value of the address bus b is equal to or larger than the start address, the output signal f is set to "1".

On the other hand, the comparison circuit 106 compares the input value of the end address e1 with the value of the address bus b. When the value of the address bus b is equal to or less than the end address as a result of the comparison, the signal g which is the output result is set to "1".

The NAND gate 107 outputs the logical product of the signals f and g which are the output results of the comparison circuits 105 and 106. Therefore, the value of the address bus b is d
When 1 ≦ value of address bus b ≦ e1, that is, within the range of the address space of the corresponding module, the NAND gate 107 outputs “0”. That is, the address bus b
If the value of is within the address range indicated by the setting contents of the start address setting register and the end address setting register, the selection signal c1 is sent to the external module via the output port.

Comparator 104-2 other than the comparator 104-1
To 104-n have the same configuration as that of FIG. 2, and the start addresses d2 to dn of the corresponding start address setting registers 102-1 to 102-n and the corresponding end address setting registers 103-1 to 103-n are also included. End address e2 to e
n is used as an input, and the selection signals c2 to cn are transmitted according to the result of comparison with the value of the address bus b.

In short, since the microprocessor 1 of this example has n comparators 104-1 to 104-n, any one of the selection signals c1 to cn is output to the output port 108-1. To 108-n through the corresponding output ports to the corresponding external modules 2-1 to 2-n. This enables access to each of the n modules 108-1 to 108-n, that is, data acquisition and data output.

As described above, since the function of selecting the external module is provided inside the microprocessor, the hardware scale of the peripheral circuit of the microprocessor can be reduced.

Since the start address setting register and the end address setting register are provided, the access area to the external module can be arbitrarily set by software. Therefore, it is not necessary to make each access area by each external module uniform, and it is possible to divide into an arbitrary address range, and it is possible to effectively use the address space of the microprocessor.

[0029]

As described above, the present invention has the effect of reducing the hardware scale of the peripheral circuits of the microprocessor by providing the function of selecting an external module inside the microprocessor.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a microprocessor according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a comparator in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional microprocessor or the like.

[Explanation of symbols]

 1 Microprocessor 2-1 to 2-n External Module 102-1 to 102-n Start Address Setting Register 103-1 to 103-n End Address Setting Register 104-1 to 104-n Comparator 105, 106 Comparison Circuit

Claims (3)

[Claims] 1. A CP for accessing an address space composed of a plurality of modules connected to the outside.
A microprocessor including a U, comprising: a start address setting register, which is provided corresponding to each of the plurality of modules and is capable of setting a start address of an address space constituted by the corresponding modules; and a start address setting register corresponding to each of the plurality of modules. An end address setting register in which an end address of an address space provided by a corresponding module can be freely set, and when an address to be accessed by the CPU is included in an address range defined by the set address values of these registers A microprocessor for transmitting a selection signal for selecting a corresponding module. 2. The first sending means for detecting that the address to be accessed by the CPU is equal to or larger than the set address value of the start address setting register, and the sending means for the CPU to access. Second detecting means for detecting that the address to be set is a value equal to or less than the set address value of the end address setting register,
2. The microprocessor according to claim 1, wherein a selection signal for selecting the corresponding module is transmitted according to the detection results of the first and second detecting means. 3. The microprocessor according to claim 1, wherein the module is a memory.