JPH02187065A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To facilitate formation of different types of elements which are isolated from each other on a same semiconductor substrate by a method wherein a trench is formed in the substrate and a single crystal semiconductor layer is provided in the trench with a dielectric film between and the elements are formed on the substrate and the single crystal semiconductor layer. CONSTITUTION:A trench 4 is formed in a silicon substrate 2 and a silicon oxide film 6 is formed in the trench 4. Further, a single crystal silicon layer 8 is formed in the trench 4 with the film 6 between. A conductor layer 10 is formed between the film 6 and the layer 8 and patterned. Further, an element isolation trench 18 is formed in the trench 4 and an element isolation silicon oxide film is provided on the wall of the trench 18 and the trench 18 is filled with an impurity-doped polycrystalline silicon layer 20. Then a bipolar transistor is formed in the trench 4 and a C-MOS is formed on the substrate side by a bipolar process and a C-MOS process.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device including dielectrically separated elements of different types.

(Prior art) BiCM including bipolar transistor and 0MO3
In a semiconductor integrated circuit device such as O8, processes for each element are different in order to optimize the characteristics of each element.

An example of a manufacturing process is the standard cell method. In this method, circuit blocks exhibiting a set of functions are prepared in advance as cells, and a desired semiconductor integrated circuit device is constructed by combining these cells. If you try to add an analog circuit to the standard cells that make up a CMOS logic circuit,
A method in which a mask step for forming a bipolar transistor is added to the S process cannot form a bipolar transistor that satisfies analog characteristics and high speed. This is because, for example, a buried layer is required in a bipolar transistor, but a buried layer is not included in a CMOS process.

(Problem to be solved by the invention) The present invention, like a bipolar transistor and 0MO3,
It is an object of the present invention to provide a semiconductor integrated circuit device in which elements of different processes can be mounted together.

(Means for Solving the Problems) In the present invention, a groove is formed in a semiconductor substrate, and a single crystal semiconductor layer is formed in the groove with a dielectric film interposed therebetween.

Elements are formed on each of the substrate and the semiconductor layer.

In a preferred embodiment of the present invention, a conductive layer is also formed between the dielectric layer and the dielectric film.

(Operation) The element formed on the substrate and the element formed on the semiconductor layer in the groove are separated from each other by the dielectric film in the groove.

When a conductive layer is formed between the semiconductor layer and the dielectric layer in the trench, this conductive layer can be used as a buried layer of a bipolar transistor, for example.

(Example) FIG. 1 represents one embodiment.

Reference numeral 2 denotes an N-type silicon substrate, in which a groove 4 is formed, and within the groove 4, about 5,000 to 10,000 silicon acids 6 are formed. An N-type, single-crystal silicon layer 8 is formed in the trench 4 with the silicon oxide film 6 interposed therebetween.

In trench 4, a conductor layer 10 is formed and patterned between silicon oxide film 6 and single crystal silicon N8. As the conductor layer 10, high melting point metals such as W, Mo, and Ti or silicides thereof can be used, for example. A base region made of a P-type impurity diffusion region 12 is formed in the groove 8 to form a bipolar transistor.

An emitter region is formed within the diffusion region 12 by an N" type diffusion region 14. 16 is a base contact region.

A groove 18 for element isolation is formed in the groove 4, and the conductor layer 1
0 is exposed within the groove 18. For example, a silicon oxide film is formed on the wall surface of the groove 18 for element isolation, and a polycrystalline silicon layer 20 whose resistance has been reduced by introducing impurities is embedded inside the groove 18. In the groove 18, the conductor layer 10 and the polycrystalline silicon layer 2o are connected.

An interlayer insulating film 22 such as a silicon oxide film is formed on this bipolar transistor, and a base electrode 24, an emitter electrode 26, and a collector made of a metal layer made of aluminum or the like are connected through contact holes formed in the glabellar insulating film 22. An electrode 28 is formed.

0MO8 is formed on the substrate 2 side. The figure shows an N-channel MOS transistor among them.

A P-type well 30 is formed in the substrate, and within the well 30, a source region 32 and a drain region 34 are formed by N-type diffused regions. A gate electrode 38 made of a polycrystalline silicon layer whose resistance has been lowered by introducing impurities is formed on the channel region with a gate oxide film 36 interposed therebetween. A source electrode 40 of a metal layer is connected to the source region 32 and the drain region 34 through a contact hole in the glabella insulating film 22. A drain electrode 42 is connected.

Reference numeral 46 denotes a trench for separating the MOS transistors, and a dielectric film 48 such as a silicon oxide film is placed in the trench 46.
Polycrystalline silicon M50 is embedded through the hole.

Although not shown in the figure, a P-channel MOS transistor whose conductivity type is opposite to that of the N-channel MoS transistor is also formed.

Elements formed so as to be isolated from each other as shown in FIG. 1 are connected by metal wiring as necessary.

According to the embodiment shown in FIG. 1, BicMO8 can be achieved simply by adding a bipolar process to a normal CMOS process. For example, specifically when adding an analog circuit to a CMOS logic circuit, it is possible to mix the analog circuit and the digital circuit by simply adding a bipolar process to the CMOS process. And CM
Based on the OS standard cell method, bipolar transistors can also be formed using the standard cell method.

In the embodiment, a bipolar transistor is formed in the groove 4,
Although a CMOS is formed on the substrate side, a CMOS or MoS transistor may be formed in the groove 4 without forming a conductor layer in the groove 4, and a bipolar transistor may be formed on the substrate side.

In addition to the bipolar transistor, for example, a DR transistor is placed in the groove 4.
It is also effective for forming elements such as AM and SRAM memory elements that need to avoid the influence of noise from other circuits.

Furthermore, although the single crystal silicon WI8 is formed in )l14, a single crystal GaAs layer is formed in place of the single crystal silicon layer 8, an optical device is formed on the GaAgN, and a logic circuit is formed on the substrate side. Accordingly, an I10 integrated semiconductor integrated circuit device can be constructed.

Next, a process for manufacturing the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

(A) Grooves 4 are formed in an N-type silicon substrate 2 by photolithography and etching. The position of the trench 4 is the position of the region where the bipolar transistor is to be formed.

(B) Next, a sub-silicon oxide film 6 having a thickness of approximately 5,000 to 10,000 layers is deposited over the entire surface by, for example, the CVD method.

A conductor layer 10 is deposited and patterned by photolithography and etching into a shape that will become a buried layer of a bipolar transistor.

(C) A polycrystalline silicon layer is deposited in the trench 4, and the polycrystalline silicon layer is grown into a single-crystalline silicon layer 8 by a method such as that described later with reference to FIG. To fill the trench 4 with a polycrystalline silicon layer, the polycrystalline silicon layer is deposited on the entire surface, and then an insulating layer such as a resist is formed so that the surface is flat.

Etching back is performed under conditions such that the etching rates of the insulating layer and the polycrystalline silicon layer are equal.

After forming the single-crystal silicon layer 8 in the groove 4, ordinary carbon
By forming a bipolar transistor in the trench 4 by a MOS process and a bipolar process, and forming OMO3 on the substrate side, the semiconductor integrated circuit device shown in FIG. 1 is formed.

The single crystal silicon layer 8 can be formed by a method called SO technology, such as a laser melting method.

According to Figure 3, single crystal silicon p! An example of a method for forming J8 will be explained.

A polycrystalline silicon layer 52 is deposited on the silicon oxide film 6 by, for example, a low pressure CVD method. Several hundreds to hundreds of silicon nitride films 54 are formed on the polycrystalline silicon M52 by, for example, low pressure CVD.
Deposit to a thickness of several thousand people, for example from 200 to 800 people. Furthermore, a polyethylene glycol layer 56 is formed thereon as a cooling medium.

Thereafter, a laser beam 58 such as an argon ion laser is focused from above the polyethylene glycol M56 using a lens and irradiated onto the polycrystalline silicon [52].

By scanning the laser beam 58 as shown by the arrow 60, the melted portion 62 of the polycrystalline silicon Wj52 is moved to grow the single crystal silicon layer 8.

Thereafter, the polyethylene glycol layer 56 and silicon nitride film 54 are removed.

In the manufacturing method shown in FIG. 3, hundreds to hundreds of silicon oxide films are further formed on the silicon nitride film 54 by, for example, low pressure CVD.
It may be deposited to a thickness of several thousand, for example about 100 degrees.

Polyethylene glycol 56 has better wettability and is more uniform when formed via a silicon oxide film than when formed directly on silicon nitride film 54. However, it is possible to form the polyethylene glycol layer 56 without providing a silicon oxide film.

Also, polyethylene glycol rr! An optical glass plate may be placed in contact with the surface of J56. The optical glass plate is effective in making the thickness of the polyethylene glycol layer 56 uniform. However, polyethylene glycol Q56 can be formed without providing an optical glass plate.

Further, in FIG. 3, instead of the laser beam 58, other light beams, electron beams, heat rays, or other energy beams may be used. Moreover, as the cooling medium, in place of polyethylene glycol 56, it is possible to use what is generally known as a surfactant, such as polyethylene ether, polyethylene ester, polypropylene oxide, or the like.

(Effects of the Invention) In the present invention, a groove is formed in a semiconductor substrate, a single crystal semiconductor layer is formed in this groove via a dielectric film, and elements are formed in each of the substrate and the semiconductor layer, so that the elements are isolated from each other. It is possible to mount different types of elements on the same substrate.

Further, by embedding a conductor layer in the semiconductor layer in the trench, it becomes easy to embed an analog circuit in a CMOS standard cell system.

Bipolar standard cell system becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing one embodiment, FIGS. 2(A) to 2(C) are sectional views showing the manufacturing process of one embodiment, and FIG. FIG. 2...Silicon substrate, 4...Groove, 6...
. . . Silicon oxide film, 8 . . . Single crystal silicon layer, 1o . . . Conductive layer buried in the trench, 12 . . . Base region. 14... Emitter region, 32... Source region, 34... Drain region. 1st

Claims (2)

[Claims] (1) A semiconductor integrated circuit device in which a groove is formed in a semiconductor substrate, a single crystal semiconductor layer is formed in the groove via a dielectric film, and elements are formed in each of the substrate and the semiconductor layer. (2) The semiconductor integrated circuit device according to claim 1, wherein a conductive layer is formed between the semiconductor layer and the dielectric film in the trench.