JPH0218643A - Cache memory control circuit - Google Patents

Abstract

PURPOSE:To minimize the discontinuation of the processor working and to improve the processing ability by adding a circuit to a cache memory control circuit to detect the accesses given to a cache memory of the processor and a main memory. CONSTITUTION:A 1st detecting means 6 detects that at least a processor 2 out of two processors 1 and 2 carried out a writing job to a main memory 3. While a 2nd detecting means 4 detects that the processor 1 tries to give accesses to a cache memory 5 attached to the processor 1 as well as to the memory 3. Then a suppressing means 8 stops the working of the processor 1 when the detection output is obtained from both means 6 and 4. As a result, the working of the processor 1 can be discontinued only when the processor 1 containing the memory 5 tries to give an access to the memory 5 or the memory 3. Thus it is possible to minimize the discontinuation of the processor working and to improve the processing ability.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a cache memory control circuit, and particularly to a cache memory control circuit that stops the operation of a processor having a cache memory when another processor writes to the main memory. hand,
The present invention relates to a cache memory control circuit that performs matching processing of cache memory contents.

[Conventional technology]

Conventionally, this type of cache memory control circuit has a detection circuit corresponding to a cache memory attached to a processor in a processor system having a plurality of processors and a main memory that can be accessed by any of these processors. When the detection circuit detects a write, the processor corresponding to the detection circuit detects whether the operation of that processor is a memory access or not. , it is forcibly stopped regardless of whether it is an internal process or not.

[Problem to be solved by the invention]

In the conventional cache memory control circuit described above, there is no detection circuit that detects when a processor with cache memory attempts to access memory, so regardless of whether the processor's operation is memory access or internal processing. , the operation is forcibly stopped. This has the drawback that the internal processing of the processor that is not affected by the contents of the cache memory is also stopped, resulting in a reduction in the processing capacity of the processor.

[Means to solve the problem]

In the cache memory control circuit of the present invention, in a processor attached to a cache memory among a plurality of processors that can access a common main memory, at least one of the other processors writes data to the main memory. a first detecting means for detecting that the cache memory has been executed; a second detecting means for detecting that the attached processor attempts to access the attached cache memory and the main storage device; and a suppressing means for stopping the operation of a processor attached to the cache memory when a detection output from the second detection means and a detection output from the second detection means are obtained.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, showing a case where one of two processors is attached to a cache memory.

In the figure, processors 1 and 2 are processors that execute processing according to the contents of instructions read from a shared main storage device 3 and instruct the main storage device 3 to write and read data. The cache memory control circuit 11 is composed of detection circuits 4 and 6, a clear circuit 7, an inhibition circuit 8, and a memory access control circuit 9. The detection circuit 4 receives an execution command signal from the processor, and the cache memory 5 The cache memory 5 belongs to the processor 1, and the detection circuit 6 is a circuit that detects whether the processor 2 has executed writing to the main memory 3. It is. The clear circuit 7 is a circuit that controls the cache memory 5 to clear the cache memory when receiving a detection signal from the detection circuit 6. In the suppression circuit 8, the detection circuit 4 detects that the instruction is to access the cache memory 5 or the main memory 3, and the detection circuit 6 detects that the processor 2 is writing to the main memory 3. In this case, the AND circuit 10 is a circuit that instructs the processor 1 to inhibit the clock input. Memory access control circuit 9
receives a memory access instruction from the processor 1, and controls sending and receiving addresses and data to and from the main storage device 3 and the cache memory 5. command bus 10
0. Data bus 101 and address bus 102 are connected to processor 1. This is a bus that connects the processor 2 and the main storage device 3. The inhibition signal line 103 is an output line from the inhibition circuit 8,
The memory access request signal line 104 is an output line for the memory access request signal of the processor 2, the memory access permission signal line 1.06 is a signal line that gives permission for memory access to the memory access control circuit 9, and the memory access request signal line 1- 07 is a signal line for requesting memory access from the memory access control circuit 9, memory access request signal line 1-08 is a signal line for requesting memory access from the processor 1, and memory access permission signal line 109 is a signal line for requesting memory access from the processor 1. This is a signal line that gives permission for memory access.

Next, the cache memory control operation when the processor 2 writes data to a certain address in the main memory 3 will be described. In order for the processor 2 to write to the main memory 3, a command bus 100 and a data bus 1.01 are used.
When the command, write data, and address are output to the address bus 102 and the address bus 102, the main memory device 3 receives the signals sent to the command bus], 00, and stores the address appearing on the address bus 102. The contents of the data bus]01 are written to the main memory device 3 as the address. At this time, the detection circuit 6
Detecting that the 0 signal is a write command,
This signal is transmitted to clear circuit 7 and inhibit circuit 8. On the other hand, when the processor 1 attempts to read the memory at this time, the detection circuit 4 detects a read signal, and this detection output is transmitted to the suppression circuit 8. The inhibiting circuit 8 receives outputs from both the detecting circuit 4 and the detecting circuit 6, and outputs a inhibiting signal to the inhibiting signal line 103. Then, the clock signal is suppressed in the ant circuit 10, the clock is no longer input to the processor 1, and the operation of the processor 1 is stopped. While the processor 1 is stopped, the detection circuit F1!16 which detects that the processor 2 is writing to the main memory 3 issues a clear instruction to the clear circuit 7. The clear circuit 7 gives a write instruction to the cache memory 5 so that the valid hit portion of the cache memory becomes invalid. That is, the address at that time is the address output by the processor 2 and is given to the cache memory 5 via the address bus 102 and the memory access control circuit 9. If this address is not hit in the cache memory 5, the valid bits 1 to 1 of this address in the cache memory 5 become invalid, and if it is not hit, it is not subject to matching processing, so the state remains as it is.

When the operation of the clear circuit 7 is completed, the termination is reported to the inhibition circuit 8, an instruction to cancel the inhibition is input to the AND circuit 1o, the clock is input to the processor, and the operation of the cache memory control circuit is completed. .

〔Effect of the invention〕

As explained above, the present invention adds a circuit for detecting accesses to the cache memory of the processor and the main memory to the cache memory control circuit, thereby improving the cache memory in the process of matching the contents of the main memory and the cache memory. Since a processor with memory can be stopped just when it attempts to access the cache memory or main memory, it has the effect of minimizing the suspension of processor operation and increasing processing capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention. 1.2... Processor, 3... Main storage device, 4, 6
Detection circuit, 5 Cache memory, 7 Clear circuit, 8 Inhibition circuit, 9 Memory access control circuit, 10 AND circuit, 11 Cache memory control circuit.

Claims (1)

[Claims] In a processor attached to a cache memory among a plurality of processors that can access a common main memory, detecting that at least one of the processors other than this processor has executed writing to the main memory. 1 detection means, a second detection means for detecting that the attached processor attempts to access the attached cache memory and the main storage device, the detection output from the first detection means and the 1. A cache memory control circuit comprising: inhibiting means for stopping the operation of a processor attached to said cache memory when a detection output from said second detecting means is obtained.