JPH0218632A - Method and device for evaluation of logical gate - Google Patents

Abstract

PURPOSE:To obtain the output state of a logical gate at high speed by using at least an arithmetic unit containing a logical computing element and a comparator and an encoder which receives the output of said comparator and produces the output state data on the logical gate. CONSTITUTION:A logical computing element 10a performs the logical arithmetic between a state data 12 on an input terminal and the 1st mask data 16 and defines a specific state of the input terminal. Then the result of the logical arithmetic is compared with the 2nd mask data 15 via a comparator 10b so that the specific state of the input terminal is detected. One or plural pieces of arithmetic unit 10 consisting of the element 10a and the comparator 10b are prepared as necessary. Thus the state of the input terminal necessary for evaluation of a logical gate can be known. As a result, the output state 14 of the logical gate is obtained by encoding the output of the comparator 10b of the unit 10 via an encoder 13. Then the output state of the logical gate is obtained in a simple constitution and at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a logic simulation device and a logic simulation method.

Conventional technology logic simulation means that when an input signal is applied to a logic circuit made up of interconnected logic gates,
It is to simulate what kind of signal appears at the output,
In this process, it is necessary to determine the output state from the state of the input terminal of each logic gate, which is called logic gate evaluation. Evaluation of this logic gate occurs frequently, and the challenge was how to do it quickly and easily.

A conventional evaluation of a logic gate involves, for example, sequentially accessing the state data of the input terminals of the logic gate for each input terminal, and determining the output state based on the logic function of the logic gate. Also, make a table in advance of the output states that correspond to the states of the input terminals of the logic gate,
There was also a method of accessing this to obtain the output state of the logic gate.

Problems to be Solved by the Invention However, these conventional methods of evaluating logic gates are
It cannot be said to be simple or fast because it requires a lot of time to sequentially access the state data of the input terminals, and the table defined becomes large as the number of input terminals increases.

The present invention has been made in view of the problems in the conventional evaluation of logic gates, and it is an object of the present invention to provide a logic gate evaluation device that can quickly obtain the output state of a logic gate with a simple configuration, and to provide a logic gate evaluation device that can quickly obtain the output state of a logic gate with a simple procedure. The purpose of this invention is to provide a method for evaluating logic gates that can determine the output state of logic gates.

Means for Solving the Problems In order to achieve the above-mentioned object, the present invention includes a logic operation unit that performs a logic operation on state data of an input terminal of a logic gate and first mask data, and an output of the logic operation unit and a second mask data. Logic characterized by comprising: at least one arithmetic unit including a comparator for comparing mask data; and an encoder for receiving an output of the comparator of the arithmetic unit and generating output state data of the logic gate. This is a gate evaluation device.

Function: In the logic gate evaluation device described above, the logic operator performs a logical operation on the state data of the input terminal and appropriately selected mask data, clarifies the specific state of the input terminal, and compares this result with the appropriately selected mask data. By comparing the data with the mask data using a comparator, it is detected that the input terminal is in a specific state.

By providing one or more arithmetic units consisting of the above-mentioned logical arithmetic units and comparators as necessary, it is possible to check the state of the input terminals necessary for evaluating the logic gates. You can know.

Therefore, the output state of the logic gate can be easily determined by encoding the output of the comparator of the arithmetic unit using an encoder.

Embodiments Examples of the logic gate evaluation apparatus and logic gate evaluation method according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a logic gate evaluation device according to the present invention. Here, 10 and 10 are arithmetic units and have the same internal configuration. 10a is a logical operation unit that calculates logical product for each bit;
It has human inputs A and B and one 4-bit output Z. 10b is a comparator that has two 4-hit inputs A and B and outputs 1 at output Z when these inputs are equal.

Further, 12 is state data of the input terminal of the logic gate whose output state is to be determined.

13 is an encoder, which generates an output Z from two inputs A and B as shown in FIG.

14 is an output state, and 15 to 18 are mask data.

The embodiment of the logic gate evaluation apparatus according to the present invention shown in FIG. 1 is a two-man power AND gate having the logic function of the truth table shown in FIG.

Note that the logic value in the logic gate evaluation device and logic gate evaluation method according to the present invention is represented by two hits as shown in FIG. However, state X represents a state of anxiety.

The state data 12 of the input terminal is 4 bits, and the upper two pits correspond to the input A of the two-man-powered AND gate, and the lower two pits are the same (corresponding to the human-powered B).

(1010) is input to mask data 15, 16 and 17, and (1,111) is input to mask data 18.

Now, the logic gate evaluation apparatus according to the present invention shown in FIG. 1 operates as described below.

The logical operator 10a of the arithmetic device 10 outputs the AND of the state data 12 of the input terminal and the mask data 16 to the output Z. At this time, the two-man power AN of the input terminal status data 12
If both the inputs A and B of the D gate are in the state O, the output Z of the logic operator 10a will have the same value as the mask data 16. Therefore, the output Z of the comparator 10b is
It becomes 1 when neither of the inputs A and B of the gate is in state O.

Similarly, the output 2 of the comparator in the arithmetic unit 11 is 1 when both inputs A and B of the two-man AND gate are in state 1.
becomes.

Therefore, the output Z of the encoder 13 and the output state 14 of the logic gate will be in the state O when either input A or B of the two-manual AND gate is in the state O, and will be in the state when both the manpower A and B are in the state 1. 1, and when the input state is other than these, the state becomes X, realizing the logical function of the truth table shown in FIG.

The operation of the logic gate evaluation device that determines the output state of a two-manpower AND gate has been described above, but for example, two-manpower OR
In the case of a logic gate evaluation device that determines the output state of a gate, the mask data 15 to 17 may be changed to (0101), and the encoder 13 may be changed to that shown in FIG. In addition, in order to realize an evaluation device for a logic gate whose number of inputs exceeds the power of two people, it is sufficient to increase the number of bits of data such as state data of input terminals.

As described above, the logic gate evaluation device according to the present invention has a simple configuration and therefore operates at high speed.

Next, an embodiment of the logic gate evaluation method according to the present invention will be described.

FIG. 6 is a flowchart showing an embodiment of the logic gate evaluation method according to the present invention. Here, 68 is a judgment step, which consists of a logical operation step 61 and a comparison step 62. Also, 69
is a judgment step, which consists of a logical operation step 63 and a comparison step 64. The judgment process 68 and the judgment process 69 differ only in mask data, and the content of the process is the same repetition. Note that the method for evaluating the logic gate according to the present invention shown in FIG. 6 is similar to the evaluation apparatus for the logic gate according to the present invention shown in FIG. belongs to.

In the logic gate evaluation method according to the present invention shown in FIG. 6, the output state of the logic gate is determined as described below.

First, in the logical operation step 61, the logical product of the state data I of the input terminal of the two-manual AND gate and the mask data M1 is calculated for each bit.

Next, the operation result in the logical operation step 61 and the mask data M
2 in comparison step 62, and if they are not equal, 2-man power AN
Since at least one of the inputs A or B of the D gate is in state O, the output state Z is immediately in state 0.

If the comparison results in comparison step 62 are equal, two-man labor AN
Inputs A and B of the D-gate are in state 1 or state X.

Next, in a logic operation step 63, the bit-by-bit logical product of the state data I of the input terminal of the two-manual AND gate and the mask data M3 is calculated.

Thereafter, the calculation result in the logic calculation step 63 and the mask data M4 are compared in a comparison step 64.

As a result, if they are equal, the inputs A and B of the two-manual AND gate are both in state 1, so the output state Z is in state 1. Further, if the comparison results in the comparison step 64 are not equal, the inputs A and B of the two-manual AND gate are in state 1 or state X, and since at least one is in state X, the output state Z is in state X.

As described above, the logic gate evaluation method according to the present invention allows the output state of a logic gate to be determined quickly and with an extremely simple procedure.

Effects of the Invention As described above, the logic gate evaluation device and logic gate evaluation method according to the present invention can easily and quickly determine the output state from the state data of the input terminal of the logic gate. The practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the logic gate evaluation device according to the present invention, and FIG. 2 is a truth value diagram illustrating the function of the encoder of the embodiment of the logic gate evaluation device according to the present invention. Fig. 3 is a truth value diagram of the two-man-operated AND gate handled in the same example, Fig. 4 is an explanatory diagram showing the correspondence between logic states and hit values used in the same example, and Fig. 5 is the same as shown in Fig. 1. In the embodiment of the logic gate evaluation device according to the present invention, 2
FIG. 6 is a truth diagram illustrating the function of an encoder when handling a manually operated OR gate, and FIG. 6 is a flowchart showing an embodiment of the logic gate evaluation method according to the present invention. 10... Arithmetic unit, 10a... Logical operator, 1°b... Comparator, 11... Arithmetic unit, 13... encoder. Name of agent: Patent attorney Shigetaka Awano (1 person)

Claims (2)

[Claims] (1) At least one logic operation unit that performs a logical operation on the state data of the input terminal of the logic gate and the first mask data, and a comparator that compares the output of the logic operation unit with the second mask data. A logic gate evaluation device comprising: an arithmetic device; and an encoder that receives an output from a comparator of the arithmetic device and generates output state data of the logic gate. (2) a logical operation step of performing a logical operation on the state data of the input terminal of the logic gate and the first mask data; and a comparison step of comparing the logical operation result in the logical operation step with the second mask data. A logic gate evaluation method comprising: determining output state data of the logic gate based on a comparison result in the comparison step, or repeating the logic operation step and the comparison step.