CN1222031C - Method for establishing linlimited measuring vector in chip design verification - Google Patents

Abstract

The present invention discloses a method for building testing vectors, which is suggested to simulate real network environment in the verification of the chip design of a very-large-scale system on a chip, abuses brought by a completely random test are avoided, and the performance and the function of the chip can be really reflected by the verification result of the chip design of the very-large-scale system on a chip. The method has the following steps: N dimensional spaces of random codes are built; N dimensional testing vectors are built to generate an engine. The present invention is adopted, data packages are randomly, infinitely and purposefully sent to the chip in a pertinency mode in the verification process of the chip, the real network environment is simulated realistically, verifying efficiency is greatly improved, and the performance and the function of the chip can be really reflected by the verification result.

Description

In the checking of chip design, set up the method for unlimited test vector

Technical field

The present invention relates to set up in a kind of chip checking the method for test vector, especially a kind of in the checking of ultra-large on-chip system chip design for simulating real network environment, set up the method for unlimited test vector.

Background technology

The checking of chip design is that packet (test vector) is mail on the chip of making according to the chip design file, tests the performance of this design chips and the process of function.Be transmission packet one by one in verification method in the past, and the packet that mails to chip model in the real network environment is infinite at random, so the checking result of traditional verification method can not truly reflect the performance and the function of this chip.But if anomic completely random sends packet, and, verification efficiency is reduced greatly not to the specific aim of chip functions and performance, so when producing the random data bag, must be purposive and targetedly.

The computing capability of the world today can not be moved all doors in millions of SOC ASIC doors up hill and dale simultaneously.If (combination of an instruction operation, 1000.000 ASIC of a 1000.00MIPS computer run can take one-year age so).The test vector that one millions of analogue system requires to produce can be accepted by system, and artificial intelligence can be handled the combination of millions of gate leves of all users at random simultaneously.Because those pure combination at random is infinite, so be impossible simple their whole combinations of operation.

Summary of the invention

The present invention is intended to simulate real network environment, and the drawback of avoiding the completely random test to bring, and the checking result that ultra-large on-chip system chip is designed can truly reflect performance, the function of chip, and a kind of method of setting up test vector that proposes.

For solving the problems of the technologies described above, the technical solution adopted in the present invention is as follows:

A kind of method of setting up unlimited test vector in the checking of chip design is characterized in that: this method comprises following two steps:

A sets up the N dimension space of random code;

B sets up N dimension test vector and produces engine.

At first determine to need the data object that produces at random in the above-mentioned a item of the present invention, such data object is exactly that N ties up one dimension in the space at random; The excursion of specified data object value then, the span of data object comprise all legal scopes and certain illegal scope, in order to the fault-tolerance of check system; For the data object of needs, its data variation scope division is several sections, definition of data appears at wherein certain section probability at random in the process that produces at random, and these probabilities of definition all have default value, that is, and the value of using when not redefining;

The present invention needs two kinds according to what test when setting up N dimension test vector generation engine

Different situations:

A) test that has needs the absolute repeating data of avoiding, at this moment need engine to adopt automatic track algorithm to avoid repetition in the common random process, so just in system, set up a little database, record is producing and the data that produced, if data that producing and the data that produced repeat then produce these data again;

B) test that has will made whole or local modification to the data that produced, and at this moment engine is done corresponding modification according to the value that produces at random from other modules.

Beneficial effect of the present invention shows:

Adopt the present invention, in the proof procedure of chip infinite at random and purposive and specific aim and the transmission packet, simulate real network environment realistically, improved verification efficiency greatly, make the checking result can truly reflect the performance and the function of this chip.

Description of drawings

Fig. 1 is a FB(flow block) of the present invention

Embodiment

The present invention takes following two big steps:

A sets up the N dimension space of random code;

The random code space is made up of N dimension, and each dimension produces test vector in own distinctive reference axis, the while quadrature distribute to the other side.

The principle of setting up the random code space of N+1 dimension is the process of abstract deduction, is functionality, ASIC SOC register configuration space, non-functional but can makes a mistake according to ASIC SOC (application-specific integrated circuit (ASIC) SOC (system on a chip)), this three aspects decision.These three aspects have comprised the function that general A SIC checking requires, the mistake of user-programmable configuration and capacitive.

Concrete steps are:

A) need to determine the data object of generation at random.Such as, the bag of Ethernet data bag is long, and such data are very a large amount of.Such data object is exactly that N ties up the one dimension of space kind at random;

B) excursion of specified data object value, these values may be various data types;

C) span of data object should comprise all legal scopes and certain illegal scope, in order to the fault-tolerance of check system, is 64 bytes such as the shortest of agreement regulation Ethernet bag length, then can define the shortest Bao Changwei 60 bytes of the packet of test usefulness;

D) for the data object of needs, its data variation scope division is several sections, definition of data the process that produces at random in appear at wherein certain section probability at random, these probabilities of definition all have default value, that is, the value of using when not redefining;

B, set up N dimension test vector and produce engine,

When specifically setting up test vector generation engine, have difference according to the needs of testing; The test that has needs the absolute repeating data of avoiding, at this moment need engine to adopt automatic track algorithm to avoid repetition in the common random process, so just in system, set up a little database, record is producing and the data that produced, if data that producing and the data that produced repeat then produce these data again; The test that has will made whole or local modification to the data that produced, and at this moment engine needs to make such modification, and revise according to the value that may produce at random from other modules.

Claims (1)

1, a kind of method of setting up unlimited test vector in the checking of chip design is characterized in that: this method comprises following two steps:

Set up the N dimension space of random code,

Set up N dimension test vector and produce engine;

At first determine to need the data object that produces at random in the above-mentioned a item, such data object is exactly that N ties up one dimension in the space at random; The excursion of specified data object value then, the span of data object comprise all legal scopes and certain illegal scope, in order to the fault-tolerance of check system; For the data object of needs, its data variation scope division is several sections, definition of data appears at wherein certain section probability at random in the process that produces at random, and these probabilities of definition all have default value, that is, and the value of using when not redefining;

When setting up N dimension test vector and producing engine, according to the two kinds of different situations that need of test:

A) test that has needs the absolute repeating data of avoiding, at this moment need engine to adopt automatic track algorithm to avoid repetition in the common random process, so just in system, set up a little database, record is producing and the data that produced, if data that producing and the data that produced repeat then produce these data again;

B) test that has will made whole or local modification to the data that produced, and at this moment engine is done corresponding modification according to the value that produces at random from other modules.

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