JPH0218516A - Beam scan type recording device - Google Patents

Abstract

PURPOSE:To enable dot position control with high accuracy than a clock period while performing digital control based upon a clock by using an ftheta characteristic storage means which store plural groups of ftheta characteristic data consisting of clock number data and delay stage quantity data. CONSTITUTION:The ROM 51 is used which stores plural groups of ftheta characteristic data differing in the largest number of delay stage while grouping ftheta characteristic data whose clock number data indicating the scanning positions of a laser beam close to respective dot positions on the scanning lines on a photosensitive body and delay stage number data stored in order in addresses corresponding to the respective dot positions. Groups of ftheta characteristic data corresponding to delay elements 61-64 of a delay means among plural groups of ftheta characteristic data stored in the ROM 51 are set with a DIP switch 60 to select the best groups of ftheta characteristic data. Consequently, the difference between the scanning position (laser beam projection position) and a correct dot position can be reduced and the ftheta characteristics are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a beam scanning recording device such as a laser printer.

(Prior Art) In a beam scanning type recording device, a photoreceptor is exposed to a laser beam that is emitted intermittently according to image information for each line of an image, and an image is recorded on paper by an electrophotographic process. A rotating optical deflector such as a polygon mirror is used to scan the photoreceptor with a laser beam. The laser beam records one line on the photoreceptor as a polygon mirror rotates, for example. The photoreceptor rotates in a direction perpendicular to this line direction. As the photoreceptor rotates, each line of the image is recorded on the photoreceptor, and the entire image is recorded.

Incidentally, the distance from the optical deflector to the photoreceptor varies depending on the position of the scanning line on the photoreceptor (for example, the center and both ends), and the scanning speed of the photoreceptor of the laser beam is not constant. Therefore, conventionally (J, in order to make the interval between each scanning position of the laser beam constant, the direction of the laser beam is corrected using an fO lens).

(Problem M to be solved by the invention) In a patent application separately disclosed by the present applicant, a memory storing fθ characteristics is used, and a digital circuit is used to operate a laser diode at a time interval (number of clocks) read from the memory. Gives a timing to emit light. This makes it possible to control the scanning position on the photoreceptor with good temperature characteristics without using an fO lens. In a beam scanning type recording device that records by scanning upward, clock number data and delay stage number data that give the scanning position of the laser beam close to each dot position for the dot position of the scanning line "-" on the photoreceptor are stored at each dot position. One set of fθ characteristic data is stored sequentially at addresses corresponding to
fθ characteristic storage means for storing a plurality of sets of fθ characteristic data having different maximum delay stages; a clock circuit for generating a reference clock; and a dot clock when the reference clock is counted by the number of clocks sent from the rθ characteristic storage means. A counter means and delay elements producing a delay time shorter than the cycle of the reference clock are connected in series, at least in such a number that the sum of the delay times is approximately equal to the monthly cycle, and the dots sent from the counter means are connected in series. A delay means for serially outputting a clock through delay elements of the number of delay stages, and a plurality of sets of rθ stored in an fθ characteristic storage means.
Among the set of characteristic data, the delay of the delay element of the delay means determines the projection position of the laser beam corresponding to the light emission timing determined by the time interval stored in the memory, that is, the actual dot position, the rotation speed of the polygon mirror, and the printer's rotation speed. The correct dot position determined by the dot density (for example, if 300 dpi) is usually not the same, and as long as control is performed using the clock as a reference, the difference between the two cannot be controlled to be less than the degree equivalent to the clock cycle.

In this sense, in order to reduce the difference between the two, it is best to shorten the clock cycle.
For example, if a reference clock of 20 M1 (z) is used, it is about 1/3 (:l).

An object of the present invention is to provide a laser beam scanning type recording apparatus that has a highly accurate rθ characteristic circuit that can control the actual dot position with higher precision than the clock cycle while performing digital control based on the clock. The purpose is to provide equipment.

(Means for Solving the Problem) A delay range specifying means for specifying a set corresponding to a characteristic, and an address specifying means for sequentially updating the address of the rθ characteristic storage means by dot blacks generated by the counter means. It is characterized by

(Function) A plurality of sets of fO characteristic data consisting of clock number data and delay stage number data are stored in the fO characteristic storage means (J), and the delay means stores the standard of the fθ characteristic circuit that provides the timing of light emission of the laser diode. Multiple clock signals with different timings are generated by connecting multiple delay elements in series with delay times shorter than the clock period.The delay characteristics of the delay elements may vary within a certain range. Therefore, the delay range specifying means specifies a set of rθ characteristic data suitable for the delay characteristics of the delay element actually used. Among the specified set of fθ characteristic data, the clock number data is It is determined to give a scanning position of the laser beam close to the dot position on the second scanning line.The counter means counts this number of clocks to generate an image lock and sends it to the delay means.The delay means According to the delay stage number data, the image clock is delayed so that the difference between the actual dot position and the correct dot position is further reduced, and the light emission timing is precisely controlled.

(Example) Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

(a) Standard Laser Printer System FIG. 2 is a diagram schematically showing a scanning system of a laser printer according to the present invention.

A laser beam (2) emitted from a semiconductor laser (la) in a laser head (1) is transmitted through a collimator lens (3).
), the light is made into parallel light and reflected by a reflective surface (4a) of a polygon mirror (4) that rotates at high speed.

This polygon mirror (4) is an example of a rotating optical deflector.
As the laser beam rotates, the incident laser beam becomes parallel light (
The inclination of each reflective surface (4a) with respect to 2) changes. As a result, the traveling direction of the reflected laser beam (2) is deflected, and the photosensitive tram (5) and the photosensor (6) are connected to each other. This photosensor (6) is illuminated by the laser beam (2) after being reflected by the polygon mirror (4).
It outputs a photocurrent when scanned at the beginning of a scanning line. This photocurrent is shaped by a waveform shaping circuit (11) and input as a synchronization signal [S OS ] (a) to an image control circuit (12).

In response to this synchronization signal [SOS] (a), the image control circuit (12) controls the scanning laser beam (2) after a certain period of time measured by the built-in timer, that is, the scanned laser beam (2) reaches the photosensor (6). After a time corresponding to reaching the recording start position on the photosensitive drum (5), a data request signal (b) is sent to the gearactor generator (+3), and image data (c) is received. Then, output of the image information (d) is started. Then, the laser drive circuit (14) receives this image information (d) and starts outputting an excitation current (e) to the semiconductor laser (la) based on the image information (d).

This synchronization signal [808] (a) is transmitted to the photoreceptor drum (5).
With respect to the rotating direction, that is, the sub-scanning direction, scanning is performed in the longitudinal direction of repetition as shown by the broken line (7) (this direction is the main scanning direction). This reflected laser beam (
In 2), an image is formed on a rotating photoreceptor tram (5) whose surface is uniformly charged, and the charged potential at the imaging position is attenuated in accordance with the intensity of the image.

On the other hand, the photoconductor drum (5), which is a cylindrical photoconductor, is configured to rotate at a constant speed in synchronization with the rotation of the polygon mirror (4) (this direction of rotation is the sub-scanning direction). ).

Then, as the photoreceptor drum (5) rotates, the scanning of the laser beam (2) described above is repeated, thereby forming an electrostatic latent image on the photoreceptor drum (5) according to the image information. It is.

Thereafter, although not shown in the drawings, a colored pigment, ie, a pigment, is selectively attached to this electrostatic latent image and developed.

Then, the output paper is brought into close contact with the toner adhesion surface to transfer the toner onto the paper surface. Furthermore, this toner is melted and fixed on the output paper by heating to obtain an output image.

In addition, the start position of the electrostatic latent image formed by the scanning of the laser beam (2) is aligned on the upper scanning side of the photoreceptor drum (5) to avoid occurrence of recording jitter. be.

On the other hand, inside the laser head (1) is a laser drive circuit (14).
) by the excitation current (e) from the laser beam (2
) At the same time, a photodiode (Ib) is provided which receives a laser beam (2) oscillated backward from a semiconductor laser (la). The output signal (f) from this photodiode (1b) is input to the laser drive circuit (14). Using the output signal (f) from this photodiode (1b), the power of the laser beam (2) oscillated forward from the semiconductor laser J' (la) is adjusted to compensate for changes in the temperature of the semiconductor laser (la). The configuration is such that the excitation current (e) to the semiconductor laser (Ia) is controlled so that it is always constant regardless of the current. Sampling of this laser power is performed by a sample halt signal (g) from the image controller/roll circuit (12).

(b) fo characteristic data In this embodiment, fθ correction is processed electrically.

FIG. 1, which will be explained later, shows an fθ characteristic correction circuit that is a part of the laser drive circuit (I4). In this circuit, R
The driving timing of the laser diode (Ia) is generated based on the fθ characteristic data stored in advance in the OM (51).

The fθ characteristic data stored in the ROM (51) will be explained next.

Now, if time t is expressed with reference to the time when the scanning line passes through the center of the photoreceptor, and the scanning position ρ of the laser beam is expressed with the center as reference, then the scanning position of the laser beam is as shown in Fig. 3. It is located at the position ρ-Ltan(wt). Here, the angular velocity of the polygon mirror (4) is set to w/2, that is, the angular velocity of the laser beam is set to W), and from the beam incidence position of the reflective surface (4a) of the polygon mirror to the photoreceptor (5).
Let L be the optical path length to the center position in the main scanning direction. Here, the rotation speed of the polygon mirror (4) is 5000 rpm, the optical path length 7 is 300 mm, and the reference clock is 20 MI (z).
is as follows.

Table 1 (1= 300 X jan(wt) w= 2 X 2πX 5000 rpm/ 6 G
sec/20 MH7X T5 236XIO-5T Now, assuming that the dot density of the printer is 300 dpi, the dot interval is 25.4/300 mm=84.7 μm. Therefore, the dot position near the center of the scanning line (N
=o, I, 2. -) and the scanning position after T clocks is the fourth
The result will be as shown in the figure. Here, in this embodiment, the number of clocks T giving the fO characteristic is the maximum integer that does not exceed the dot position, that is, 847XN≧300Lan (5, 23
6XlO-5T), the largest integer 'r (=0.5.
The number of clocks T' (= 5
. The table shows the clock T, the distance ρ from the center at this time, and the difference ΔQ from the tosoto position.

In the following Kinpaku example, as shown in FIG. 5 which shows the basic structure of the delay circuit, a delay means is provided in which, for example, four stages of delay elements (61 to 64) are connected in series with respect to the reference clock signal. Clock signals φI to φ4 are taken out from each stage. Now, if the reference clock is 20 MHz (period: 50 ns) and the delay time of each delay element is 1° ns, a clock signal that is substantially five times as large as that shown in FIG. 6 can be obtained.

Therefore, if you specify the maximum clock number data T(N) and delay stage number data L(N) that do not exceed the Nth dot position, Q-300tan(wX CT +t/5)
). Table 3 shows the data T(N) at each dot position.
T'(N), t(N) and the difference ΔQ are shown. Here, T'
(N) is the number of clocks representing the interval between each scanning position.

The difference Δρ is at most about the delay time, that is, about 36% or less. In this way, the difference Δρ between the scanning position (laser beam projection position) and the correct dot position can be reduced to about 115, and f
The θ characteristics are significantly improved.

As a delay element, for example, an inexpensive high-speed 0MO8 element 7 is used.
4 Using HCOO. The propagation delay characteristics of an IC generally vary depending on the manufacturing lot, operating temperature, operating voltage, etc., but if elements in the same package are used, the characteristics can generally be made uniform to some extent. Therefore, delay elements within the same package are used.

Table 4 below shows rθ characteristic data (T').
1) shows fθ characteristic data consisting of clock number data (T”l) and delay stage number data t to be stored. fθ
The characteristic data is stored at address 80 (
l Stored from H. Clock number data (T' -1
) is stored in the 3 bits from the 5th pit to the 3rd hit, and the delay stage number data t is stored in the 3 bits from the 2nd bit to the 0th bit.

The number of clocks (T''-1) is one more than the data set in the dot clock counter (57) in the circuit configuration shown in FIG. 1, so it is one less than the data in Table 3. The number of delay stages t corresponding to T'-1)
In the circuit configuration shown in FIG. 1, is written to the next address in consideration of data input timing.

What determines the time accuracy of the dot clock signal generated by the delay circuit is the delay characteristic of the delay element.

For example, when an inexpensive TTL-IC is used as a delay element, there are large variations in the delay time. for example,
74 L S 24.4. (3-state output storage ROM (5)) stores data corresponding to each division number.

For example, in the example shown in FIG. 7, four sets of fθ characteristic data for three divisions, four divisions, five divisions, and six divisions are sequentially stored in the ROM (51). Then, as shown in Figure 1, by setting the upper two bits (A10 and A11) of the address to the number of divisions that match the delay time of the delay element using the DIP switch (60), the optimum rθ characteristic data can be obtained. You can select a set of In this embodiment, as shown in FIG.
, stored from C0OH, lower 10 bits (A9 to AO)
is designated by the ROM address counter (55).

In this embodiment, the number of clocks and the number of delay stages may be set to the maximum value that does not exceed the dot position, or may be determined by an appropriate method depending on the nature of the image. For example, in a variant embodiment N
At the clock number T(N) at the position closest to the dot position, that is, the buffer), the transmission delay time of L level → H level and I (level − L level) are both 18ns max, typically 1
2 ns, and no minimum time is specified.

For example, when data calculated using the delay time of a delay element as 10 ns is used, the best accuracy can be obtained if the actual delay time is 10 ns. However, if the actual delay time is as short as 7 ns or as long as 13 ns, the difference Δρ from the dot position will be approximately twice as large as in the best case. The greater the difference between the calculated delay time and the actual delay time, the greater the difference ΔQ from the dot position.

Therefore, it is necessary to use data on the number of delay stages that matches the delay time of the delay element actually used.

Therefore, in this embodiment, a plurality of types of the number of divisions (delay range) of the reference clock can be set, and the number that best matches the delay time of the actual delay element is set among them. The rθ characteristic data is written as the difference Δρ− from the driver 1 position.
Find T at which the absolute value 1Δg1 of Nx25.4/300-300XwXT(N) is minimized. Table 6 shows the data when using a delay circuit consisting of a delay element with a delay time of 3 ns, that is, the clock number data T' and the delay stage number data (1) when the reference clock is substantially divided into four. show.

In this method, the difference ρ from the dot position takes a positive or negative value depending on whether it is closer to or farther from the center than the dot position. Then, the obtained value of the clock interval T'' is stored in the ROM (51).

The following margins are shown in Table 5, Table 6, and Figure 5. When a delay element with a delay time of 10 ns is used to create a clock with substantially 5 times the frequency, as shown in Table 6, from the center The number of clocks 'r(N) from the central position closest to the Nth dot position and the number of delay stages L(N) for the Nth dot are calculated. At this time, the difference ρ from the dot position is Nx25.4/300-300
xtan(wx(T(N)+(10150)t(N))
). ) The error with the head position is within the range of about ±19%.

Margin below Also, Tables 7 and 8 each have a delay time of 7 ns.
The number of clocks 'r(N) and the number of delay stages t(N) when using a delay circuit consisting of 13118 delay elements are shown. In these cases, the error Δg between the clock frequency (Jl is effectively 7 times and 4 times, respectively) and position is ±1
It is within the range of about 3% and ±24%. Note that the number of delay elements required to configure the delay circuit is as follows:
There will be 7 pieces and 4 pieces.

Furthermore, in the second example, the delay elements were selected so that the delay time was one integer fraction of the period of the reference clock. However, even if it is not necessarily a fraction of an integer (for example,
Even if it is 1/45), the fθ characteristics can be improved.

Table 7 (c) fθ characteristic correction circuit Below, fθ characteristic correction using the ROM (51) storing the data shown in FIG. 7 will be explained.

In the fθ characteristic correction circuit shown in FIG. ), the LSTRT signal is generated.

That is, the first flip-flop (52) is set to a high level immediately upon receiving the synchronization signal [SOS] (a) as a clock signal. The second flip-flop (53) converts the output signal of the first flip-flop (52) into a clock signal [C
Output in synchronization with LK]. This output signal serves as a signal for clearing the first flip-flop circuit (52) and also serves as the LSTRT signal. Therefore, L.S.
The TRT signal is output during one period of the clock signal [CLK].

The ROM address counter (55) generates ROM address signals A9-A Table 8 which give the address of the ROM (51). On the other hand, the DIF switch (60) is set to, for example, AI1="0" and Al0-"BI. Therefore, fθ characteristic data in the case of four divisions (fourth
table) is selected. The above LSTRT signal clears the ROM address counter (55) via the OR gate (56).

Therefore, addresses A9 to AO of ROM (51) are
It returns to "0" in synchronization with the SO8 synchronization signal. In addition, in the case of the first line of the page, press RESE before printing.
The T signal is input through the OR gate 56, and the ROM address -AO is "0".

At this time, the ROM (51) transfers the clock number data T'-1 at the address "800H" to the dot clock counter (51).
7). At the same time, the above LSTRT signal is
Dot clock counter (5) via R gate (58)
7) is sent to the LOAD terminal, and this clock number data T
'-1 is preset in the dot clock counter (57) as an initial value.

This value is subtracted by one each time a clock signal is received from the clock circuit (54). Count value is °゛0″
When the temperature is reached, a ripple clock output signal [RC] is generated. This ripple clock signal [RC] is output with a pulse width equal to the period (50 ns) of the clock signal [CL Kl, for example, and is output through a total of four stages of delay elements (61 to 61).
64) connected in series.

This ripple clock signal [RC] is simultaneously applied to the ROM
The ripple clock signal [RC] is sent as a clock signal to the address counter (55), and the ROM address is incremented by one to 801H''. is sent to the LOAD terminal.This causes the ROM (51)
Clock number data (T'-
1) is preset in the dot clock counter (57). Similarly, the dot clock counter (57)
The clock signal [CL
Ripple clock signal [RC]
is generated.

Thus, the rising edge of the dot clock signal output from the OR gate (70) is synchronized with the rising edge of the signal φ0 (RC), and the falling edge of the dot clock signal is synchronized with the rising edge of the signal φ0 or the selected delayed clock signal (φl). to φ4). The fall of this dot clock signal provides the timing for the laser diode (1a) to emit light.

Therefore, when the characteristics of the delay elements (61 to 64) are aligned, correct fθ characteristics can be obtained except for slight errors as shown in Table 3.

Note that the actual delay time is further determined by the individual AND gates (
65 to 69), therefore, it is preferable to reduce the variation in delay time by using AND gates within the same pankeno.

FIG. 8 shows a timing diagram from the time when the center of the photosensitive drum (5) is scanned. For convenience of explanation, the address output by the ROM address counter (55) is set to 8001-I in the center. In addition to the ripple clock signal [RC] (also called φ0), 4
Stage delayed clock signals φl-φ4 are generated. These ripple clock signal φO and delayed clock signal φl~
φ4 is the corresponding AND gate (65 to 69
), and when each AND gate is opened, it is sent to an OR game 1-(70) having five input terminals. The signal φ0 is output to O via an AND gate (65).
It is output to the R-gate (70). On the other hand, ROM(5
The delay stage number data t in 1) is determined by the decoder/latch circuit (7
1) and latched at a timing slightly delayed from the falling edge of the ripple clock signal [RC]. Then, four signals (IEN, 2EN, 3EN, 4
．． EN) and the AN of the corresponding number of delay stages.
It is sent to the other input terminal of D game 1-(66-69). Therefore, the signal representing the number of delay stages (] EN, 2E
Only the eight NI) gates selected by N, 3EN, 4EN) OR the delayed clock signals φ1 to φ4 (70
). When the clock counter (57) outputs the ripple clock signal [RC], if the count value of the ROM address counter (55) is °'0',
The count value increases to "B" and is sent to the ROM (51) using the ROM address signals -9 to AO.
The OM (51) sends 4° to the dot clock counter (57) as the clock number data (T'-1) of the address "8011(".Then, the rising edge of the ripple clock signal [RC] to be output next is On the downhill, this clock number "4"
” is set in the dot clock counter (57).The dot clock counter (57) receives the clock signal [CL
K] is counted down, and the count value becomes “°0°
A triple clock signal [RC] is output. Then, at the falling edge of the ripple clock signal [RC], R
The count value of the OM address counter (55) becomes "2", and the ROM (51) outputs the address "3, which is the number of delay stages t of '8021ZE" to the decoder/latch circuit (71), and the decoder/latch circuit ( 71) launches this data and enables the decode signal 3EN. Therefore, the logical sum of the ripple clock signal [RC] and the signal φ3 is output from the OR gate (70) as a dot clock. That is, the falling edge of the dot clock coincides with the falling edge of the signal φ3. This dot clock exhibits fθ characteristics with errors shown in Table 3.

Note that although the above description has been about scanning from the center, the operation from the start of scanning to the center is performed in the same way.

When the laser beam (2) is within the image area of the photoreceptor (5), the laser drive circuit (14) receives the dot clock from the character generator (I3) in synchronization with the dot clock sent from the internal fθ characteristic correction circuit. Image information (d
), outputs a timing signal (e) for driving the laser diode (la).

(Effect of the invention) Even if an inexpensive TTLIC or the like with some variation in characteristics is used as a delay element without using an expensive and accurate delay element, it is possible to select an appropriate set of fθ characteristic data from among multiple sets of fθ characteristic data. By specifying the fθ characteristic, a certain degree of time accuracy can be ensured.

61-64...delay element, φO to φ4...Clock signal.

Claims (1)

[Claims] (1) In a beam scanning recording device that scans and records a laser beam emitted according to image information onto a photoconductor using an optical deflector, a laser beam close to each dot position on a scanning line on the photoconductor is used. One set of fθ characteristic data is obtained by sequentially storing clock number data giving the beam scanning position and delay stage number data in addresses corresponding to each dot position, and multiple sets of fθ characteristic data having different maximum delay stage numbers are stored. f
θ characteristic storage means, a clock circuit that generates a reference clock, a counter means that generates a dot clock when the reference clock is counted by the number of clocks sent from the fθ characteristic storage means, and a delay time shorter than the period of the reference clock is generated. A number of delay elements are connected in series such that at least the sum of the delay times is approximately equal to one cycle, and the dot clock sent from the counter means is passed through the delay elements of the number of delay stages in series. a delay means for outputting fθ characteristic data, a delay range specifying means for specifying a set corresponding to the delay characteristic of the delay element of the delay means among the plurality of sets of fθ characteristic data stored in the fθ characteristic storage means, and a counter means. 1. A beam scanning type recording apparatus comprising: address designating means for sequentially updating the address of the fθ characteristic storage means based on a generated dot clock.