JP2011227250A - Image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image display device that improves an image quality by generating a pixel clock of a variable period different in pulse width in response to drive of scanning means.SOLUTION: An image display device 1 displaying an image by scanning light from a laser light source 25 by a MEMS mirror 55 includes a variable clock generating section 30 that generates a pixel clock of a variable period different in pulse width in response to the drive of the MEMS mirror 55 for every pixel of a display image by varying the number of stages of delay sections provided to have a plurality of stages, a delay number-of-stages selector 40 that outputs a control signal for selecting the number of stages of the delay section to the variable clock generating section 30 and an image data buffer 10 that receives a fixed-period clock, an image signal that is synchronized with the fixed-period clock, and the pixel clock of the variable period and outputs an image signal in synchronization with the pixel clock of the variable period to a laser driver circuit 20.

Description

  The present invention relates to a scanning image display apparatus.

  2. Description of the Related Art Conventionally, an image display device that drives a MEMS (Micro Electro Mechanical Systems) mirror irradiated with light such as laser light at high speed is known. In such an image display device, the drawing range may be raster-scanned by non-resonant driving in the vertical direction and resonant driving in the horizontal direction. In this case, the scanning in the horizontal direction fluctuates in a sinusoidal manner by resonance driving, and this scanning speed is the fastest at the center in the horizontal direction of the screen and the slowest at the side. For this reason, if a fixed clock is used, the pixels are coarser in the center of the screen, and the pixels become denser as the screen ends, resulting in nonuniform pixel display positions and brightness.

  Therefore, it is conceivable to generate a signal whose phase is shifted in accordance with the pixel position, such that the period becomes shorter as it goes toward the center of the screen and becomes longer as it goes toward the edge of the screen as the horizontal synchronization signal. For example, Patent Document 1 discloses a circuit that prepares a clock having a frequency twice that of a write clock and generates a clock having four types of phase differences by a flip-flop.

JP-A-6-121139 ([0007], FIG. 8)

  According to such a circuit, it is possible to generate a clock having a frequency twice as high as that of the writing clock and having a phase shifted from the original clock. It is considered possible. In this case, pixel and luminance non-uniformities are alleviated as compared to using a fixed clock. However, in such a circuit, since it is difficult to generate a very small phase delay with respect to the original clock, it is required to generate the clock with higher accuracy.

  In addition, although the case where the MEMS mirror was used as the scanning means of the image display device has been described, the non-uniformity of pixels and luminance is not limited to the image display device using the MEMS mirror, and other scanning such as a polygon mirror, for example. This is also common to image display devices using means.

  SUMMARY An advantage of some aspects of the invention is to solve the above-described problems and to provide an image display device that can solve these problems. For the purpose.

  In order to solve the above-described problem, an image display device according to a first aspect of the present invention is an image display device that displays an image by scanning light from a light source with a scanning unit. A variable clock generation unit that generates a pixel clock having a variable period with a different pulse width according to driving of the scanning unit by changing the number of delay units connected in series in a plurality of stages for each pixel, and the variable clock generation unit A delay stage number selection unit that outputs a control signal for selecting the number of stages of the delay unit, an image signal and a pixel clock of the variable period are input, and an image signal synchronized with the pixel clock of the variable period And a buffer for image data to be output to the light source.

It is a block diagram which shows the structure of the image display apparatus which concerns on one embodiment of this invention. It is a block diagram which shows the structure of the image display apparatus which concerns on one embodiment of this invention. It is a block diagram which shows the structure of the variable clock generation circuit of the image display apparatus which concerns on one embodiment of this invention. It is a circuit diagram which shows the structure of the variable clock generation circuit of the image display apparatus which concerns on one embodiment of this invention. 6 is a timing chart in the variable clock generation circuit of the image display device according to the embodiment of the present invention. It is a block diagram which shows the structure of the delay stage number selection part of the image display apparatus which concerns on one embodiment of this invention. It is a block diagram which shows the structure of the delay stage number selection part of the image display apparatus which concerns on one embodiment of this invention. It is a circuit diagram which shows the structure of the variable clock generation circuit of the image display apparatus which concerns on other embodiment of this invention.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings. For the sake of convenience, the same reference numerals are given to the portions having the same operational effects, and the description thereof is omitted.

  FIG. 1 is a block diagram showing the basic concept of an embodiment of the present invention. In the image display apparatus 1 according to the present embodiment, a pixel clock having a fixed period and image data synchronized with the pixel clock are input to the image data buffer 10, and a scanning unit (not shown in FIG. 1) is input from the image data buffer 10. A variable period pixel clock, which is a set of signals having different pulse widths according to driving, and image data synchronized therewith are output to the laser driving circuit 20. Here, the pixel clock having a variable period is generated according to the driving period of the scanning unit, and is generated by the variable clock generation circuit 30 including a delay circuit capable of generating an arbitrary delay amount. At this time, the delay amount of the delay circuit is selected by the delay stage number selection unit 40 for each pixel, so that a pixel clock having a variable period in which the delay of each signal is adjusted is generated. Note that the variable clock generation circuit 30 can include a calibration circuit for increasing the accuracy of the delay amount.

  FIG. 2 is a block diagram showing FIG. 1 more specifically. In this example, the scanning unit is a MEMS mirror 55 that is controlled by a mirror drive circuit 50. The MEMS mirror 55 is driven in a non-resonant manner in the vertical direction and in a resonant direction in the horizontal direction. Are raster scanned. The vertical synchronization signal V-Sync and the horizontal synchronization signal H-Sync used for driving control of the MEMS mirror 55 are generated by a synchronization signal generation circuit provided in the variable clock generation circuit 30, and the mirror position detection unit 60. The amplitude of the MEMS mirror 55 is controlled to be constant by feeding back the signal detected by the above to the synchronization signal generating circuit.

  The light applied to the MEMS mirror 55 is laser light from a laser light source 25 such as an LD (Laser Diode), and the laser light source 25 is controlled by the laser driving circuit 20. The control signal input to the laser drive circuit 20 is output from the modulation signal generator 11 (including the image data buffer 10 in FIG. 1). The modulation signal generation unit 11 includes a FIFO-RAM having a RAM capacity equal to or greater than that of the horizontal pixels, and receives image data such as analog RGB signals as input data, and pixels with variable periods from the variable clock generation circuit 30. A clock and a vertical synchronization signal V-Sync are input. As a result, the laser drive circuit 20 reads out the vertical synchronization signal V-Sync, the variable period pixel clock, and the image data synchronized with these from the FIFO-RAM, and the laser drive current is modulated on the basis of these and the laser light is modulated. Is adjusted.

  The variable clock generation circuit 30 has a delay circuit in which a plurality of delay units are connected in series. As a result, the clock is extracted at an arbitrary number of stages, and a pixel clock having a variable period with a different pulse width according to the resonance driving of the MEMS mirror 55 is generated.

  The variable clock generation circuit 30 receives a signal for selecting the number of stages of the delay unit from the delay stage number selection unit 40, and selects the delay stage number for each pixel in accordance with the signal, so that variable periods having different pulse widths are selected. Pixel clocks are generated. The delay stage number selection unit 40 can select an arbitrary number of delay stages each time the horizontal line of the pixel clock generated by the variable clock generation circuit 30 changes.

  3 and 4 are a block diagram and a circuit diagram of the variable clock generation circuit 30 in FIG. 2, FIG. 5 is a timing chart in the variable clock generation circuit 30, and FIG. 6 is a block diagram for explaining the delay stage number selection unit 40. is there. 3 and 4, the synchronization signal generation circuit is omitted. In this embodiment, as an example, the horizontal drawing rate (effective scanning rate) K is 0.9, the number of horizontal pixels N is 640 pixels, and the horizontal scanning frequency f is 15720.5524 Hz. Note that the horizontal drawing rate refers to the proportion of the drawing range in the horizontal direction that is actually used for drawing. Further, the horizontal scanning frequency f is the resonance frequency of the MEMS mirror 55.

  Since the MEMS mirror 55 as the scanning unit is driven in the horizontal direction by sinusoidal vibration, the period of the horizontal synchronizing signal varies depending on the pixel position, and the period Tc of the pixel at the center of the screen is expressed by Expression (1). Yes, in this embodiment, it is about 28.5 ns (nanoseconds).

  Further, the period Te at the screen edge is expressed by the equation (2), which is about 65.4 ns in the embodiment, which is about 2.3 times the period Tc at the center of the screen.

  The period at an arbitrary pixel position Nx from the center of the screen is expressed by Expression (3). Since “Nx” is a pixel position from the center of the screen, “Nx” at both ends of the screen is −320 at the left end and 320 at the right end.

  In the variable clock generation circuit 30, a plurality of DFFs (Delay Flip-Flop) that generate a count start trigger in synchronization with the horizontal synchronization signal H-sync and DFFs that count the number of system clocks from the start of counting are connected in series. Accordingly, a delay generation circuit 32 that can generate a delay of a clock corresponding to the horizontal scanning time of the MEMS mirror 55 at the maximum and a delay element as a delay unit are connected in series in a plurality of stages, whereby the delay generation circuit 32 is a maximum. In the embodiment, a calibration circuit 36 used for calibration of the precision delay generation circuit 34 is further provided. . The clock generated by the delay generation circuit 32 is input to the precision delay generation circuit 34.

  With such a configuration, a delayed clock is generated in each pixel by combining the delay by the delay generation circuit 32 and the delay by the fine delay generation circuit 34. Then, by outputting the clock in each pixel through the OR gate, a continuous pixel clock (pixel clock having a variable period) having a different period for each pixel is generated. The delay element in the precision delay generation circuit 34 is calibrated by the calibration circuit 36 because the delay time changes due to temperature change.

  In the embodiment, since the period at the center of the screen (that is, the earliest period of the synchronization signal) is about 28.5 ns, the frequency of the system clock is set to 50 MHz so that the delay amount by 1 DFF is smaller than this, for example, 20 ns. is there. In this case, since the horizontal scanning time is 22.650 μs (microseconds), the delay generation circuit 32 requires at least 1132 DFFs. In the delay generation circuit 32, a delay is added by 20 ns every time one DFF is passed, so that a clock delayed by an accuracy of 20 ns can be generated by extracting a clock with an arbitrary number of DFF stages.

  In the embodiment, one end of the screen is used as the first pixel and is scanned in the horizontal direction toward the other end. In this case, since the pixel position of the first pixel from the center of the screen is 320, the period from the first pixel to the next pulse is about 65.3 ns, about 64.5 ns, in order from the first pixel according to Equation (3). About 63.7 ns, about 62.9 ns, and so on. This is about 65.3 ns, about 129.8 ns, about 193.5 ns, about 256.4 ns, and so on when converted to the elapsed time from the start of output, and this is the period of the pixel clock having a variable period that is desired to be generated.

  Therefore, when the horizontal synchronization signal H-Sync is input, the signal output from the delay generation circuit 32 to the fine delay generation circuit 34 as the clock for the first pixel is based on the sum of the delay amount due to the DFF in 65.3 ns. 60ns, which is the maximum value that can be generated, is extracted from the third stage. Similarly, the clock for the second pixel is 120ns from the sixth stage, and the clock for the third pixel is 180ns from the ninth stage to the fourth stage. As for the clock of the pixel, 240 ns is extracted from the 12th stage. By extracting the clock up to the 640th pixel clock, a clock for one horizontal scan is output to the precision delay generation circuit 34. As described above, since the delay amount (20 ns) by one DFF is set to be smaller than the earliest period (about 28.5 ns) of the pixel clock, the clock for 640 pixels is always extracted from the number of different DFF stages. Will be.

  In the illustrated example, one precision delay generation circuit 34 is provided for each pixel of 640 pixels in the horizontal direction, and each clock corresponding to 640 pixels generated by the delay generation circuit 32 corresponds to each precision. Input to the delay generation circuit 34. In the embodiment, the precision delay generation circuit 34 has a required number of stages of delay elements having a delay amount of 100 ps per stage so that a delay is generated with an accuracy of 100 ps (picosecond), for example. The delay amount can be generated with an accuracy of 100 ps. As a result, a delay of 20 ns corresponding to one cycle of the system clock can be generated at the maximum. Note that the delay element in the embodiment is configured by two CMOS inverters in one stage so that the logic is not inverted. The precision delay generation circuit 34 adds a delay of 100 ps each time one delay element is passed, so that a delay of 100 ps at the minimum and 19.9 ns at the maximum is generated by extracting the signal with the delay elements of an arbitrary number of stages. Can be made.

  The number of stages of delay elements in the precision delay generation circuit 34 is 200 stages if only the standard state is considered. However, as described later, the delay element changes its delay time due to a temperature change or the like. Therefore, when the delay time of the delay element changes so as to be shortened (for example, in a low temperature state), the number of stages greater than 200 is larger. Necessary. For example, if the delay time per delay element is assumed to be shortened to 99 ps, 202 stages are required, and the delay time per delay element is assumed to be shortened to 90 ps. Requires 222 stages.

  In the precision delay generation circuit 34, the remaining delay of less than 20 ns that cannot be generated by the delay generation circuit 32 is generated. That is, in the first pixel, 60 ns is generated by the delay generation circuit 32 with respect to the delay of 65.3 ns, so that the remaining 5.3 ns is generated by the fine delay generation circuit 34. In this case, since the delay amount per stage of the delay elements is 100 ps, the number of stages of delay elements from which signals are extracted is the 53rd stage. Similarly, in the second pixel, 9.8 ns out of the 129.8 ns delay is from the 98th stage, and in the third pixel, 13.5 ns out of the 193.5 ns delay is from the 135th stage, and the fourth pixel is 256.4 ns. Of the delay, 16.4 ns is from the 164th stage, so that signals are extracted for all 640 pixels. Note that the number of stages from which the signal is extracted in the precision delay generation circuit 34 is controlled by the delay stage number selector 40. That is, the delay stage number selection unit 40 enables only the number of stages from which a signal is to be extracted, and disables the other stages. The delay signal output from the delay element is input to the clock pulse generation delay circuit 34a, and a delay corresponding to the clock pulse width is added. Then, by taking an exclusive OR of the input signal and the output signal of the clock pulse generation delay circuit 34a, a pulse is generated for a fixed time starting from the delay time generated by the delay element, and becomes a clock pulse in each pixel. Then, the logical sum output of the clock pulses in each pixel of these 640 becomes a variable period pixel clock.

  The timing chart in FIG. 4 shows this state up to the fourth pixel. When the horizontal synchronization signal H-Sync is input, the count start trigger by the 0th stage DFF is turned ON, and delay generation by the delay generation circuit is started. Then, the 53rd stage output of the precision delay refinement circuit obtained by further adding the 53rd stage delay of the precision delay generation circuit 34 to the delay of the 3rd stage DFF of the delay generation circuit 32 (the 3rd stage output of the delay generation circuit), and this A clock pulse for the first pixel, which is an exclusive OR with the output of the delay circuit for clock pulse generation in which a delay corresponding to the clock pulse width is added to the output, is generated. Similarly, a second pixel clock pulse or less is generated, and a variable-period pixel clock is generated as a logical sum of these.

  The delay stage number selection unit 40 includes a plurality of lookup tables (LUT1 to LUT3 in the illustrated example), and corresponds to each pixel of 640 pixels according to the lookup table selected by the lookup table selector 45. Whether to enable or disable is selected for each number of stages of delay elements. Note that which lookup table is selected depends on the state of the delay element, and is determined by the result of the calibration circuit 36. In the embodiment, the selection signal by the lookup table selector 45 is sent to the enable signal selector corresponding to each pixel 1 to 640 so that the enable signal selector refers only to the selected lookup table. It is composed.

  The calibration circuit 36 is used for calibration of the precision delay generation circuit 34. Even if a CMOS inverter that is a delay element constituting the precision delay generation circuit 34 generates a delay of 100 ps in the standard state, for example, the delay time is long at a high temperature and the delay time is short at a low temperature. The delay time changes due to a temperature change or the like. For this reason, in the standard state, the same delay can always be generated by extracting a signal from a predetermined number of stages. However, in order to generate the same delay when a temperature change or the like occurs, the number of stages must be changed. There is a case. In this case, the number of stages to be changed can be determined by estimating (calculating) the delay time per stage of the delay element by the calibration circuit 36.

  The calibration circuit 36 includes a comparison delay circuit 37 that can generate a delay of one cycle or more of the system clock by connecting a plurality of delay elements that are the same as the delay elements used in the precision delay generation circuit 34 in series. The system clock input to the comparison delay circuit 37 and the delayed clock extracted from an arbitrary number of stages of the comparison delay circuit 37 are, for example, output by a phase comparator 38 including an exclusive OR gate and a low-pass filter. To compare.

  When the phase difference between the delayed clock extracted through the 200-stage delay element and the system clock is the smallest among all, according to the comparison result of the phase comparator 38, the temperature condition etc. For example, the delay time per stage of the delay element is calculated to be 100 ps (20 ns / 200 stages) by a calculation unit including a CPU.

  Further, for example, when the phase difference between the delayed clock extracted through the 198-stage delay element in the comparison delay circuit 37 and the system clock is the smallest among all, the 198-stage delay Since it is considered that 20 ns is generated by the element, the delay time per stage of the delay element is calculated to be 101 ps (20 ns / 198 stages) by the arithmetic unit.

  Similarly, for example, when the phase difference between the delayed clock extracted through the 202 delay elements in the comparison delay circuit 37 and the system clock is the smallest of all, the 202 stages Since it is considered that 20 ns is generated by the delay element, the delay time per stage of the delay element is calculated to be 99 ps (20 ns / 202 stages) by the arithmetic unit.

  In this way, the phase comparator 38 compares the delayed signal of each stage number in the comparison delay circuit 37 with the system clock, thereby calculating the delay time per stage of the delay element. Then, this result is input to a lookup table selector 45 in the delay stage number selector 40, and the lookup table selector 45 selects an optimum lookup table corresponding to the delay time from among a plurality of lookup tables. Will choose. If the state of the delay element can be grasped by a phase comparator or the like, it is not always necessary to calculate the delay time per stage of the delay element, and the look-up table selector 45 determines the optimum look according to the state of the delay element. It doesn't matter if you can select an uptable.

  The operations of the calibration circuit 36 and the lookup table selector 45 will be described more specifically. As a premise, as shown in FIGS. 6 and 7, the look-up table in the look-up table selector 45 corresponds to the case where the delay time per stage of the delay elements is 99 ps, 100 ps and 101 ps. It is assumed that three types of LUT1, lookup table LUT2, and lookup table LUT3 are prepared. Note that the types of look-up tables are not limited to three, but are prepared in accordance with changes in the delay time assumed for the delay elements. For example, in the embodiment, when a change of ± 10 ps is assumed in the delay time of the delay element, 11 types of delay times per stage may be prepared for 90 ps to 110 ps. Thus, the type of the lookup table is prepared when the number of extraction stages in the precision delay generation circuit 34 changes due to the change in the delay time, and the type is not limited.

  As described above, delays to be generated by the variable clock generation circuit 30 are approximately 65.3 ns, approximately 129.8 ns, approximately 193.5 ns, and so on in order from the first pixel. In the delay generation circuit 32, the clock for the first pixel is extracted from the third stage (60 ns) of the DFF, the clock for the second pixel is extracted from the sixth stage (120 ns) of the DFF, and the clock for the third pixel is extracted from the ninth stage (180 ns) of the DFF. This is input to the precision delay generation circuit 34. In this case, the delay to be further added by the precision delay generation circuit 34 is 5.3 ns for the first pixel, 9.8 ns for the second pixel, 13.5 ns for the third pixel, and so on.

  Here, for example, when the delay time per stage of the delay element is calculated to be 100 ps equivalent to the standard state by the calibration circuit 36, each pixel of the LUT2 selection signal 1 to 640 is calculated by the lookup table selector 45. The enable signal selector is connected to each enable signal selector and the lookup table LUT2. Here, in the lookup table LUT2, the number of delay stages when the delay time per stage of the delay elements is 100 ps is enabled. That is, in the precision delay generation circuit 34 for the first pixel, the 53rd stage (5.3 ns = 100 ps × 53 stages), and in the precision delay generation circuit 34 for the second pixel, the 98th stage (9.8 ns = 100 ps × 98). In the fine delay generation circuit 34 for the third pixel, the 135th stage (13.5 ns = 100 ps × 135 stage) is enabled, and the others are disabled. As a result, the optimum number of delay stages is selected in the precision delay generation circuit 34 for each pixel of 640.

  For example, if the calibration circuit 36 calculates that the delay time per stage of the delay element is 101 ps, which is longer than the standard state, the lookup table selector 45 sets the LUT3 selection signal for each pixel of 1 to 640. Each enable signal selector is connected to the look-up table LUT3 (FIG. 7 shows the state at this time). Here, in the lookup table LUT3, the number of delay stages when the delay time per stage of the delay elements is 101 ps is enabled. That is, in the fine delay generation circuit 34 for the first pixel, the 52nd stage (5.3 ns≈101 ps × 52 stages), and in the precision delay generation circuit 34 for the second pixel, the 97th stage (9.8 ns≈101 ps × 97). In the fine delay generation circuit 34 for the third pixel, the 134th stage (13.5 ns≈101 ps × 134 stage) is enabled, and the other stages are disabled. As a result, the optimum number of delay stages is selected in the precision delay generation circuit 34 for each pixel of 640.

  Similarly, for example, if the calibration circuit calculates that the delay time per stage of the delay element is 99 ps, which is shorter than the standard state, the lookup table selector 45 sets the LUT1 selection signal for each pixel of 1 to 640. Each enable signal selector is connected to the lookup table LUT1. Here, in the lookup table LUT1, the number of delay stages when the delay time per stage of the delay elements is 99 ps is enabled. That is, in the fine delay generation circuit 34 for the first pixel, the 53rd stage (5.3 ns≈99 ps × 53 stages), and in the precision delay generation circuit 34 for the second pixel, the 99th stage (9.8 ns≈99 ps × 99). In the fine delay generation circuit 34 for the third pixel, the 136th stage (13.5 ns≈99 ps × 136 stage) is enabled, and the others are disabled. As a result, the optimum number of delay stages is selected in the precision delay generation circuit 34 for each pixel of 640.

  In this way, the lookup table selector 45 selects the optimum lookup table in response to the phase comparison result in the calibration circuit 36, so that a delay of less than 20 ns that could not be produced by the delay generation circuit 32 is generated as a precise delay. It is generated by the circuit 34 with high accuracy. By combining the delay by the delay generation circuit 32 and the delay by the fine delay generation circuit 34, a delay signal corresponding to each pixel position is generated. This delay signal is further delayed by a clock pulse generation delay circuit 34a. The exclusive OR of the input signal and the output signal of the clock pulse generation delay circuit 34a becomes a clock pulse in each pixel. A logical sum output of clock pulses in each pixel becomes a pixel clock having a variable period.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to these embodiments, and the design can be changed without departing from the scope of the present invention. Is included in the present invention. For example, the specific circuit configuration is not limited to the embodiment, and can be appropriately changed as shown in FIG. 7, for example. FIG. 8 focuses on the fact that the clock of each pixel has a phase difference of at least one cycle of the system clock. That is, even if a fine delay generation circuit is prepared for each pixel as in the embodiment, these are not used at the same time, so that these fine delay generation circuits can be combined into one. In this example, a delay stage number selection enable signal for each pixel and a decode circuit are added, and the precision delay generation circuit 34 is shared by each pixel.

  Moreover, although the example which used the MEMS mirror as a scanning part was shown, it is not limited to this, For example, you may use a polygon mirror as a scanning part. When the polygon mirror irradiated with the laser light from the light source is two-dimensionally scanned, the scanning speed of the laser light varies depending on the scanning position when the polygon mirror is rotated at an equiangular speed. Therefore, the optimum image data can be read by generating a variable clock according to the scanning speed.

  In addition, although an example using a delay element constituted by a CMOS inverter as a delay unit has been shown, the present invention is not limited to this. For example, other methods can be used as long as a predetermined delay can be generated, such as a delay circuit using a resistor and a capacitor. A delay unit may be configured. In addition, although an example in which the delay amount per stage of the delay element is 100 ps is shown, the present invention is not limited to this and can be appropriately determined depending on the required accuracy.

  Further, the values of the horizontal drawing rate, the number of horizontal pixels, the horizontal scanning frequency, etc. are not limited to those in the embodiment. Further, when these values are changed, the delay time per stage of the DFF is adjusted. The frequency of the system clock is also changed as appropriate.

DESCRIPTION OF SYMBOLS 1 Image display apparatus 10 Image data buffer 11 Modulation signal generation part 20 Laser drive circuit 25 Laser light source 30 Variable clock generation circuit 40 Delay stage number selection part 55 MEMS mirror (scanning part)

Claims (5)

An image display device that displays light by scanning light from a light source by a scanning unit,
A variable clock generating unit that generates a pixel clock having a variable period with a different pulse width according to driving of the scanning unit by changing the number of delay units connected in series in a plurality of stages for each pixel of a display image;
A delay stage number selection unit that outputs a control signal for selecting the number of stages of the delay unit to the variable clock generation unit;
An image data buffer that receives an image signal and the pixel clock of the variable period and outputs an image signal synchronized with the pixel clock of the variable period to the light source;
An image display device comprising: The variable clock generator is
A calibration circuit for estimating a delay time of the delay unit;
A delay generation circuit that receives a system clock of a predetermined period and generates a delay in unit of one period of the system clock;
A precision delay generation circuit that inputs a delay clock in units of a period of the system clock and adds a delay in unit of one stage of the delay unit;
A logic circuit connecting the delay generation circuit and the fine delay generation circuit;
The image display apparatus according to claim 1, wherein a delay caused by the precision delay generation circuit is calibrated by the calibration circuit. The calibration circuit includes:
3. The delay time of the delay unit is calculated by generating a delay corresponding to one cycle of the system clock by a plurality of delay units connected in series, and comparing the delay with the system clock. Image display device.   The image display device according to claim 1, wherein the delay stage number selection unit includes a plurality of lookup tables configured by delay stage number information for changing the number of stages of the delay unit.   The variable clock generation unit includes a calibration circuit that estimates a delay time of the delay unit, and selects one from the plurality of lookup tables based on a signal from the calibration circuit. Item 5. The image display device according to Item 4.

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