JPH02185114A - Noise reduction circuit for semiconductor device - Google Patents

Abstract

PURPOSE:To suppress the quick change of the voltage of an internal circuit to reduce the noise by providing a means, which is substituted for voltage supply or current output to the internal circuit for a short time, in the immediate vicinity of the internal circuit, where the occurrence of noise is a problem, and on the same chip. CONSTITUTION:When an internal circuit 25 is not operated, transistors TRs P1 and P2 are turned off and a TR P3 is turned on, and therefore, a supply voltage VCC from a VCC power line 32 is applied to a TR N2, and the TR N2 is charged. When a signal to turn on a TR P4 is inputted, the charged electric charge stored in the TR N2 is applied to the source of the TR P4 by turning-on of the TR P2, and the TR P4 is turned on. Since the supply voltage of the TR P4 at this time is the terminal voltage of the TR N2, the supply voltage VCC of the VCC power line 32 is not reduced at all.

Description

[Detailed Description of the Invention] (Summary) Regarding a noise reduction circuit that reduces power supply noise in a semiconductor integrated circuit, the present invention aims to effectively reduce noise generated in an internal circuit without using unnecessary internal capacitance. A noise reduction capacitor formed on the same chip as an internal circuit of a semiconductor device connected to an external capacitive load, and a voltage from a first voltage source passed through or cut off to a first voltage input terminal of the internal circuit. a first switch that passes or blocks the terminal voltage of the capacitor to a second voltage input terminal of the internal circuit; and a second switch that passes or blocks the terminal voltage of the capacitor to a second voltage input terminal of the internal circuit; a third switch for setting the value, and the first switch is turned off and the second switch is turned on for a certain period from the start of the internal circuit's movement f\, and then the first switch is turned on and the second switch is turned on. It consists of a timing adjustment circuit that turns off the second switch.

[Industrial application field]

The present invention relates to a noise reduction circuit for a semiconductor device, and more particularly to a noise reduction circuit for reducing power supply noise of a semiconductor integrated circuit.

In recent years, as semiconductor integrated circuits (ICs) have become larger in capacity and more multifunctional, the number of I10 terminals on ICs has increased.

As a result, the number of package pin terminals has increased dramatically.
The size of packages has become enormous.

On the other hand, due to the miniaturization of the IC device chip itself, the size of the chip has hardly increased despite advances. As a result, the distance from the external terminals of the package to the internal pads of the chip has increased, and internal circuits have begun to malfunction due to noise generated within the chip.

Therefore, it is necessary to reduce the internal noise of this IC.

(Prior Art) There is a method shown in FIG. 6 as one of the conventional methods for reducing noise in a semiconductor device, particularly power supply noise. In the same figure,
11 is an IC device package whose power supply voltage V
It has a pin terminal 12 for VSS, a pin 13 for VSS, and various other pin terminals.

Further, 14 is a board wiring GND electrode, and the pin terminal 13
It is connected to the.

In this conventional example, the vcc bin terminal 12 is connected to the capacitor 15.
It is connected to the GND electrode 14 via. As a result, noise that enters the power supply line from the outside is absorbed by the capacitor 15, and power supply noise can be reduced.

FIG. 7 shows a configuration diagram of another example of reducing conventional power supply noise. In the figure, 16 is a package, and 17 is a chip built into the package 16. In the semiconductor device having such a configuration, a capacitor 18 is built inside the package 16 between the power supply line between the chip 17 and the external terminal portion of the package 16 .

According to this conventional example, since the capacitor 18 is connected closer to the power supply line of the chip 17 than in the conventional example in which the capacitor is provided outside the package 11 shown in FIG. 6, noise can be suppressed more effectively. Can be done.

Furthermore, as another conventional power supply noise reduction method, there has been a method of providing a capacitance pattern on the power supply line of the IC device (chip) pattern itself. According to this conventional method,
The noise reduction operation by the capacitor pattern acts on the entire internal circuit and stabilizes it.

(Problems to be Solved by the Invention) The conventional noise reduction methods shown in FIGS. 6 and 7 described above have an equivalent circuit as shown in FIG. In FIG. 6, the external capacitor 12) is a circuit, and in FIG. 7, a wiring load 21, 22 is connected between the built-in capacitor 18).

Therefore, in today's IC devices, where the size of the package has become huge due to the increase in capacity and multifunction of IC devices, the wiring loads 21 and 22 are quite large, so the noise generated in the internal circuit 20' is The capacitor C cannot sufficiently reduce the wiring load, and the wiring load 21 and 22 are not always calculated and added based on the design of the mounted chip, and are not appropriate values for the noise generated in the internal circuit 20. Normally, it was not possible to follow internal operations, which had a negative effect.

Furthermore, the conventional noise reduction method shown in FIG. 7 is expensive because it includes a dedicated noise reduction capacitor 18 connected to the chip 17 by wiring within the package 16.
Reliability was also not good.

In addition, the conventional method of providing a capacitance pattern on the power supply line of the chip pattern described above (the equivalent circuit is the same as that shown in Figure 8) is difficult to pattern-wise and is not very practical. Ta.

The present invention has been made in view of the above points, and an object of the present invention is to provide a noise reduction circuit for a semiconductor device that effectively reduces noise generated in an internal circuit without using unnecessary internal capacitance.

[Means to solve the problem]

FIG. 1 shows a circuit diagram of the principle of the present invention. In the figure, 25 is the internal circuit of the semiconductor device, 26 is a noise reduction capacitor,
27 is a timing adjustment circuit, SW + is a first switch, SW2 is a second switch, and SW3 is a third switch. Note that the capacitor 26 may be connected in parallel with the switch SW3.

The third switch SV%h is a switch for setting the terminal voltage of the capacitor 26 to a predetermined value during the non-operation period of the internal circuit 25, and the terminal voltage of the capacitor 26 is 1.

The timing adjustment circuit 27 turns off the first switch SWs and turns on the second switch SW2 for a certain period from the start of operation of the internal circuit 25, and then turns on the first switch SWs and turns off the second switch SW2. .

(Function) The present invention does not remove all noise, but reduces internal circuit noise, which is a particular problem in circuit operation, and also reduces the wiring load 21, 22 to almost zero. has no switch SW2゜8W3, only SWI, and the switch SW + is always on, so when the internal circuit 25 starts operating, the voltage of the voltage V1 line becomes the real III as shown in Fig. 2. As shown, there was a large decrease and noise was generated.The amount of decrease depends on the magnitude of the load driven by the internal circuit 25.

That is, since the output terminal of the internal circuit 25 is connected to the external terminal to the input/output terminal of another device, when the drive transistor of the internal circuit 25 operates, a sudden current flows through the drive transistor due to the large external capacitive load. flows to Such a rapid current change causes a voltage V+ (e.g. V,.

) cannot cope with the voltage supply, and the voltage V+ is significantly reduced as described above. Similarly, the voltage on the voltage v2 line shows a rapid rise as shown by the solid line ▪ in FIG.

In the present invention, when noise reduction is performed by reducing the drop in voltage V1 (in this case V+>V2), a switch S W s is provided, and this case will be described first. During the non-operation period of the internal circuit 25, the capacitor 26 is connected to the voltage V+ by the switch S W 3.
It is applied via W3, and its terminal voltage is vl.

In this state, when the internal circuit 25 starts operating at time t1, the timing adjustment circuit 27 turns off the switch SW+, turns on SW2, and turns off SWs. As a result, the terminal voltage of the capacitor 26 is applied to the internal circuit 25.

At time t2 after a certain period of time elapses before the capacitor 26 finishes discharging, the timing adjustment circuit 27 turns on the switch SW2, turns off SW2, and turns off SW3, so that the voltage V+ is applied to the internal circuit 25. It is applied via the switch S W +. This state is maintained while the internal circuit 25 is operating.

Therefore, the internal circuit 25 operates for a certain period a immediately after the start of its operation.
(i+~t2), the terminal voltage of the capacitor 26 is applied to the internal circuit 25 instead of the v1 line, so at time t
During a certain period from 1 to t2, there is no change as shown by the broken line ■ in FIG. Thereafter, at time t2, V+ is applied from the voltage line, but at that point, the external official load has already been charged to a certain extent by the terminal voltage from the capacitor 26, so the voltage on line 1 is as shown in Figure 2. As shown by the broken line ■, the level drop after time t2 is extremely small.

Further, the voltage V+ <Vz, - and the internal circuit 25
When the circuit is such that a voltage change from the V1 line is a problem, the capacitor 26 is connected in parallel to the switch SWs. In this case as well, the timing adjustment circuit 27 is the switch SW.
+, SW2 is controlled in the same manner as above, and at time 1. From the time when the internal circuit 25 starts operating at time t1
1, switch SW + is off for a certain period of time, SW2
is turned on and S W s is turned off, so during this period, the voltage of line ■1 does not change as shown by the broken line ■ in Figure 3, and the charge in the external capacitive load is transferred to internal circuit 2.
5 to form a capacitor 26.

Thereafter, at time tn, the switch SWI is turned on and SW2 is turned off, and when the ■1 line is connected to the internal circuit 25 via the switch SW +, the external capacitive load is transferred through the internal circuit 25. Although it is discharged to the V+ line, since the discharge of the capacitive load has progressed to a certain extent at this point, the rise in the potential of the V1 line due to the discharge current is smaller than in the conventional case, as shown by the broken line ■ in FIG.

Note that after the operation of the internal circuit 25 is completed, the switch SW +
and SW2 are both turned off, and SW3 is turned on.

〔Example〕

FIG. 4 shows a circuit diagram of a first embodiment of the present invention.

In the figure, the same components as in FIG. 1 are denoted by the same reference numerals, and their explanations will be omitted. In FIG. 4, the internal circuit 25 is P
It consists of a CMOS inverter and the like consisting of a channel MO8 type field effect transistor (hereinafter simply referred to as a transistor) P4 and an N-channel transistor N1, and its output terminal is connected to a capacitive load 31 external to the IC device package via a pad 30. It is connected to the.

Further, P+, P2 and P3 are respectively the first. P-channel transistors for switching correspond to the second and third switches SW+, SW2 and SW3, and the sources of the transistors P+ and P3 are connected to the vc- source line 3.
2, and the gates of transistors P+, P2 and P3 are respectively connected to a timing adjustment circuit 33. Also, the source of the transistor P2 is the transistor P+
and the source of P4, respectively, and the drain of P2 is connected to the drain of P3 and the N-channel transistor N2.
are connected to the respective gates.

The drain and source of the transistor N2 are short-circuited, so that the transistor N2 operates as a capacitive element corresponding to the capacitor 26. That is, in this embodiment, since the capacitor 26 is connected very close to the internal circuit 25, it does not need to have a large capacitance, and there is no need for a dedicated capacitor 18 as shown in FIG. It can be used as a substitute, and it is inexpensive because it does not require a process to incorporate a capacitor.

Next, to explain the operation of this embodiment, the internal circuit 25
When is not operating, transistors P+ and P2 are turned off and transistor P3 is turned on, respectively, by the output signal of the timing adjustment circuit 33, so that transistor N2
Electricity from vCoWi source line 32! Voltage vCC is applied and transistor N2 is charged.

Next, when a signal is input to turn on the transistor P4, this signal is branched and input to the timing adjustment port 3.
3 outputs a signal that turns on the transistor P2, and also outputs a signal that turns off the transistors P1 and P3, respectively. When the transistor P2 is turned on, the charge stored in the transistor Nz is applied to the source of the transistor P4 through the drain and source of the transistor P2, and the transistor P4 is turned on.

When transistor P4 is turned on, a drain current flows through P4 and charges the external capacitive load 31, but since the power supply voltage of P4 at this time is the terminal voltage of transistor N2, vc
The power supply voltage vCc of the c power line 32 does not decrease at all.

After a certain period of time has elapsed, the timing adjustment circuit 33 supplies a signal to turn on transistor P+ to the gate of P+, and also supplies a signal to turn off transistors P2 and P3 to the gates of P2 and P3, respectively. As a result, the power supply voltage vCc from the cC%i source line 32 is supplied to the source of the transistor P4 through the transistor P1.

At this time, the 'I4 current flowing through the transistor P4 is supplied to the external load capacitor 31 via the pad 30, but since the external load capacitor '31 is already charged to some extent at this point, the current change is not so large. Already done, therefore v
The drop in CC power supply is significantly alleviated compared to the conventional method, and noise can be reduced.

The above state continues during the on period of transistor P4.

After that, when the transistor P4 is turned off, the output signal of the timing adjustment circuit 33 causes the transistors P1 and P4 to turn off.
Switching control is performed so that P2 is turned off and P3 is turned on.

This example is V. . This is an example in which noise caused by a significant drop immediately after the internal circuit 25 of the power supply starts operating becomes a problem, but v, S1! Noise caused by a significant increase immediately after the internal circuit 25 of the source starts operating (indicated by a solid line ■ in FIG. 3) may become a problem. The second embodiment shown in FIG. 5 below is an embodiment in this case, and in FIG. 5, the same components as those in FIG.

In FIG. 5, Ns, N4 and Ns are the first, second and third switches SW+, SWz and SW3.
Each gate is connected to the output terminal of the timing adjustment circuit 34, and each source of the transistors N3 and Ns is connected to the source power supply vSS.

In this configuration, when the internal circuit 25 is off, transistors N3 and N4 are off, and transistor N
Since s is turned on, the charge in the transistor N2 is completely discharged through the transistor N5.

When a signal that turns on the transistor N1 is input in this state, the timing adjustment circuit 34 outputs a signal that turns on the transistor N4, while controlling each of the transistors N3 and Ns to turn off.

As a result, the charging charge of the external capacitive load 31 is reduced to the bad 30.
．． It is discharged to the train of the transistor N1 to turn it on, and is further discharged to the gate of the transistor N2 via the source of N+, the drain and source of the transistor N4, and charges the gate capacitance of N2. Because of this charging to N2, no rise in the 738M source occurs.

After that, before the above discharge is completed, the timing adjustment circuit 3
4 controls the transistor N3 to be on and N4 and Ns to be off, respectively. As a result, the charge in the external capacitive load 31 is discharged to the Vs5 power supply line via the transistor N3, but since the charge NNWIm at this point has decreased considerably, the VssN source power line current is small.
Therefore, as indicated by the broken line ■ in FIG. 3, the rise in the ■ss power supply is significantly smaller than in the past, and the noise accompanying the rise is also reduced.

Note that the present invention is not limited to the above-mentioned embodiment, and for example, the transistor Ps corresponding to the switch SW3
, Ns, a transistor whose driving capacity is sufficiently smaller than that of the transistor P+, N3 corresponding to the switch SWs, and the transistor P3
, Ns may be operated with always on.

In this case, when transistors P+, Ns, or P2゜N4 are controlled to be on, almost no current flows even in the on state because the driving ability of transistor P3゜Ns is small.
Since most of the current flows through the transistors P+ and NZ (or P2 and Na) which have a large driving capacity, it is possible to substantially perform the operation of the above embodiment. Therefore, in this case, timing control of the transistors Ps and Ns is unnecessary, and the timing adjustment circuits 27 and 33 can have a simpler configuration.

In addition, the present invention may use the first and second embodiments together,
Furthermore, it can be applied to noise caused by sudden changes in voltage other than the I source voltage.

〔Effect of the invention〕

As described above, according to the present invention, a means for replacing the voltage supply or current output to the internal circuits is provided in the immediate vicinity of the internal circuits where noise generation is a problem and on the same chip. It is possible to suppress sudden changes in voltage, thereby reducing noise, and the capacitance of the noise reduction capacitor is small. It can be constructed at a lower cost than the conventional method, and the process and pattern design are almost the same as before. Appropriate values can be set by circuit calculation centrally in the place where noise is generated, eliminating unnecessary parts. This has the advantage of eliminating the need for internal circuitry and reducing noise in the entire internal circuit.

26 is a noise reduction capacitor, 27 is a timing adjustment circuit; 31 is an external capacitive load, SW + is the first switch, SW2 is the second switch, SWz is the third switch shows.

Claims (1)

[Claims] An internal circuit (2) of a semiconductor device connected to an external capacitive load.
a noise reduction capacitor (26) formed on the same chip as 5); and a first switch that passes or cuts off the voltage from the first voltage source to the first voltage input terminal of the internal circuit (25). (S
W_1); a second switch (SW_2) that passes or cuts off the terminal voltage of the capacitor (26) to the second voltage input terminal of the internal circuit (25); Internal circuit (2
a third switch (SW_3) for setting a predetermined value during the non-operation period of 5);
The second switch (SW_1) is turned off, and the second switch (SW_1) is turned off.
SW_2) is turned on, and then the first switch (SW_2) is turned on.
1) and a timing adjustment circuit (27) that turns on the second switch (SW_2) and turns off the second switch (SW_2).