JPH02185114A - Noise reduction circuit for semiconductor device - Google Patents

Noise reduction circuit for semiconductor device

Info

Publication number
JPH02185114A
JPH02185114A JP1005377A JP537789A JPH02185114A JP H02185114 A JPH02185114 A JP H02185114A JP 1005377 A JP1005377 A JP 1005377A JP 537789 A JP537789 A JP 537789A JP H02185114 A JPH02185114 A JP H02185114A
Authority
JP
Japan
Prior art keywords
internal circuit
turned
voltage
vcc
supply voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1005377A
Other languages
Japanese (ja)
Inventor
Nobuo Ikuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1005377A priority Critical patent/JPH02185114A/en
Publication of JPH02185114A publication Critical patent/JPH02185114A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To suppress the quick change of the voltage of an internal circuit to reduce the noise by providing a means, which is substituted for voltage supply or current output to the internal circuit for a short time, in the immediate vicinity of the internal circuit, where the occurrence of noise is a problem, and on the same chip.
CONSTITUTION: When an internal circuit 25 is not operated, transistors TRs P1 and P2 are turned off and a TR P3 is turned on, and therefore, a supply voltage VCC from a VCC power line 32 is applied to a TR N2, and the TR N2 is charged. When a signal to turn on a TR P4 is inputted, the charged electric charge stored in the TR N2 is applied to the source of the TR P4 by turning-on of the TR P2, and the TR P4 is turned on. Since the supply voltage of the TR P4 at this time is the terminal voltage of the TR N2, the supply voltage VCC of the VCC power line 32 is not reduced at all.
COPYRIGHT: (C)1990,JPO&Japio
JP1005377A 1989-01-12 1989-01-12 Noise reduction circuit for semiconductor device Pending JPH02185114A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1005377A JPH02185114A (en) 1989-01-12 1989-01-12 Noise reduction circuit for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1005377A JPH02185114A (en) 1989-01-12 1989-01-12 Noise reduction circuit for semiconductor device

Publications (1)

Publication Number Publication Date
JPH02185114A true JPH02185114A (en) 1990-07-19

Family

ID=11609484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1005377A Pending JPH02185114A (en) 1989-01-12 1989-01-12 Noise reduction circuit for semiconductor device

Country Status (1)

Country Link
JP (1) JPH02185114A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07106944A (en) * 1993-09-03 1995-04-21 Goldstar Electron Co Ltd Output buffer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07106944A (en) * 1993-09-03 1995-04-21 Goldstar Electron Co Ltd Output buffer

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