JPH02183699A - Redundancy circuit system for time division channel switch - Google Patents

Abstract

PURPOSE:To identify a parity error by inputting a test pattern inserted to a specific channel of a channel to a channel switch and extracting the output and comparing it with the test pattern. CONSTITUTION:Test pattern information generated by a pattern generating circuit 101 is inserted to a specific channel of the channel by an insert circuit 100, three time division switch circuits 102-104 switch the output of the insert circuit 100 in the time division system and an output gate circuit 108 extracts the specific channel inserted with the test pattern. Then a pattern check circuit 109 compares the pattern information of the extracted specific channel with the inserted test pattern and a 2/3 majority decision circuit 201 applies majority decision by using an output of the pattern check circuit 109. Thus, a parity check error is identified.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to time-division channel switching of digital communication channels in digital exchanges, and relates to percent trap channel switch identification monitoring and redundancy.

(Prior Art) Space-division switches and time-division switches are conventionally known as switches for switching communication paths in digital exchanges. Although the configuration of the switch varies depending on the system, most systems employ a dual configuration to achieve switch redundancy.

Typical redundant switch systems include a hot standby system that allows immediate switching to a normal system in the event of a failure, and a cold standby system that starts up a backup system and switches over after a failure occurs.

(Problems to be Solved by the Invention) The normality monitoring system for the conventional digital communication path switch described above usually relies only on a horizontal parity check of the communication path switch memory. Therefore, when a fault is detected, it is impossible to identify whether the fault is in the channel memory or in the parity check generated and added by the peripheral circuitry of the memory.

In addition, if a duplex system is used as a redundant configuration,
When a failure occurs, the faulty system is disconnected and the normal system is installed. This switching operation has the disadvantage that, depending on the case, it may cause a momentary interruption of the communication path data or an abnormality in the channel data of the communication path.

If the information on the communication path is similar to a voice telephone call, even if it is only audible as click noise, if it is data communication information such as a computer, it will be identified as a complete data abnormality. This method has the disadvantage that retransmission processing must be performed between terminals such as computers.

An object of the present invention is to input a test pattern inserted into a specific channel of a communication path into a communication path switch, extract the output, and compare it with the test pattern to eliminate the above-mentioned drawbacks and easily identify parity abnormalities. It is an object of the present invention to provide a redundant circuit system for a time-division communication path switch configured to enable this.

(Means for Solving the Problems) The redundant circuit system of the time-division channel switch according to the present invention includes an insert circuit, a pattern generation circuit, a three-circuit time-division switch circuit, an output gate circuit, a pattern check circuit, This configuration includes a 2/3 majority determination circuit.

The insert circuit is for inserting a test pattern into a specific channel of the communication path.

The pattern generation circuit is for generating test patterns.

The three time division switch circuits are for switching the outputs of the insert circuits in a time division manner.

The output gate circuit is for extracting a specific channel into which a test pattern has been inserted from the outputs of the three time division switch circuits.

The pattern check circuit is for comparing the pattern information of a specific channel extracted from the output gate circuit with the test pattern inserted by the pattern generation circuit.

The 2A majority decision circuit is for making majority decision based on the output of the pattern check circuit.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a redundant circuit system for a time division path switch according to the present invention. Figure 2 shows
FIG. 2 is an explanatory diagram showing a highway format input to a communication path switch.

In FIG. 1, 600 is a time division communication circuit, 100 is an insert circuit, 101 is a pattern generation circuit, and 102 to 1
04 is a time division switch circuit, 105 to 107 are time division switch control memories, 108 is an output gate circuit, 109 is a pattern check circuit, 200 is a control circuit, 201 is a 2/3 majority decision circuit, and 202 is a gate control circuit. , 203 is a processor path interface circuit, 300 is a switch circuit input highway, 301 is a switch circuit output highway, 400 is a processor bus, 50
0 is a test channel, and 600 is a time division communication circuit.

The redundant circuit of the time-division channel switch of this embodiment will be explained with reference to FIG.

The time division communication path switch is composed of a time division communication circuit 600 and a control circuit 200 for controlling the time division communication circuit 600.

The time division communication circuit 600 includes an insert circuit 100 for inserting the test pattern into the switch circuit input highway 300, a pattern generation circuit 101 for generating the test pattern, and a time division communication circuit for switching the time division communication channel. Split switch circuits 102 to 104;
Time division switch control memories 105 to 107 for storing communication path channel switching information corresponding to time division switch circuits 102 to 104; and time division switch circuits 102;
A pattern check circuit 109 which is a downstream circuit of the output highway of ~104, an output gate circuit 108 for controlling connection to the pattern check circuit 109, and a test pattern channel are extracted from the output highway of the output gate circuit 108, A pattern check circuit 109 for comparison with the test pattern generated by the generation circuit 101
It consists of

Next, the control circuit 200 transmits and receives control information to and from the higher-level control device that controls the time-division switch according to the present invention and the gross processor bus interface circuit 203 via the processor 400, and performs gate control that controls the output gate circuit 108. It is comprised of a circuit 202 and a 2/3 majority decision circuit for monitoring the normality of the time division switch circuits 102 to 104 from information obtained by the pattern check circuit 109.

Next, the general operation will be explained with reference to FIGS. 1 and 2.

Switch circuit input highway 300 is insert circuit 1
The test pattern information input to the switch circuit input highway 30 and generated by the pattern generation circuit 101 is input to the switch circuit input highway 30.
As shown in FIG. 2, the switch circuit output highway 301 from the insert circuit 100 is inserted into the test channel 500 every frame as a specific time slot on the insert circuit 100 as shown in FIG. Ru.

Furthermore, the switch circuit output highway 301 from the time division switch circuits 102 to 104 is connected to the output gate circuit 108.
is input. The output gate circuit 108 is controlled by the gate control circuit 202, and when normal, the time division switch circuit 1
Switch circuit output highway 301 from 02-104
are all connected to the pattern check circuit 109. The pattern check circuit 109 extracts the information of the test channel 500 in the high format shown in FIG.

If the two match, it is determined that the time division call circuit 600 is operating normally.

Country comparisons are made for each channel information of the time division switch circuits 102 to 104, and the matching of the channel information of the 3 highways is monitored. Only when the channel information of 2 highways or more matches, the information is sent to the switch circuit output highway 301. Output.

The match comparison information of the test pattern information is sent to the 273 majority decision circuit 201, and the test channel 5 of 2 or more high
If 00 does not match, it is determined that there is a failure in the time division communication circuit 600, and the result of identifying the normality of the failed highway is notified from the processor bus 400 to the upper control device through the processor server interface circuit 203. In addition, time division switch circuits 102 to 10 corresponding to the above-mentioned faulty highway
On the output highway No. 4, the output gate circuit 108 and the pattern check circuit 1
The connection with 09 is disconnected.

(Effects of the Invention) As explained above, the present invention inputs the test pattern inserted into a specific channel of the communication path into the communication path switch, extracts the output, and compares it with the test pattern.
Constantly monitors the normality of the time division communication path, and further inputs communication path information multiple times into three or more communication path switches,
Since redundant output can be obtained by making a majority decision on the output information of the plurality of communication path switches, normally a duplex system is adopted as a redundant configuration of the communication path switches, and systems are switched in the event of a failure. It has the effect of being able to

Therefore, continuity of output is guaranteed, redundant output can be obtained without switching systems, and control when switching systems can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a redundant circuit system for a time-division channel switch according to the present invention. FIG. 2 is a highway format diagram input to the communication path switch. 100... Insert circuit 101... Pattern generation circuit 102-104... Time division switch circuit 105-10
7... Time division switch control memory 108... Output gate circuit 109... Pattern check circuit 200... Control circuit 201... 2/3 majority decision circuit 202... Gate control circuit 203... Processor bus interface circuit 300
... Switch circuit input cable 301 ... Switch circuit output highway 400 ... Processor bus 500 ... Test channel 600 ... Time division communication circuit Patent applicant NEC Corporation Agent Patent attorney Ino B. Hisashi 2

Claims (1)

[Claims] An insert circuit for inserting a test pattern into a specific channel of a communication path, a pattern generation circuit for generating the test pattern, and a three-circuit time division switch circuit for switching the output of the insert circuit in a time division manner. and an output gate circuit for extracting the specific channel into which the test pattern is inserted from the outputs of the three time division switch circuits, and pattern information of the specific channel extracted from the output gate circuit and the pattern. A pattern check circuit for comparing the test pattern inserted by the generation circuit, and a 2/3 majority decision circuit for making a majority decision based on the output of the pattern check circuit. A redundant circuit method for time-division communication path switches.