JPH02183566A - Triac - Google Patents

Abstract

PURPOSE:To stabilize resistance between terminals by forming a channel of low resistance and a narrow and long channel of high resistance which are sandwiched by N<+> type diffusion layers, between a P-type diffusion layer 4 and a P-type diffusion layer under a gate electrode. CONSTITUTION:Between an N<+> type diffusion layer 2 and an N<+> type diffusion layer 3 for a gate use, a channel 8 and a channel 5-1 are arranged. The length (a) of the channel 8 is large; the width (b) of the channel 8 is small; the length of the channel 5-1 is small; the width (c) of the channel 5-1 is large. An electrode 12 with which a terminal T1 is connected is formed over the N<+> type diffusion layer 2 and a P-type diffusion layer 1; an electrode 13 with which a terminal G is connected is formed over a P-type diffusion layer 4, which is an extension part of the N<+> type diffusion layer 3 and a P<+> type diffusion layer 1, and most of which is surrounded by the N<+> type diffusion layer 3. As a result, a combined resistance between the terminal T1 and the terminal G becomes equal to the combined resistance of a P-type diffusion resistance of the channel 5-1 and a P-type diffusion resistance of the channel 8. Thereby, the precise and stable resistance between the terminal T1 and the terminal G can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement of a planar triac using semiconductors.

(Prior Art) FIG. 2 is a plan view schematically showing an example of a conventional planar triac, and FIG. 8 is a schematic sectional view for explaining its operation. This triac is a particle type, and the current is input from the gate terminal G to the terminal T1.
and the terminal T2 in the direction of the dotted arrow A or B. A KPM diffusion layer 10 is provided on the lower and side surfaces of the N-type semiconductor substrate 7, an N+ type scattering layer 14 is provided on a part of the lower surface, the entire surface is covered with an electrode 11, and a terminal T2 is provided.

On the other surface of the N-type semiconductor substrate 7, a P-type diffusion layer 1 is formed inside, and an N+-type diffusion layer 8 for a gate of an appropriate shape is further formed inside the N-type semiconductor substrate 7. Layer 2 is formed. Part of Pfi diffusion layer 1 and N+ type scattering layer 2
An electrode 12 is provided across it, and a terminal T1 is provided.

A t-pole 18 is provided over a part of the P-type scattered layer 1 and the N+ type scattered layer 3, and a terminal G is taken out. These electrodes are not shown in Figure @2. Note that the shapes of the N+ type scattering layers 2 and 8 are also simplified in FIG. 3.

P-type diffusion layer 1°N-type semiconductor substrate 7 in the path of dotted arrow A in FIG. P-type semiconductor layer 10 and N+ type scattering layer 14
A first thyristor is formed by a PNPN configuration consisting of an N+ type diffused layer 2P diffused layer 1. A second thyristor is formed of an NPNP configuration consisting of an N-type semiconductor substrate 7 and a P-type semiconductor layer 10.

The resistance between the terminal T1 and the gate terminal G is the resistance between the electrode 12
This is the P-type diffused resistance between the P-diffused layer l on the lower surface of the electrode 18 and the P-type diffused layer 4 on the lower surface of the electrode 12.
+ type scattered layer 2 P type diffused resistance of channel 5 between N+ type scattered layer 8 on the lower surface of electrode 18 and P type between N+ type scattered layer 8P diffused layer 1 on the lower surface of electrode 18 This is a combined resistance of 6.6 diffused resistances.

(Problem to be solved by the invention) In the conventional diffusion pattern shape as shown in Fig. 2, the terminal τ
The resistance between L and terminal G is the P-type diffused resistor 5 and P
It is a combined resistance with the type diffused resistance 6. At this time, N++ diffused layer 2 on the lower surface of the electrode 12 and N++ on the lower surface of the electrode 13
Since the diffused layer 8 is formed at the same time by photolithography, the width, length, etc. of the P-type diffused resistor formed by the channel 5 are always constant and stable. However, since the P type diffused resistor 6 is formed by separate photolithography of the P diffused layer l and the N+g+ diffused layer 3, the width, length, etc. may change due to mask alignment errors at that time. The resistance value becomes unstable.

The resistance between terminal TI and terminal G has a deep relationship with other characteristics such as sensitivity and holding current, and it is desirable that the resistance be stable from the viewpoint of element quality and yield.

The present invention aims to stabilize this resistance.

(Means for Solving the Problems) In the present invention, when forming the N medium temperature diffusion layers 2 and 8,
A channel with a low resistance value and a narrow channel with a long length and a high resistance value are sandwiched between the P type diffusion layer 4 and the P diffusion layer 1 below the gate electrode by the N+ type diffusion layer 28. formed.

(Function) The width, length, etc. of the channel are always constant because the N+ type scattering layer 28 is formed at the same time. If the width is narrow and the length is long, the resistance value becomes large.If the resistance value is made sufficiently larger than the resistance value of the pm diffused resistor 5, the resistance value between the terminal T1 and the terminal 0 approaches the resistance value of the P type diffused resistor due to the channel 5. Stabilize.

(Embodiment) Fig. 1 is a plan view showing an example of a surface pattern of an embodiment of the present invention.
is omitted. The same parts as in FIG. 2 are designated by the same reference numerals.

The difference between the present invention and the conventional example is that the N+
This is the shape between the type scattering layer 2 and the N++ diffusion layer 3 for the gate.

In Figure 1, N is the cathode of one thyristor.
Between the + type scattering layer 2 gate N+ type diffusion layer 8, there are a long channel 8 with a length 1 and a narrow width, and a channel 5-1 with a short length and a wide width C. It is provided.

The electrode 12 to which the terminal TI is connected is an N+ type scattering layer 2P.
The electrode 18 formed over the diffused diffusion layer l and to which the terminal G is connected is an extended part of the N+m+ diffused layer 8 and the P+ warm diffusion layer 1, and is mostly surrounded by the N+ type diffused layer 8. It is formed over a P-type number of 4. Therefore, the combined resistance between terminal T1 and terminal G is a combination of the P-type diffused resistance of channel 5 and the P-type diffused resistance of channel 8. If the P type diffused resistance of channel 8 is made sufficiently larger than the pg diffused resistance of channel 5, terminal TI
The resistance between and terminal G approaches the P-type diffused resistance of channel 5-1.

(Effects of the Invention) According to the present invention, the resistance between the terminal TI and the terminal G is N
By forming the +-type scattering layer 28, a highly accurate and stable product can be obtained, so that quality and yield can be improved.

[Brief explanation of the drawing]

FIG. 1 is a plan view of an embodiment of the present invention, FIG. 2 is a plan view of a conventional example, and FIG. 8 is a sectional view for explaining the operation. l...P-ya diffusion layer, 2...N+ type number turbidity, 8...
N+ deaf diffusion layer, 4... P type diffusion layer, 5... Channel, 6... P type diffused resistor, 7... N type semiconductor substrate, 8... Channel 1, 0... P-type diffusion layer, 1... back electrode,

Claims (1)

[Claims] 1. Consists of two systems of thyristors, NPNP and PNPN, formed perpendicular to the substrate, and a gate formed on the surface of the substrate, with the gate-side thyristor formed on the semiconductor layer of the first conductivity type. A triac characterized in that a channel with a small resistance value and a channel with a large resistance value are provided between a semiconductor layer of a second conductivity type and a semiconductor layer of a second conductivity type on the surface of a thyristor of one system.