JPH02183496A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent element destruction caused by excessive program voltage by providing a program voltage lowering circuit to lower the program voltage to voltage lower than a prescribed potential when the program voltage is higher than the prescribed potential. CONSTITUTION:When program voltage VPP of an EPROM becomes 21V because of erroneous setting though the voltage VPP is 12.5V, the output voltage of a program voltage detection circuit 3 becomes an H level. Since an n-channel transistor Tr 25 operates in response to the output signal of an inverter 21, in this case, the Tr 25 is turned on. As the result, even when the voltage VPP is 21V, since the potential is grounded by the Tr 25, the potential of a voltage VPP wiring is made into a ground potential. As the result, the ground potential is impressed to a VCC/VPP voltage switching circuit 15 and a memory cell selecting peripheral circuit 5, and the excessive voltage is never impressed to the respective circuits of the EPROM. Consequently, it can be prevented that the EPROM is join-destroyed caused by the impressing of the excessive voltage to the EPROM.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a non-volatile semiconductor memory device (hereinafter abbreviated as EFROM) using a floating gate type memory cell, and particularly relates to a junction breakdown that may occur during programming. The present invention relates to a nonvolatile semiconductor memory device that can prevent the above.

[Conventional technology]

FIG. 4A is a block diagram showing the overall configuration of a conventional ultraviolet irradiation type EFROM. Referring to FIG. 4A, the ultraviolet irradiation type EFROM is controlled by a control section 1 for controlling the entire EPROM, a signal from the control section 1, and a program voltage VP''P% power supply voltage VCC applied from the outside. A VCC/VPP power supply switching circuit 15 for supplying internal power to the memory cell selection peripheral circuit 5 and the peripheral circuit control signal line output from the control unit 1, VCC/V
selected by the memory cell selection peripheral circuit 5 connected to the PP power supply switching circuit 15 and the externally applied program voltage VFP, and the memory cell selection peripheral circuit 5;
It includes a memory array 12 in which memory cells for storing information charges are arranged in rows and columns. The control unit 1 has an EFROM
Control signal input terminals CE, OE, and PGM are respectively provided to which control signals for controlling are input. The memory cell selection peripheral circuit 5 is connected to the memory array 12.
A row decoder 7 and a column decoder 8 are used to select one memory cell 9 included in the memory cell 9, and an address signal is output to the row decoder 7 and column decoder 8 in response to external address signals A0 to An. address buffer 6, and Do-wDn, which is an external data input/output terminal.
It is connected to the output buffer 11 for temporarily storing input/output data, the column decoder 8 and the output buffer 11, and determines the presence or absence of information charges in the memory cells in the memory array 12 when sequential data is output. and a sense amplifier 10 for.

FIG. 4B is a schematic diagram showing an outline of an EPROM programmer for writing data into the EFROM shown in FIG. 4A. Referring to FIG. 4B, the EPROM programmer has a program power supply terminal for supplying a program power supply VPP, a power supply terminal VCC for supplying power, and an EPROM programmer.
CE for outputting control signals to control the ROM
, O.E.

Each control signal output terminal of the PGM and an address signal A0 for selecting a memory cell in the memory array 12
An address signal output terminal for outputting ~An and a data input/output terminal for data input/output. -Dn. When the EFROM is programmed, the EP
The ROM and EPROM programmers are respectively connected to the power supply and signal terminals with the same symbols mentioned above through IC sockets.

FIG. 5 is a schematic cross-sectional view showing the structure of one memory cell 9 constituting the memory array 12. As shown in FIG.

Referring to FIG. 5, one memory cell of the EFROM is
A source 52 and a drain 53 are formed at intervals on the main surface of the semiconductor substrate 51, and information charges formed on a region sandwiched between the source 52 and the drain 53 via an insulating film 56 are stored. and an insulating film 56 on the floating gate 54.
and a control gate 55 for selecting a memory cell.

FIG. 6 is a graph showing the relationship between the control gate voltage VcG and the drain current tos flowing to the drain when information charges are written and erased in one memory cell 9. When information charges are written into the floating gate 54 of the memory cell 9, a drain current XOS shown by a in the figure flows, and when the information charges are erased from the floating gate 54, a drain current tos shown in the figure already flows. flows. This state is read by applying read gate voltage VR to control gate 55. Thereby, the presence or absence of information charges in the floating gate 54 is determined.

Next, the operation of the EFROM will be explained. When programming, use the EP programmer shown in Figure 4B to
The control unit 1 of the EFROM receives a signal from the OM programmer and senses that the EFROM is in the program mode. The control section 1 guides the program voltage supplied from the EPROM programmer to the memory cell selection peripheral circuit 5, and sets it in a program enable state. address buffer 6
transmits an address signal to the row decoder 7 and column decoder 8 which are to select a predetermined memory cell 9 based on the signal from the EP programmer. Row decoder 7 and column decoder 8 select word lines and bit lines connected to control gate 55 and drain 53 of each memory cell 9. At the same time, the memory cells 9 are programmed with predetermined information obtained from the crowd buffer 11 by accumulating information charges in the selected memory cells 9.

Next, the operation of the EFROM memory cell 9 will be briefly explained. Referring to FIGS. 5 and 6, when writing is performed on floating gate 54, drain 53 and control gate 55 are applied with a high voltage (program voltage VP
F) is applied, and the source 52 is brought to ground potential.

Then, hot electrons are generated in the channel region sandwiched between the source 52 and the drain 53, and these hot electrons are injected into the floating gate 54. When data in the EFROM is erased, the EFROM is irradiated with ultraviolet light. As a result, the electrons within the floating gate are excited and emitted. By injecting electrons into the floating gate 54, writing is performed on the floating gate, raising the threshold value, and by releasing the electrons in the floating gate, the floating gate is erased and the threshold value returns to the original value. return.

After the above program is completed, if the program continues, the control unit 1
transmits a signal for controlling the EPROM to read mode to the memory cell selection peripheral circuit 5. As in programming, a predetermined memory cell 9 is selected by an address signal. The sense amplifier IO senses information in the memory cell 9 and transmits it to the input/output buffer 11. The human output buffer 11 outputs the read information voltage to the outside after waveform shaping and amplification.

The program voltage of currently available EFROM is 1
There are 2.5V and 21V types. Generally, the read voltage is 5V for both the 12.5V system and the 2IV system.

Also, as an EFROM programmer, 12.5V system, 2
Most devices are compatible with both 1V and 1V systems.

The conventional EFROM is configured as described above. In addition, EFRO
The M programming voltage is becoming lower. but,
Since EFROMs requiring different programming voltages coexist, there is a problem in that during programming, an overvoltage is applied to the EFROM due to incorrect settings of the EFROM programmer, resulting in destruction.

In order to solve the above-mentioned problems, in the conventional improved EFROM, a program voltage detection circuit is provided in the control section of the EFROM. In other words, the program voltage detection circuit logically detects a program voltage higher than the specified value as EF.
If applied to ROM, program mode was not set.

Vcc was supplied as the power supply voltage for the internal peripheral circuitry using Vrr/Vcc as the power supply, thereby preventing destruction of the internal elements due to exceeding their breakdown voltage.

An example of such an improved EFROM is disclosed in, for example, Japanese Patent Laid-Open No. 81550/1983.

[Problem to be solved by the invention]

FIG. 7 is a schematic diagram of a Vl:C/VPP power supply switching circuit (corresponding to 15 in FIG. 1) of an improved EEPROM described in Japanese Patent Application Laid-Open No. 63-81550. Referring to FIG. 7, a conventional improved EPROM Vcc/Vpp power supply switching circuit 15 is provided between a program voltage VPP terminal and a node N, and is an N channel that operates in response to the output of a NOR circuit. A transistor 37 , an N-channel transistor 39 connected between the node N and the power supply voltage Vcc terminal and operated in response to a peripheral circuit control signal output from the control unit 1 , and a peripheral circuit control signal and an N-channel transistor 37 . The internal power supply used in the control unit 1 and the memory cell selection peripheral circuit 5 is connected from the node N to vcC/VP? It is output to internally used circuits (peripheral circuits for memory cell selection, control circuits, etc.).

In the improved EFROM, the program mode is not set if a program voltage higher than a logically specified value is applied by the program voltage detection circuit. However, even in the conventional improved EEFROM! As shown in Figure 07, the program voltage VP applied externally
P is directly applied to the VCC/Vrr power supply switching circuit 15. In such a case, the program voltage VPP
is higher than a predetermined programmable voltage, it is not possible to prevent junction breakdown of the device due to overvoltage. That is, an overvoltage is applied to the vcc/vPP power supply switching circuit 15, and the Vc(/VPP power supply switching circuit) may be destroyed.

This invention was made to solve the above-mentioned problems, and even if an overvoltage is applied from an EPROM programmer, it is possible to prevent element destruction due to overvoltage.
The purpose is to provide FROM.

[Means for Solving the Problems] An EFROM according to the present invention includes an array of memory cells that have floating gates and store information charges, a memory cell selection circuit section that selects memory cells, and memory cells and memory cells. a control section for controlling the selection circuit section; and an internal power generation means for applying an operating voltage to the control section, the memory cell, and the memory cell selection circuit section;
This is a non-volatile semiconductor memory device that performs programming by receiving a write program voltage. During writing, the write program voltage is applied to a memory cell selection circuit section, a control section, and an internal power supply generation circuit, and the program voltage is maintained at a predetermined level. a program voltage determination circuit that determines whether the program voltage is at a second potential higher than the first potential; and when the program voltage determination circuit determines that the program voltage is at the second potential, and a program voltage drop path for lowering the voltage to a potential lower than that of the voltage.

[Function] The program voltage drop circuit according to the present invention lowers the EPROM voltage when the program voltage VFF is higher than a predetermined potential.
The program voltage VrP applied from the programmer is lowered to a potential lower than a predetermined first potential. Therefore, in each circuit portion to which the program voltage Vrr is applied,
A potential higher than the predetermined first potential is never applied.

[Embodiments of the Invention] FIG. 1 is a block diagram showing the overall configuration of an ultraviolet irradiation type EFROM according to the present invention.

Referring to FIG. 1, the EFROM according to the present invention is
FROMControl unit 1 for controlling all ROMs and EPROM
VCC/VPP power supply switching circuit 15 for supplying operating power to the control unit 1 and the memory cell selection peripheral circuit 5 in response to the program voltage Vtt applied from the programmer and the peripheral circuit control signal output from the control unit 1; and E
Program voltage VP applied from PROM programmer
? and a peripheral circuit for memory cell selection 5 which is connected to the peripheral circuit control signal outputted from the control unit 1 and performs memory cell selection etc.; and a memory array 12 including an array of memory cells.

The control section 1 is connected to the program voltage VPP applied from the EPROM programmer, and includes a program voltage detection circuit 3 for detecting the voltage of the program voltage VPP, and a program/program/program for controlling the program and subsequent execution.
A read control section 2, a program circuit 4 connected to the program voltage detection circuit 3 and the program/read control section 2, and outputting a peripheral circuit control signal for controlling the memory and memory cell selection peripheral circuit. include.

The configurations of the memory cell selection peripheral circuit 5 and the memory array 12 are similar to those shown in FIG. 4A, so the same parts are given the same reference numerals and the explanation thereof will be omitted.

Furthermore, the relationship between EPROM and EPROM programmer is
Since the contents are the same as those explained in FIGS. 4A and 4B, the same parts are given the same reference numerals and the explanation thereof will be omitted.

Next, the operation of the control section 1 of the EFROM according to the present invention will be explained. Referring to Figure 1, when programming, E
Using a PROM programmer, the program/read control circuit 2 receives signals from the EPROM programmer. A control signal for causing the EFROM to enter the program mode is transmitted to the program circuit 4. The program voltage detection circuit 3 detects whether or not the program voltage VPP supplied by the EPROM programmer is appropriate for programming, and transmits appropriate/inappropriate information to the program circuit 4. The program circuit 4 receives a program signal from the program/reading ratio control circuit 2 and a program signal from the program voltage detection circuit 3, and is supplied from the EFROM programmer only when the signals from both are under conditions suitable for programming. The programmed voltage is output to the memory cell selection peripheral circuit 5, and the EFROM is placed in a program enable state.

Address buffer 6 provides address signals to row decoder 7 and column decoder 8 to select a predetermined memory cell 9 based on a signal from the EFROM programmer.

Row decoder 7 and column decoder 8 select word lines and bit lines connected to the control gate and drain of memory cell 9, respectively. At the same time, EFR is applied to the memory cell 9 via the outflow buffer 11.
Predetermined information obtained from the OM programmer is programmed.

At the time of reading after completion of programming, the program/read control unit 2 transmits a signal for controlling the EPROM to read mode to the memory cell selection peripheral circuit 5.

As a result, a predetermined memory cell 9 is selected by the address signal in the same manner as during programming. The sense amplifier 10 senses the information in the memory cell 9 as explained in the explanation of FIGS. 5 and 6, and transmits the contents to the human output buffer 11. The crowd buffer 11 shapes and amplifies the waveform of the information signal and outputs it to the outside.

FIG. 2 is a circuit diagram showing an example of the program voltage detection circuit 3. Referring to FIG. 2, the program voltage detection circuit 3 according to the present invention has a program voltage VP? an N-channel transistor 22 connected between the terminal and the node M and operated in response to the program voltage vrr; an inverter 21 connected between the node M and the ground potential terminal and operated in response to the power supply voltage VCC; , the program voltage VP is connected between the terminal and the ground potential terminal, and the inverter 21
N-channel transistor 25 operates in response to the output of
including. The program voltage VP r wiring connected to the N-channel transistor 25 is connected to a vcc/vPP power supply switching circuit 15 for outputting the internal power supply of the control unit 1 and the memory cell selection peripheral circuit 5, as shown in FIG. It is connected to the memory cell selection peripheral circuit 5.

Inverter 21 includes a P-channel transistor 23 and an N-channel transistor 24, which are connected in series between node M and ground and operate in response to power supply voltage VCC. The threshold voltage of the N-channel transistor 22 is now:
Two types of program voltages, namely 12.5V and 21V
It is assumed that a value between 1 and 2 is selected, for example, 15V.

Next, the operation of the program voltage detection circuit 3 will be explained with reference to diagram m2. First, a case will be described in which the program voltage VPP output from the EFROM programmer and the program voltage VPP of the EPROM are both 12.5V. It is assumed that the power supply voltage VCC is 5V. When program voltage Vpp is 12.5V, N-channel transistor 22 does not turn on because its threshold is 15V. On the other hand, in the inverter 21, the power supply voltage VC
Since C is 5V, the N-channel transistor 24 is turned on and the output voltage of the inverter 21 becomes L''. Therefore, the N-channel transistor 25, which operates in response to the output voltage of the inverter 21, is not turned on.As a result, the program The potential of the voltage vrr wiring remains at 12.5V, and this voltage is applied to the Vcc/Vrp power supply switching circuit 15 and the memory cell selection peripheral circuit 5.

Next, the program voltage VFP of EFROM is 12.5v.
Regardless of the program voltage VP from the EFROM programmer due to incorrect setting of the EFROM programmer,
A case where the voltage becomes 21V will be explained. At this time, first the N-channel transistor 22 is turned on. As a result, the program voltage VPP of 21 V is applied to the source of the P-channel transistor 23 of the inverter 21. At this time, since the power supply voltage VCC is set to 5V, the P-channel transistor 23 is turned on, and the output of the inverter 21 becomes sHs. Since N-channel transistor 25 operates in response to the output signal of inverter 21, N-channel transistor 25 is turned on in this case. As a result, even if the program voltage VPF applied from the EFROM programmer is 21V, this potential is grounded by the N-channel transistor 25, so that the potential of the wiring for the program voltage VP is set to the ground potential.

Therefore, V
A ground potential is applied to the CC/VPP power supply switching circuit 15 and the memory cell selection peripheral circuit 5.

As a result, even if a program voltage higher than a predetermined program voltage of the EFROM is applied from the EFROM programmer, the overvoltage is not applied to each circuit of the EFROM. Therefore, the problem of junction breakdown in the EFROM due to overvoltage being applied to the EPROM due to incorrect settings of the EFROM programmer during programming is solved.

Note that by appropriately adjusting the threshold values of the P-channel transistor 23 and the N-channel transistor 24 that constitute the inverter 21, the operating voltage of the N-channel transistor 25 can be adjusted as appropriate.

Next, the contents of the program circuit 4 will be explained.

The program circuit 4 is for inhibiting program execution when the program voltage VPP is higher than a predetermined potential in response to the output signals of the program voltage detection circuit 3 and the program/read control section 2. FIG. 3 is a circuit diagram showing one embodiment of the program circuit 4 according to the present invention. Referring to FIG. 3, the program circuit 4 according to the present invention includes a NOR circuit 28 connected to the program/read control section 2 and the program voltage detection circuit 3, and a NOR circuit 28 connected to the program/read control section 2 and the program voltage detection circuit 3.
and a NOT circuit 29 connected to the R circuit 28.
The output signal of the T circuit 29 is output to the memory cell selection peripheral circuit 5. The relationship between the output signals of the program/read control section 2 and the program voltage detection circuit 3, and the output signal of the program circuit 4 in each case is shown in the table.

(Left below) Referring to the table, only when the output of the program/read control unit 2 and program voltage detection circuit 3 becomes “Lo”,
EFROM is set to program mode. That is, when the program voltage VPP is higher than a predetermined potential, the EFROM is not programmed. Therefore, E
A program voltage VFP higher than a predetermined value is never applied to the memory selection peripheral circuit 5 of the FROM. As a result, junction breakdown due to application of high voltage to the EPROM can be prevented.

Although the ultraviolet ray irradiation type EFROM has been described in this embodiment, similar effects can be obtained for other nonvolatile semiconductor memory devices that require an external programming power source.

〔Effect of the invention〕

As described above, according to the present invention, an EFROM includes a program voltage determining means for determining whether a program voltage is at a potential higher than a predetermined value; and program voltage lowering means for lowering the program voltage to a voltage lower than a predetermined value.

Therefore, even if the program voltage is higher than a predetermined value, the high voltage is lowered to a lower voltage and execution of the program is prohibited. is not applied to any part of the

As a result, a nonvolatile semiconductor memory device that will not be destroyed even if a program voltage higher than a predetermined value is applied can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an EFROM according to the invention, FIG. 2 is a circuit diagram showing the contents of a program voltage detection circuit according to the invention, and FIG. 3 is a program circuit according to the invention. FIG. 4A is a block diagram showing the overall configuration of a conventional EFROM;
Figure B is a schematic diagram showing the output terminal of the EFROM programmer, Figure 5 is a cross-sectional view showing the structure of one memory cell, and Figure 6 is a diagram showing when information charges are written to and erased from the memory cell. FIG. 7 is a graph showing the relationship between the gate voltage and the drain current when the voltage is changed. FIG. 7 is a schematic diagram of a conventional vcc/Vpo power supply switching circuit. 1 is a control circuit, 2 is a program/read control unit, 3 is a program voltage detection circuit, 4 is a program circuit, 5 is a peripheral circuit for memory cell selection, 6 is an address buffer, 7 is a row decoder, 8 is a column decoder, 9 is a memory cell, 10
11 is a sense amplifier, 11 is an output buffer, and 12 is a memory array. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

Claims: memory cells each having a floating gate and storing information charges; the memory cells being arranged in a matrix in rows and columns, thereby forming an array of memory cells; a memory cell selection section connected to the memory cell selection section for selecting the memory cell; a control section connected to the memory cell selection section for controlling the memory cell and the memory cell selection section; A nonvolatile semiconductor memory, which is connected to a cell selection section and includes an internal power generation means for applying an operating voltage to each of the cells, and receives a write program voltage applied from the outside to write data into the memory cells. In the device, when the data is written, the write program voltage is applied to the memory cell selection section, the control section, and the internal power generation means, and the nonvolatile semiconductor memory device is higher than the predetermined first potential.
program voltage determining means for determining whether the program voltage is at the second potential; and when the program voltage determining means determines that the program voltage is at the second potential, the program voltage is set to a potential lower than the first potential. and program voltage drop means for lowering the program voltage.