JPH02183356A - Main body processing wait control system for line adapter - Google Patents

Abstract

PURPOSE:To improve the processing performance of a line adapter by selecting the main body processing wait of the line adapter in accordance with the throughput of a main body device. CONSTITUTION:After the lapse of a prescribed time, a first processing waiting means 19 monitors the ready state of a main body device 10 by re-reading an adapter side read register 16 according to time monitor by a timer. A second processing waiting means 20 reconnects a task for DMA control to the tail of a ready queue and when an execution schedule is turned again, the ready state of the main body device 10 is monitored by re-reading the adapter side read register 16. A processing wait selecting means 18 selects the first processing waiting means 19 suitable for low speed or the second processing waiting means 20 suitable for high speed in correspondence to a system according to the value of a flag in a main body processing waiting flag part 17. Thus, the vain time of main body processing waiting can be effectively utilized and the processing performance of the line adapter can be improved.

Description

[Detailed Description of the Invention] [Summary] Main unit processing related to the first system for waiting for main unit processing of a line adapter in which the timing for notifying the main unit of data received by the line adapter can be selected according to the performance of the two main units. In order to improve the processing performance of the single-line adapter by making effective use of wasted waiting time, a flag part indicating the type of main unit processing wait in the line adapter and a timer are set when the main unit is busy. The first processing waiting means monitors the ready status of the first main unit by time monitoring, and when the second main unit is in a busy state, the second main unit is connected by connecting the DMA control task to the end of the ready queue. and a processing waiting selection means for selecting either the first processing waiting means or the second processing waiting means depending on the contents of the flag part. .

[Industrial application field]

The present invention relates to a main body processing wait control method for a line adapter in which the timing for notifying the main body of data received by nine line adapters can be selected in accordance with the performance of one main body.

When performing data communication with a terminal, a three-line adapter is used to reduce the processing load on the terminal main unit and to perform control according to one line type and various control procedures. Especially with highly functional line adapters.

It is equipped with a microprocessor and memory, and after multitasking control, the microprocessor executes a program dedicated to the adapter. It is desired to improve the processing performance of such line adapters.

[Conventional technology]

FIG. 7 shows an example of processing of a line adapter according to the conventional method.

When performing data communication with a terminal, a line adapter is used that allows one line type and control procedure to be selected as an option. Normally, a three-line adapter has a microprocessor (MPU) and is installed in a slot of a terminal main unit, and data is received and transferred using DMA between the main unit and the adapter. In order to avoid increasing the burden on the 7 main unit by connecting the line adapter, consideration has been given to placing the program of the procedure section on the adapter side as much as possible.

By the way, the CPU/MPU between the main unit and the line adapter
Due to differences in clocks and clocks, data received by the line adapter may not be immediately notified to the main unit. ■10 The status of the main device is processing (busy) or waiting for DMA from the adapter side (ready).
This can be known by reading the register, but the conventional adapter-side DMA control task monitors the status of one main unit through processing as shown in FIG.

■ Read the I10 register on the adapter side.

■ 5 due to the main unit status flag in I10 registration
Determine whether the main unit is busy or ready. If it is in a busy state, control is returned to process (2) and reading of the I10 register is repeated.

- If it is confirmed that the main unit is in the ready state, start DMA transfer processing for the second main unit.

If the control for three main units is fixed to one type, not only for direct processing waiting like this, even if that control is optimal for one system, the performance of other main units will be degraded. The system wastes every hour and sometimes becomes suboptimal.

Therefore, in order to perform optimal main body processing wait control, there is a problem in that the program for the adapter must be modified each time depending on the system.

The present invention aims to solve the above-mentioned problems and to improve the processing performance of a 5-line adapter by making effective use of the wasted time waiting for processing by two main units.

[Problem to be solved by the invention]

According to the conventional method as described above, the DMA control task on the adapter side simply waits for main body processing.

Because the execution environment of the microprocessor in the line adapter is occupied and other tasks cannot run.

There is a problem that performance deteriorates.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle configuration of the present invention.

In FIG. 1, 110 is the main unit that performs data input/output processing, 11 is C1)U, +2 is memory, 13 is the main unit status write register which is the I10 register that indicates the status of the main unit, and 14 is communication control. Line adapter that performs 15
16 is the microphone co-processor unit (MPU), and 16 is the line adapter 14 that writes the status write register 13 on the main body side.
Adapter side read register which is I10 register for taking J, 17 is non-stop processing 94 (flag section, +8 is processing machine) is also selection means, 19 is first processing waiting means for waiting for processing by timer activation, 20 is task This represents a second processing waiting means that waits for processing by reconnecting the ready queue.

The line adapter 14 has a multitask processing function and transmits and receives data to and from the main unit 10 by l) MA transfer. The status of the main unit 10 is written in the second main unit side status write register 13 and can be referenced via the adapter side read register 16.

The main body processing wait flag unit 17
This flag is used to set the type of two-body processing wait according to the performance of the two main bodies. The flag is not limited to a flag in a narrow sense, but may be something like a type number.

When notifying the non-stop device 10 of the data received from the two lines, the processing waiting selection means 18 determines from the contents of the first main body processing waiting flag unit 17 that the first main device 10 is in a busy state,
First processing waiting means 19 or second processing waiting means 20
This process selects one of the following.

The first processing waiting means 19 is a processing means that monitors the ready state of the non-stop device 10 by re-reading the adapter-side read register 16 when a predetermined time has elapsed by time monitoring using a timer.

The second processing waiting means 20 reconnects the DMA control task that performs the data transfer control '4' 111 to the second main unit 10 to the end of the ready key □-, and reconnects the execution schedule J.
This processing means monitors the ready status of the third main unit 10 by rereading the adapter side read register 16 when the .

[Effect]

If the ready status of the main unit 10 is monitored by a loop of commands as shown in FIG. 7, for example, until the main unit IO reaches the ready status.

Execution control will not be passed to other tasks with lower execution priority levels, and the processing function of the line adapter 14 will temporarily stop.

On the other hand, when the first processing waiting means I9 monitors the ready state of the main unit 10, the DMA control task is put into a waiting state by the timer, so during that time,
Other tasks gain execution control and can execute necessary processing.

In addition, the second processing waiting means 20 causes one main device IO
By monitoring the ready state of the main device 10, the DMA control task will not be in a waiting state, and the ready state of the main device 10 can be determined at high speed. The DMA control task is connected to the end of the ready queue for task control, so execution scheduling allows the task to become ready.
This means that other tasks can be processed until the task reaches the head of the queue.

By changing the value of the flag in the main body processing wait flag section 17, the processing wait selector stage 18 selects the first processing waiting means (9) suitable for low-speed applications or the second processing waiting means (9) suitable for high-speed applications, depending on the system. The processing waiting means 20 can be easily selected.

〔Example〕

Fig. 2 is an example of a system configuration to which the present invention is applied, Fig. 3 is an example of ■/○ registers according to an embodiment of the present invention, and Fig. 4 is a task state for explaining an embodiment of the present invention. transition diagram,
FIG. 5 is an explanatory diagram of task queuing to explain an embodiment of the present invention. FIG. 6 shows a processing flow of an embodiment of the present invention.

In FIG. 2, 30 is a terminal main unit equipped with a CPU, memory, etc.; 31 is a monitor that monitors system operations, manages tasks, and performs various controls; and a monitor 32 that performs processing according to line procedures on the wooden cup side. 33 is a main unit side line procedure section, 33 is a program by which performs input/output control for the display, keyboard, Tisp printer, etc. connected to the terminal main unit 30; 34 is a system service program;
35 is a timer control task, and 36 is a main body side DM that executes the channel inktease program (CIF).
A control task 37 represents a DMA lotus.

In addition, in the line adapter 14 shown in FIG.
), 40 is an adapter side line element +g4 unit that performs processing according to the line procedure on the adapter side, 41 is a system service program that manages buffers, etc., and 42 is for timer control. task.

43 represents a line hardware control section.

The present invention is particularly applicable to the adapter side I) M A control task 3
It is related to the process of 9. The terminal main unit 30 side is the same as the conventional one and there is no change.

The I10 register used as an ink interface between the main body side DMA control task 36 and the adapter side DMA control task 39 shown in FIG. 2, and the part related to the present invention, is as shown in FIG. ing.

When the main body side DMA control '41■ task 36 sets a value in the first main body side status write register 13, the value of the adapter side read register 16 changes in conjunction. This I10
The first hit of the registration disk is 5TSE or 2. This is the main unit status determination flag. When it is “0”, the main unit is busy 7 lie, “1”
” indicates that the second main unit is in a ready state where it can accept DMA transfer.

The monitor 38 shown in FIG. 2 manages tasks in four states, as shown in FIG. 4, in order to control parallel processing of tasks. In Figure 4, RON is microbe 1
” This is the state of execution by Cenoza. REA I) Y is
It is in an executable state. WA1'F is in a state of waiting for an event such as a processing request or an interrupt.

5TOP is in a stopped state.

The task scheduler of the monitor 38 detects the task switching event number and the I) CB (Program Control Rl) connected to the task ready queue.
Execution control is passed to each task in the order of .ock). In this embodiment, the following macro commands are prepared as system macros for changing the state of tasks.

5-EXEC macro 2 starts the specified task.

5-CANL macro: Stops the specified task.

S-3T Or) Macro: Brings the invoking task to a stopped state.

5-WAIT macro: Puts the invoking task into an event wait state.

5-P05T MacrJ: Make the specified task ready.

S-SEN D? Black: Sends a buffer to the specified task and makes it ready.

SR”rN macro: Connects the invoking task to the end of the ready queue.

As shown in FIG. 5, the task ready queue that manages tasks in the ready state is
It is designed to chain CB. In FIG. 5, 50 is a ready queue of tasks, 51-1 to 51
-4 is a PCB that stores program control information for each task.
It is.

FIG. 6 shows an example of the processing related to the present invention performed by the adapter-side DMA control task 39 shown in FIG. Hereinafter, the process will be explained according to the processes ① to ② shown in FIG.

■ When notifying the terminal main unit 30 of received data,
First, in order to check the status of the main unit, use 110 on the adapter side.
Register, that is, adapter side read register 16
I Read.

(2) Check the main unit status determination flag of 5TSE shown in FIG. 3 to determine whether the 1 main unit is in a busy state or a ready state. If it is in the ready state, proceed to process ■.

(2) If the main unit is in a busy state, check the value of the main unit processing wait flag unit 17 shown in FIG. When this flag is 1", the process moves to process (2), and when this flag is "O", the process moves to process (2).

(2) Issue the S-RTN macro, connect the invoking task to the end of the ready queue, and when execution control returns again, repeat the process (2) and the subsequent steps.

■ When the value of the main body processing wait flag section 17 is “0”, 1
A predetermined monitoring time on the order of ms to looms is set as a parameter of the S-TIME macro that is issued primarily.

■ Issue the S-TIME macro. The S-TIME macro is a one-clock instruction that allows the timer control task 42 shown in FIG. 2 to monitor time and execute the tasks of the five issuers when a specified time has elapsed. When control returns, the process returns to process (2) and the process is repeated in the same manner.

- When the main unit becomes ready, start DMA processing for one main unit and transfer the received data.

When the 5-RTN macro is issued by the above process (2), the adapter side DMA control task (
PCB5m-2 with MIF>39.

It will be connected to the end of the ready queue at the same level. If there is a PCB for another task at the head of the queue, that task will be executed next. In Figure 5, 5 tasks A
will enter the RUN state and be executed. If there are no other tasks in that queue, the secondary level ready queue is searched and task B is executed.

After that task is executed, scheduling is performed for the level 1 ready queue, so next the adapter side D
If the PCB 51-2 of the MA control task 39 is at the head of the queue, 5 execution control is passed.

In this way, if you use the 5-RTN macro, monitor 38
After the other tasks have finished, control is returned to you, but the time it takes is usually less than 2 ms.

This is effective if the processing speed of the main unit is fast.

On the other hand, if you use the S-TIME macro provided in the monitor 38, it is possible to release control in units of, for example, 1ms to 1001ns, and when the specified time is reached, control is returned to the own task. This is effective when processing on the main unit takes a long time.

Which one to choose depends on the receiving performance of the main unit, for example,
Run the test application program and measure it across other workstations.

If the double-sided display of an application is slow, this can be determined by performing a memory dump etc. during reception and checking the internal state of the adapter.

If the sofa is always waiting to receive notifications from the first device, you can see that the processing on the second device is slow, so the S-
All you have to do is wait for main body processing using the TIME macro. Otherwise, it waits for main body processing by the 5-RTN macro.

When the program for the line adapter 14 shown in FIG. 2 is loaded from the terminal main unit 30 at the time of initialization, in the program module managed by the terminal main unit 30, the main unit processing waiting flag shown in FIG. Part 1
By patching flag 7, you can easily install S-TI.
It is possible to switch between using the ME macro or using the S-RTN macro. In addition, the environment setting program in the terminal main unit 30 sets the main unit processing wait flag section 1
7 may be updated.

Furthermore, when using the S-TIME macro, the specified time can be specified statically or dynamically from the outside depending on the processing capacity of the two main units, thereby realizing an appropriate amount of time for waiting for main unit processing. be able to.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to easily select the main body processing waiting state of the one-line adapter according to the processing capacity of the three-line adapter, and the parallel processing performance of tasks in the two-line adapter can be improved. The processing performance of the 3-line adapter is improved.

[Brief explanation of the drawing]

FIG. 1 shows the basic configuration of the present invention. FIG. 2 shows an example of a system configuration to which the present invention is applied. FIG. 3 is an example of the I10 register according to an embodiment of the present invention. FIG. 4 is a state transition diagram of a task for explaining an embodiment of the present invention. FIG. 5 is an explanatory diagram of task queuing for explaining an embodiment of the present invention. FIG. 6 is an embodiment of the present invention. Example Processing Flow FIG. 7 shows an example of processing of a line adapter according to the conventional method. In the figure, 10 is a main unit, 11 is a C1), 12 is a memory, 13 is a main body side state writing register, 14 is a line adapter, and 15 is a micro processor. Reference numeral 16 represents an adapter side read register, 17 a main body processing wait flag section, 18 a processing wait selection means, 19 a first processing wait means, and 20 a second processing wait means.

Claims (1)

[Claims] A line adapter (14) that performs communication control and is equipped with a microprocessor (15), has a multitask processing function, and transmits and receives data to and from the main device (10) by DMA transfer. A flag section (17) indicating the type of main unit processing waiting in the line adapter, and a first process for monitoring the ready state of the main unit by time monitoring using a timer when the main unit is in a busy state. Waiting means (19); and second processing waiting means (2) for monitoring the ready state of the main unit by connecting a DMA control task to the end of the ready queue when the main unit is in the busy state.
0); and processing waiting selection means (18) for selecting either the first processing waiting means or the second processing waiting means according to the contents of the flag part. Main body processing wait control method.