JPH02183324A - A/d converter - Google Patents

Abstract

PURPOSE:To suppress external noise and to stabilize comparison operation by adding a circuit, which is composed of a resistor and diode, to an integrator. CONSTITUTION:In an integrator 1, a diode D is inserted and connected between the output edge of an OP amplifier U1 and an integrated capacitor C1 so as to be reverse to a direction, in which an integration current flows, and a resistor R1 is parallelly connected to the diode D. Then, a resistor R2 is inserted and connected between the connecting point, which is between the diode D and integrated capacitor C1, and a common potential. The resistors R1 and R2 and diode D give a non-linear characteristic to the integrator 1 and near a comparison point, the output of a comparator 4 is widely switched from gain 1 to the gain which is determined by the resistors R1 and R2. Then, the inversion speed of the comparator 4 is improved. Thus, since the gain of the integrator 1 can be improved, the external noise can be suppressed without damaging stability.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a double integration type A/D converter, and more specifically, to an integrator that switches input analog voltage and reference signal for input and integration. , relates to a double integration type A/D converter equipped with a comparator that compares the output of the integrator and a common potential.

<Prior Art> FIG. 7 is a block diagram of a conventionally known double integral type A/D converter. In the figure, Sl is the input analog signal E
A switch I that switches between x and the reference signal Es.
NT is an integrator that integrates the signal taken out by the switch S1, and is composed of a resistor R, a capacitor C5, an amplifier A, and a switch S2 connected in parallel with the capacitor C.

CP is a comparator that compares the output of the integrator with a common potential, and O8 is a clock oscillator that controls on/off of the switch 5IS2. CU is a counter that counts clocks, and its counting operation is controlled by a signal from the comparator CP.

DS is a display device that displays the output of the counter.

The switch S1 first inputs the input signal Ex to the integrator INT for a certain period of time Ts as shown in FIG.

As a result, the output of the integrator IN'f' changes as shown in FIG. 9, and the integrator output Eo after Ts is expressed by equation (1).

Eo= (-Ex/ (C-R)) ・Ts...
(1) Next, the switch S1 inputs the reference voltage Es to the integrator INT as shown in FIG.

The integrator output Eo at this time is expressed by equation (2).

Eo= (-Ex/ (C-R)! ・Ts+
(Es/ (C-R)l · t...(2) Here, if the time until the output voltage EO becomes zero is TX, then equation (3) is obtained.

Ex-(Tx/Ts)-Es-(3) Therefore, if the integration time Ts and the reference voltage ES are constant, the input signal Ex is TX, that is, the switch S1 is at the reference voltage E.
By counting the time from when the output voltage EO is connected to the s side until the output voltage EO becomes zero with the counter CU, a digital signal corresponding to the input analog signal EX can be obtained in the counter.

<Problem to be Solved by the Invention> The A/D converter having such a configuration has features such as no drift or error in the integral constant CR and clock frequency. However, if the gain of the comparator is increased to obtain high resolution, the operation of the counter becomes unstable.
Switch 81. Since the circuit impedance near S2 and the capacitor is high, noise is easily mixed in, and when noise is mixed in, there is a problem that it affects the comparison operation of the comparator.

The present invention was made in view of these problems, and
The purpose is to compress external noise and realize an A/D converter with a simple configuration that provides stable comparison operations.

<Means for Solving the Problems> FIG. 1 is a basic configuration block diagram of the present invention. In the figure, ■ is an integrator, which includes an OP amplifier U1 and an integrating capacitor C1. 2 is a reference power supply; 3 is a switch circuit; a switch SO1 input analog signal EX for short-circuiting the integrating capacitor C1; switches SL and S2 for switching the reference earth ES and supplying it to the integrator 1;
Contains. 4 is a comparator that compares the signal from the integrator 1 with a common potential, and 5 is a counting/arithmetic control means to which the signal from the comparator 4 is input.

In the integrator 1, D is a diode inserted and connected between the output terminal of the OP amplifier U1 and the integrating capacitor C1 so as to be opposite to the direction in which the integrated current flows, and R1 is connected in parallel to the diode D. The resistor R2 is inserted and connected between the connection point of the diode D and the integrating capacitor C1 and the common potential.

Function> The resistors R1, R2 and the diode D provide the integrator 1 with nonlinear gain characteristics. Due to these, the output of the comparator largely switches from a gain of 1 to a gain determined by the resistors R1 and R2 near the comparison point of the comparator, increasing the inversion speed of the comparator.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, parts corresponding to those in FIG. 1 are designated by the same reference numerals. In integrator 1, R3 is a tummy load resistor for stabilizing the integrator output during the integrator reset I-period.

U2 is an OP amplifier that constitutes the comparator 4, and its input stage is equipped with a resistor R4° and a capacitor C to reduce noise components.
A low pass filter consisting of 2 is provided.

The counting/arithmetic control unit 5 uses a microprocessor that includes a counter 51 as a counting means therein. In addition to the counter 51, the microprocessor 5 includes a tally clock source 52, an output board 53 that operates in synchronization with the tally clock from the clock source 52, an arithmetic control unit (CPU) 54,
It includes a memory 55.

The operation of the apparatus configured in this way will be explained next.

FIG. 3 is a time chart 1- showing an example of the operation. In the figure, TO is in an initial state, switch SO of switch circuit 3 is on as shown in (a), and capacitor C of integrator 1 is short-circuited. In this state, the integrator 1 is in a reset state and its output voltage eA is caused by the voltage signal +V applied via the resistor R3.
A few voltages 0 in the negative polarity direction are output.

The next period T1 is an input integration period, during which the switch S1 is on as shown in (b), and the current ix proportional to the input analog signal EX is integrated for a certain period of time through the resistor R.

'l'2 is the inverse integration interval. In this section, the switch S2 is turned on as shown in (c), and the constant current value Is shown by equation (4) is inversely integrated.

I5=-Es/R・+++++++++ (4) The operation of the input integral interval TI and the inverse integral interval T2 is the same as that of a general double integral circuit, and is the same as that of the conventional device shown in Fig. 7. It is.

The comparator 4 receives the output voltage eA of the integrator 1 as shown in (d).
and the reference potential are compared and amplified, and as shown in (e), H(
A digital signal eB of high level)/L (low level) is input to the microprocessor 5.

The microprocessor 5 receives the digital signal from the comparator 4, generates timing signals TO to T2, operates the switch circuit 3, and changes the output eB of the comparator 4 from H to l- from the start of the 1゛2 interval. The time T until it changes to
Count X with a counter 51. As a result, the digital signal corresponding to the input analog signal Ex is transferred to the counter 51.
You can get it within.

The above is an outline of the operation shown in FIG. 2.Next, the nonlinear gain section (third
The operation of the part surrounded by O in Figure (d) will be explained.

FIG. 4 shows the current-voltage characteristics in the nonlinear gain section, and FIG. 5 shows an enlarged view of the nonlinear gain section. Note that in these figures, the current i5 flowing through the resistor R3 is ignored. Also, the same marks indicate corresponding points in time.

In FIG. 3, in the interval T2, the integrator 1 is connected to the reference voltage -E
s is integrated, and the potential eA1 at the connection point between the resistors R1 and R2 increases linearly from a negative potential.The integrator 1 performs the following operation depending on the value of this potential eA1.

(a) If eAl<eAl, c, where e A 1. c is eAl at the time of gain switching
(See FIG. 5) The connection point potential e A 1 is a negative potential as is clear from FIG. 5, and the current 12 flowing through the resistor R2 has a direction as shown in FIG. This current 12 is passed through the diode D
A current i3 flows through the resistor R1, a current i4 flows through the resistor R1, and an integrated current 11 flows through the capacitor C1.

At this time, the current i3 forward biases the diode D, so the potential difference (F) across the diode is always constant.

As a result, the equivalent circuit of the integrator 1 in this state is as shown in FIG. 6(a), and its output gain is 1. Furthermore, the output voltage eA to the comparator 4 is the connection point potential e
Compared to A1, the unidirectional voltage VF of diode D is lower.

(b) eA1=eA1. In the case of c, when the potential of the connection point eA1 gradually increases, the resistance R
The current 12 flowing through 2 decreases and reaches a point e A 1-c where 12=il+i4.

At this time, the current j3 flowing through the diode D becomes zero.

(c)e A1. > e A i c case,
Since (eAl-eA)<VF, the diode D is cut off and the current is 13-0.

At this time, the integrator 1 becomes an equivalent circuit as shown in FIG. 6(b), and its output gain is (R1+R2)/R2
becomes.

As mentioned above, the integrator 1 is near the comparison point (eA1=eA1
In c), since the gain increases, the inversion speed of the comparator 4 increases. This eliminates jitter and lag caused by insufficient gain of the comparator 1. Furthermore, as shown in FIG. 2, if a low-pass filter consisting of a resistor R4 and a capacitor C2 is inserted into the input stage of the comparator 4, it is possible to reduce external noise, but the gain of the integrator 1 is If it remains at "1", it will lead to increased instability in the comparison operation, but by applying the present invention, the gain of the integrator can be increased, so external noise can be compressed without any loss in stability. becomes possible.

<Effects of the Invention> As described above in detail, according to the present invention, by adding a simple circuit, it is possible to compress external noise and provide an A/D converter with stable comparison operation.

[Brief explanation of the drawing]

Figure 1 is a basic configuration block diagram of the present invention, Figure 2 is a configuration block diagram showing an embodiment of the present invention, Figure 3 is a waveform diagram for explaining the outline of its operation, and Figure 4 is a waveform diagram for explaining the outline of its operation. Figure 3 shows the current-voltage characteristics of the nonlinear gain section, Figure 5 is an enlarged view of the nonlinear gain interval, Figure 6 is an equivalent circuit of the integrator, Figure 7 is a block diagram of the configuration of the conventional device, and Figure 8 and FIG. 9 is an operation waveform diagram thereof. 1... Integrator, 2... Reference power supply, 3...
Switch circuit, 4... Comparator, 5... Counting/arithmetic control means, R1, R2... Resistor, D... Diode, C1...
・Integrator capacitor, 6th one (α) Ct No. 2 (b)

Claims (1)

[Claims of Claims] A double integration type A/D comprising an integrator that switches and integrates input analog voltage and reference signal, and a comparator that compares the output of this integrator with a common potential. In the converter, a diode is inserted and connected between the output terminal of the OP amplifier constituting the integrator and the integrating capacitor in a direction opposite to the direction in which the integrated current flows, and connected in parallel to this diode. and a resistor inserted and connected between a connection point between the diode and the integrating capacitor and a common potential.