JPH02182031A - Unlock detection method for pll circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction such as unlock display during synchronization pull-in by comparing an input voltage of a voltage controlled oscillator with a threshold voltage of a prescribed level so as to detect the unlock state of a PLL. CONSTITUTION:When a large ripple takes place in an input voltage Vin with respect to a voltage controlled oscillator 1 due to an external disturbance and an output is obtained from a terminal Q of a flip-flop 18 synchronously with a reference signal fr with an output from a comparator 16 in a timing t1 operated by the flip-flop 18. Even during the grating scanning period, since the output level is less than a reference voltage Vref2, an output is obtained from a comparator 17 in a timing t2. Then an output is obtained from a terminal Q of a flip-flop 20 synchronously with the reference signal fr. Thus, an LED 24 is lighted and it is displayed that a PLL system remains still in the unlock state regardless of the elapse of a pull-in time Tp.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for detecting unlocking of a PLL circuit used for generating a pixel clock in a multi-point synchronization type optical writing device or the like.

2. Description of the Related Art Conventionally, in an optical scanning optical system of an optical writing device such as a laser printer, a laser beam for scanning is generally deflected and scanned by a deflector such as a rotating polygon mirror. In order to properly perform such optical scanning, a synchronization signal is required to time the optical scanning. Therefore, in general, the laser beam is received by a single light-receiving element placed at a position on the scanning optical path of the laser beam on the scanning start side and outside the image range, and a synchronization signal is obtained by this light-receiving element. The laser beam is modulated by image information in synchronization with the signal. However, since this method synchronizes only at the start of scanning, at the end of the image, the speed or timing of optical scanning does not necessarily change for each scan due to uneven rotation of a deflector such as a rotating polygon mirror, uneven processing accuracy, etc. is not constant. This allows dot arrangement accuracy,
In other words, print quality etc. deteriorate.

For this reason, a multi-point synchronization method in which reference pulses are provided at a plurality of points in one scanning line area has been considered. this is,
As shown in Japanese Patent Laid-Open No. 60-10967, a pixel clock is generated using a grating (also called a slit, grid, or scale), and as shown in Japanese Patent Laid-Open No. 60-75168, , which uses a concave mirror array and a plurality of small-diameter light receiving elements (for example, bin photodiodes).

FIG. 3 shows an example of a recording apparatus employing such a multi-point synchronization system and using a laser scanning optical system using a semiconductor laser as a light source. First, a recording semiconductor laser 1 is provided which emits a recording beam P modulated by a pixel signal. This recording beam P is deflected by one surface of the rotating polygon mirror 2, passes through the fO lens 3, is reflected by the mirror 4, and is imaged on the photoreceptor 5, as shown by the scanning line 6. Perform recording scanning. On the other hand, the synchronizing beam P5 emitted from the synchronizing semiconductor laser 7 provided separately from the semiconductor laser l is located at a certain distance from the beam P1 on the same reflecting surface of the polygon mirror 2 (at the same position in the main scanning direction). ), the beam P,
Similarly, the light is incident on the fO lens 3. After passing through the f.theta. lens 3, the beam P passes over a mirror 4 and scans a grating 8 disposed at a position optically equivalent to the photoreceptor 5, since the upper and lower positions are different. The beam P that has passed through the transparent part of the grating 8 is transmitted to the lens array 9.
The light is sequentially focused and imaged onto a plurality of, for example, four, light receiving elements 10a to 10d, and a reference pulse signal Pr is generated from these light receiving elements 10a to 10d. That is, the light-receiving signals received by these light-receiving elements 10a to 10d and photoelectrically converted are each amplified and then added by an adding circuit. As a result, the reference signal fr, which is a pulse train signal over the entire scanning length according to the bright and dark arrangement of the grating 8, is obtained, and after being subjected to waveform shaping by a waveform shaping circuit as necessary, the
A pixel clock fo is generated by processing by an LL (phase locked loop) circuit.

Here, the structure and operation of such a PLL circuit will be explained with reference to FIG. First, the reference signal Sr, which is an input signal to the PLL circuit 11, is input to the voltage controlled oscillator (VCO) 12.
The pixel clock fo output from the frequency divider 13 is divided into 1
The phase difference between the feedback signal fb and the feedback signal fb obtained by frequency division by /N is compared in the phase comparator 14. The output from the phase comparator 14 is then passed through a low-pass filter (LPF) 15 that removes noise and high frequency components to the voltage controlled oscillator 12.
The voltage controlled oscillator 12 is feedback-controlled so that the reference signal fr and the feedback signal fb are in phase with each other. As a result, the voltage controlled oscillator 12 outputs a pixel clock f which is phase synchronized with the reference signal fr and which is multiplied by N.
O occurs.

Such a PLL circuit 11 provides a pixel clock fo that follows changes in scanning speed (changes in frequency of reference signal fr).

Therefore, recording is performed while modulating the pixel-corresponding recording information output from the printer controller or host machine to the recording semiconductor laser drive modulation circuit in synchronization with the pixel clock fO from the PLL circuit 11. , exposure recording with high dot arrangement accuracy becomes possible. In other words, even if the scanning speed fluctuates due to uneven rotation of the rotating polygon mirror during recording, the modulation timing of the semiconductor laser is controlled by the pixel clock fo, making it possible to perform proper optical writing. be.

By the way, when the output of the PLL circuit is used to generate the write pixel clock of a laser printer or the like in this way, the reference signal fr input to the phase comparator 14 is controlled by the scanning of the grating 8, as shown in FIG. 5(a). It becomes intermittent at times and when not scanning. At this time, the output voltage V from the low-pass filter 15 that controls the oscillation frequency of the voltage controlled oscillator 12
As shown in FIG. 5(b), in has large ripples (oscillations) both at the time when the reference signal fr starts inputting and at the time it stops inputting, and has a time constant determined by the loop gain of the PLL system (here Then, P L L pull-in time - synchronization establishment time) settles to steady values V and V. Here, the steady value V is the oscillation frequency f of the voltage controlled oscillator 12.
o is the value when synchronized with the reference signal fr which is the input signal, and the steady value V1 is the value when the voltage controlled oscillator 12 is oscillating at the free running frequency. The actual pixel clock fo needs to be output with the PLL system in a locked state when the PLL system has settled down to the steady-state value Vo.

Problems to be Solved by the Invention By the way, the input terminal Vin for the voltage controlled oscillator 12
(Output of the low-pass filter 15) causes large ripples as shown in FIG. 5(c) due to disturbances, etc., and remains at the steady value V even after the pull-in time Tp has passed.

Sometimes I have a hard time calming down. However, as the pull-in time Tp elapses, the PLL system becomes locked, and the pixel clock fo may be output in an unstable manner. In the second situation, the image quality deteriorates due to the disturbance of the pixel clock fo. Therefore, it is necessary to accurately detect the unlocked state so as not to output the mother pixel clock in such an unstable state.

Means for Solving the Problem A phase comparator, a low-pass filter, a voltage-controlled oscillator, and a frequency divider are connected in a loop, and a feedback signal obtained by dividing the oscillation output from the voltage-controlled oscillator by the frequency divider is sent to the phase comparator. In an optical writing device using a PLL circuit that compares the phase with a reference signal, passes it through a low-pass filter, inputs it to the voltage-controlled oscillator, and outputs a pixel clock in a locked state phase-synchronized with the reference signal. The PL is determined by comparing the input voltage of the oscillator with a threshold voltage of a predetermined level.
Detects the unlocked state of L.

Also, after the reference signal is input to the phase comparator, the input voltage of the voltage controlled oscillator after a predetermined set time has passed is PL.
It was used to detect unlocking of L.

When the PLL system is unlocked, the input voltage of the voltage controlled oscillator will oscillate greatly around a certain reference value, so unlocking can be accurately detected by using a threshold voltage at a predetermined level for this input voltage. can.

In particular, by using the input voltage of the voltage controlled oscillator after a predetermined set time has elapsed after the reference signal is input to the phase comparator for unlock detection, it is possible to perform unlock display etc. during synchronization pull-in. No malfunctions will occur.

Embodiment An embodiment of the present invention will be explained based on FIGS. 1 and 2. The same parts as shown in FIGS. 3 to 5 are used as they are.

In this embodiment, the unlocked state of the PLL system is detected using the input voltage Vin of the voltage controlled oscillator 12, and two comparators 16 are connected to the input voltage Vin from the low-pass filter 15 to the voltage controlled oscillator 12.
, 17 are provided.

Here, the comparators 16 and 17 compare different reference voltages Vref, . . . Vref, which serve as threshold voltages, with the input voltage Vin. On the output side of the comparator 16, a two-stage flip-flop 18.
19 are connected. Furthermore, two stages of flip-flops 20 and 21 are connected to the output side of the comparator 17. A reference signal fr is input to the clock terminals of these flip-flops 18 and 20. Further, a predetermined pulse signal To, which will be described later, is input to the clear terminals of any of these flip-flops 18 to 21 to control their operation. The outputs of these flip-flops 19 and 21 are connected via an OR gate 22 and a buffer 23 to an unlock display LED 24.

Here, the output of the low-pass filter 15, ie, the input voltage Vi of the voltage controlled oscillator 12, contains a very small ripple component even in a steady state. The upper limit value is the reference voltage Vref of the comparator 16, and the lower limit value is the reference voltage Vr6f of the comparator 17.

That is. Also, flip-flops 18 to 21
As shown in FIG. 2(C), the signal To for
A pulse signal that rises at the timing when the time required for the system to stabilize, that is, the pull-in time Tp required for the output fo of the voltage controlled oscillator 12 to be phase-synchronized with the reference signal fr, has elapsed, and falls in the state of the reference signal fr. It is.

In such a configuration, four flip-flops 18
21 are controlled in operation by a pulse signal To, and become operational after the pull-in time Tp has elapsed during the grating scanning period. At this time, the input voltage Vin to the voltage controlled oscillator 12 becomes the reference voltage V as shown in FIG. 2(b).
If the condition is such that it settles within ref, , V ref, both comparator]6°17 outputs become L level. Therefore, output is output from both the path on the flip-flop 18.19 side and the path on the flip-flop 20.21 side, and the LED 24 does not emit light. Therefore, after the pull-in time Tp has elapsed, the PLL system settles into a stable state, and the clock pixel fo is output as a stable locked state.

As shown in FIG. 2(d), consider a case where a large ripple occurs in the input voltage Vin to the voltage controlled oscillator 12 due to a disturbance or the like. That is, in such a case, the input voltage Vin does not fall within the range of the reference voltages Vref', .about.Vref' even after the pull-in time Tp has elapsed. Then, at the timing when the flip-flop 18 operates, an output is output from the Q of the flip-flop 18 in synchronization with the reference signal fr based on the output from the comparator 16.

That is, the output of the comparator 16 is latched into the flip-flop 19 using the reference signal fr. Therefore, an output is also output from the flip-flop 19 at the subsequent stage, the LED 24 emits light, and it is displayed that although the pull-in time Tp has elapsed, the PLL system is in the unlocked state. On the other hand, in the case shown during the next grating scanning period, even if the pull-in time Tp has elapsed, the reference voltage Vref, ~Vre
Since the pressure is not within the range of r, and is below the base*m pressure Vr13r*, an output is output from the comparator 17 at timing t1. Then, an output is output from Q of the flip-flop 20 in synchronization with the reference signal fr. Therefore, an output is also output from the flip-flop 21 in the subsequent stage,
Although the LED 24 emits light and the pull-in time Tp has passed, P
It is displayed that the LL system is in an unlocked state.

As described above, according to the present embodiment, the reference voltage Vref, with respect to the input voltage Vin of the voltage controlled oscillator 12.

Since the unlocked state is detected using Vref, it is possible to accurately detect the locked/unlocked state of the PLL system. In particular, since the input voltage Vin largely oscillates around a certain reference value, it is easy to detect the unrotated state. Furthermore, since the operations of the flip-flops 18 to 21 are controlled by the pulse signal TO corresponding to the pull-in time Tp, during the off state of the reference signal fr (during non-scanning of the grating) and the pull-in time Tp of the PLL system,
Even if there is a large ripple in the input voltage Vin, a malfunction such as detecting it as unlock does not occur.

Since the reference signal fr is used as the clock for these flip-flops 18 and 20, the LED 24 will not be erroneously lit due to noise or the like.

In this embodiment, unlock detection is displayed by lighting the LED 24, but the present invention is not limited to this, and unlock information may be provided to the system drive circuit, for example.

Effects of the Invention In the present invention, as described above, the unlock state is detected using a threshold voltage of a predetermined level with respect to the input voltage of the voltage controlled oscillator. Therefore, when the lock is released in the PLL system, Since the input voltage of the voltage controlled oscillator oscillates greatly around a certain reference value, unlocking can be detected accurately by using a threshold voltage of a predetermined level for this input voltage. Since the input voltage of the voltage controlled oscillator after a predetermined set time elapses after the reference signal is input is used for unlock detection, malfunctions such as unlock display during synchronization pull-in do not occur.

[Brief Description of the Drawings] Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a timing chart showing waveforms, and Fig. 3 is a schematic perspective view of a general multi-point synchronization type optical system. , FIG. 4 is a block diagram of a general PLL circuit, and FIG. 5 is a timing chart showing waveforms. 12... Voltage controlled oscillator, 13... Frequency divider, 14...
... Phase comparator, 15 ... Low-pass filter, fr.
...Reference signal, f. ...Pixel clock, Vjn...Input voltage Applicant Rico Co., Ltd.

Claims (1)

[Claims] 1. Connect the phase comparator, low-pass filter, voltage-controlled oscillator, and frequency divider in a loop, and compare the phase of the feedback signal obtained by dividing the oscillation output from the voltage-controlled oscillator with the reference signal using the phase comparator. After passing through a low-pass filter,
In an optical writing device using a PLL circuit that is input to the voltage controlled oscillator and outputs a pixel clock in a locked state in phase synchronization with the reference signal, the input voltage of the voltage controlled oscillator is compared with a threshold voltage of a predetermined level. Detecting the unlocked state of the PLL by
LL circuit unlock detection method. 2. The PLL circuit according to claim 1, wherein the input voltage of the voltage controlled oscillator after a predetermined set time has elapsed after the reference signal is input to the phase comparator is used for PLL unlock detection. unlock detection method.