JP2566229B2 - Optical scanning device - Google Patents

Description

TECHNICAL FIELD The present invention relates to an optical scanning device, and more particularly to a synchronous position detection device.

2. Description of the Related Art Generally, an optical scanning device is used in an image forming device such as a laser printer, a reading device, or the like. This optical scanning device forms a scanning beam (scanning light) by deflecting a light beam by a rotary polygon mirror or a rotary deflector such as a deflector that rotates a hologram disk having a linear diffraction grating formed by a hologram. The surface to be scanned is scanned with this scanning beam to write information on the surface to be scanned or to read information on the surface to be scanned.

In such an optical scanning device, when the light beam is deflected by the rotary deflector, the scanning beam is caused by a manufacturing error of the rotary polygon mirror or the hologram disk or a mechanical error in the mechanical rotation. Strictly speaking, the repetition of the deflection is not the same period.

On the other hand, in the scanning of the surface to be scanned by the scanning beam, the starting point of the scanning region, that is, the starting point of scanning by the scanning beam is aligned in order to prevent the distortion of the image due to the jitter in the reproduced image of the written image or the read information. There is a need.

Therefore, conventionally, an optical sensor having a circular light-receiving surface for receiving the scanning beam is arranged outside the scanning area, and when the scanning beam incident for each deflection is incident, that is, the rising position of the output of the optical sensor is the synchronous detection position. However, the number of clocks of the image scanning clock is counted by a predetermined number based on this synchronous detection position, and the optical scanning is performed after the counting is completed.

However, if the rising position of the output of the optical sensor having the circular light receiving surface is set as the synchronous detection position, the rising timing of the output of the sensor varies due to the variation of the scanning height of the scanning beam, and thus the accurate detection is performed. However, there is the inconvenience that a good synchronization detection position cannot be obtained, and thus a high quality image cannot be obtained.

Object The present invention has been made in view of the above points, and an object thereof is to improve the accuracy of the synchronization detection position.

In order to achieve the above-mentioned object, the present invention provides an optical scanning device which uses a rotary deflector to periodically deflect a light beam to optically scan a surface to be scanned. And a means for outputting a synchronization detection signal based on the output of the light sensor when the light beam is received, and a width in the optical scanning direction of the synchronization detection signal output by the means. A means for counting by a signal and a means for calculating the position of 1/2 of the count value by the means are provided,
The position calculated by the means is determined as the synchronization detection position.

Hereinafter, a specific description will be given based on an embodiment of the present invention.

FIG. 1 is a schematic configuration diagram showing a main part of an optical scanning device embodying the present invention.

This optical scanning device collimates a laser beam emitted from a semiconductor laser 1 by a collimator lens (not shown), and then forms a waveform through a first cylindrical lens 2 and a half-wave plate 3, The light enters the rotary polygon mirror 4 that rotates in the indicated direction.

Then, the light beam which is deflected by the rotary polygon mirror 4 and becomes the scanning beam is incident on the photoconductive photoconductor 7, which is a surface to be scanned, through the θ lens 5 and the second cylindrical lens 6. The second cylindrical lens 6
Is a lens for correcting surface tilt, and is for keeping the reflection point of the rotary polygon mirror 4 and the surface to be scanned in a conjugate relationship with the θ lens 5 in the sub-scanning direction.

Then, outside the scanning region of the light beam (scanning beam), a photodetector (light detecting device) as a synchronization detecting sensor having a line-symmetrical light-receiving surface, for example, a circular or elliptical light-receiving surface, on a line segment orthogonal to the scanning direction of the scanning beam. Sensor) 8
Prior to scanning (main scanning) of the surface to be scanned by the scanning beam, the scanning beam is made incident on the photodetector 8 via the third cylindrical lens 9.

FIG. 2 is a circuit diagram showing an example of the synchronization detection signal generating circuit.

The synchronization detection signal generation circuit 11 amplifies the output of the photodetector 8 which receives the scanning beam by the transistor 12 and then shapes the waveform by the comparator 13 to obtain the synchronization detection signal DETP.
Output as

FIG. 3 is a block diagram showing an example of a write control circuit including a synchronous detection position determination circuit.

The basic clock generation circuit 21 determines the N of the image clock WCLK as the write synchronization clock according to the writing accuracy 1 / N dot.
Outputs double clock CLKN. The frequency dividing circuit 22 divides the clock CLKN from the basic clock generating circuit 21 into 1 / N and outputs the basic clock CLKD of the image clock WCLK.
The shift register 23 has a clock CLKN from the basic clock generating circuit 21 and a basic clock CL from the frequency dividing circuit 22.
Input KD and have N clocks CLKR that have the same period as the basic clock CLKD that is out of phase with each other by the clock CLKN period.
Is output.

The DETP width counting circuit 25 inputs the sync detection signal DETP from the sync detection signal generation circuit 11 and the clock CLKN from the basic clock generation circuit 21 to clock the width of the sync detection signal DETP.
Count the accuracy of CLKN. The DETP / 2 position calculation circuit 26 calculates the position of 1/2 of the width of the synchronization detection signal DETP from the DETP width counting circuit 25. The DETP width counting circuit 25 and the DETP / 2 position calculating circuit 26 constitute a synchronization detection position determining circuit. The WCLK trigger generation circuit 27 receives the calculation result of the position of 1/2 of the width of the sync detection signal DETP from the DETP / 2 position calculation circuit 26 and receives 1 / N at the position of 1/2 of the width of the sync detection signal DETP. The trigger signal TRG is output so that the image clock WCLK that is phase-synchronized with the dot precision of is obtained.

The data selector 28 is the clock from the shift register 23.
Trigger signal TR from WCLK trigger generation circuit 27 from among CLKR
A clock corresponding to G is selected and output as an image clock WCLK-1.

The correction WCLK generation circuit 29 outputs the correction image clock WCLK-2 when the length from the center position of the light receiving surface of the photodetector 8 to the rear end is longer than one image clock WCLK. That is, the image clock WCLK, which will be described later, is a write start synchronization signal.
It also serves as a reference clock for the counter to generate LSYNC, write area signal LGATE, and laser light setting signal ERASE outside the write area.
Since the number of occurrences of K does not match, the number of occurrences of the image clock WCLK must be corrected so as to be the number counted from the center position of the light receiving surface of the photodetector 8.
The WCLK generation circuit 29 outputs the correction image clock WCLK-2.

The OR circuit 30 is the image clock WC from the data selector 28.
The image clock WCLK is obtained by ORing the LK-1 and the correction image clock WCLK-2 from the correction WCLK generation circuit 29.
Output as

Next, regarding the operation of this synchronization detection position determination circuit,
It will be described with reference to the drawings.

As shown in FIG. 4 (a), the light receiving surface of the photo detector 8
When 8a has an elliptical shape (or may be circular) which is line-symmetric with respect to a line segment orthogonal to the scanning direction of the scanning beam (scanning light), the scanning beam a, If b and c are incident, since the light receiving surface 8a is elliptical, the incident timings of the scanning beams a, b, and c are deviated, so that the synchronization detection signal is generated as shown in FIG. The rising and falling timings of the synchronization detection signal DETP output from the circuit 11 are different from each other.

Therefore, this synchronization detection signal DETP is input to the DETP width counting circuit 25, and the width of the synchronization detection signal DETP, that is, the scanning beam is scanned with an accuracy of 1 / N by the clock CLKN as shown in FIG. 4B. The length of the light receiving surface 8a at the height thus obtained is counted.

Then, the count value of the DETP width counting circuit 25 is input to the DETP / 2 position calculating circuit 26 to reduce the count value of the DETP width counting circuit 25 to 1/2.
The calculated value is calculated, and this position is determined as the synchronization detection position.

Therefore, this synchronous detection position represents the center position of the light receiving surface 8a of the photodetector 8, that is, the position of the line segment orthogonal to the scanning direction of the scanning beam.

Accordingly, the calculation result of the DETP / 2 position calculation circuit 26 is
As shown in FIG. 4, even if the scanning beam changes like the scanning beams a, b, and c, the light receiving surface 8a of the photodetector 8 is always present.
Since it indicates the center position of the synchronization detection position, a highly accurate and stable synchronization detection position can be obtained by setting the calculation result as the synchronization detection position.

Next, the specific configuration and operation of the write control circuit including the synchronization detection position determination circuit will be described with reference to FIGS. 5 and 6.

First, referring to FIG. 5, the oscillator 41 has a write synchronization accuracy of 1 /
Image clock W according to N (here N = 4) dots
Outputs clock CLKN that is N times CLK.

The frequency divider 42 outputs the basic clock CLKD of the image clock WCLK obtained by dividing the clock CLKN into 1 / N. Shift register
The clock 43 receives the clock CLKN from the oscillator 41 as a shift clock, and is shifted in phase from the clock CLKD from the frequency divider 42 by the period of the clock CLKN.
It outputs N (N = 4) clocks CLKR with the same cycle as KD. The latch and data acquirer 44 inputs the trigger signal from the trigger generation counter 50, which will be described later, as a clock signal, selects the clock synchronized with the synchronization detection position from the clock CLKR from the shift register 43, and selects the image clock.
Output as WCLK-1.

The synchronization detection counter 45 receives the synchronization detection signal DETP from the synchronization detection signal generation circuit 11 as a load signal and divides it.
Count clock CLKD from 42 as clock input. A D-type flip-flop circuit (hereinafter referred to as "D-FF circuit") 46 uses the count value of the sync detection counter 45 as a preset input, and inverts the sync detection signal DETP from the sync detection signal generation circuit 11 with an inverter 47 for inverted synchronization. The detection signal ▲ ▼ is input to the clock terminal and its Q output is output as the signal DSYN.

The DETP width counting counter 48 inputs the sync detection signal DETP from the sync detection signal generating circuit 11 to the enable terminal, and while the sync detection signal DETP is being input, the clock from the oscillator 41 is input.
CLKN is counted (counted), and a signal obtained by inverting the signal DSYNC from the D-FF circuit 46 by the inverter 49 is input as a clear signal. The trigger generation counter 50 inputs the synchronization detection signal DETP from the synchronization detection signal generation circuit 11 as a load signal, inputs the clock CLKN from the oscillator 41 as a clock signal, and further outputs D2 to DTP of the DETP width counting counter 48.
Input the output D2 and D1 of D0 and set the sync detection signal DETP to 1/2
Dot accuracy N to be counted as (N = 4 here)
This is a ring counter in the system of, and the value loaded at the falling edge of the sync detection signal DETP is further counted by the clock CLKN,
The trigger signal TRG is output at the time when the count reaches N.

The D-FF circuit 51 inverts the output D2 of the DETP width counter 48 by the inverter 52 and inputs it to the input terminal D, and inverts the clock CLKN from the oscillator 41 by the inverter 53. Is input as a clock signal, and the inverted sync detection signal ▲
Input ▼ as a clear signal. The D-FF circuit 54 is D
A signal obtained by inverting the clock CLKN from the oscillator 41 with the inverter 53 by inputting the Q output of the FF circuit 52 to the input terminal D.
Input ▼ as a clock signal and invert sync detection signal.
Input DETP as a clear signal. AND circuit 55 is D-
Input the Q output of the FF circuit 51 and the output of the D-FF circuit 54,
The AND circuit 56 outputs the output of the AND circuit 55 and the synchronization detection signal DE.
TP is input and the output is output as the correction image clock WCLK-2. The OR circuit 57 inputs the image clock WCLK-1 from the latch and data selector 44 and the correction image clock WCLK-2 from the AND circuit 56, and outputs the output as the image clock WCLK.

The counter 61 inputs the sync detection signal DETP as a load signal and counts the image clock WCLK as a clock input, and the JK type flip-flop circuit (hereinafter referred to as "J-KEF circuit") 62 receives the image clock WCLK as a clock input. Upon receiving the count value of the counter 61, the write start synchronization signal LSYNC is output.

The counter 63 inputs the sync detection signal DETP as a load signal and counts the image clock WCLK as a clock input. The J-KFF circuit 64 receives the count value of the counter 63 with the image clock WCLK as a clock input and receives the write area signal.
Output LGATE.

The counter 65 inputs the sync detection signal DETP as a load signal to count the image clock WCLK as a clock input, and the J-KFF circuit 66 receives the count value of the counter 6 with the image clock WCLK as a clock input and receives the laser light outside the writing area. Outputs the setting signal ERASE. The laser light setting signal ERASE outside the writing area is used for unnecessary charging (PP method) of the photosensitive member outside the writing area or unnecessary discharging (N-
P system), and is a signal for preventing P
It is a method.

The D-FF circuit 67 inputs the write data WDATE to the input terminal D using the image clock WCLK as a clock input, inputs the AND circuit 68 to the write area signal WGATE and the Q output of the D-FF circuit 67, and calculates the logical product of them. And output as signal WDATE1. AND circuit 69 is a laser light setting signal ERAS outside the writing area
E and a signal obtained by inverting the write area signal LGATE by the inverter 70 are input, the logical product thereof is taken and output as the signal ERASE1. The OR circuit 71 inputs the signal DSYNC from the D-FF circuit 46, the signal WDATE1 from the AND circuit 68, and the signal ERASE1 from the AND circuit 69, and takes the logical OR to obtain the semiconductor laser 1
Output as a modulated signal VIDEO for.

Next, the write control except the generation of the image clock WCLK in this circuit will be described.

First, the modulation signal VIDEO for the semiconductor laser 1 is a signal from the D-FF circuit 46 according to the output of the synchronization detection counter 45.
When DSYNC becomes true (“1”), the semiconductor laser 1 lights up as it becomes true. In this state, the scanning beam is detected by the photodetector 8 so that the synchronization detection signal DE
When TP is true, an image clock WCLK synchronized with the sync detection position is generated as described later, and the sync detection signal DETP loads the initial value into the sync detection counter 45 to start counting again, and the The sync detection signal ▲ ▼, which is the inverted detection signal DETP, becomes false (“0”), and the signal DSYNC, which is the Q output of the D-FF circuit 46, becomes false and the modulation signal VID
EO becomes false and the semiconductor laser 1 is turned off.

In addition, each counter 61, 63, 65 is sent by the synchronization detection signal DETP.
Starts counting the image clock WCLK and, after a while after the laser light setting signal ERASE outside the writing area from the J-KFF circuit 67 becomes true, the writing start synchronizing signal LSYNC becomes true for k clocks. This write start sync signal LSYNC
Is a signal for prompting a data controller (not shown) to start writing data transfer. This write start sync signal LS
Writing area signal L with a delay of 1 clock after YNC becomes false
GATE becomes true.

The write area signal LGATE becomes true only for the write area, and the write data from the data controller (not shown) is received. For example, when the writing area is 8 "with a resolution of 1/300", the true value is obtained for 2400 image clocks WCLK. While the write area signal LGATE is true, the write data WDATE is valid, and the modulation signal VIDEO is changed by the signal WDATE1 synchronized with the image clock WCLK. That is, the scanning beam is on / off controlled by the data itself of the write data WDATA to obtain an effective image.

Further, for a while after the writing area signal LGATE becomes false, the modulation signal VIDEO is also true by the outside writing area laser light setting signal ERASE. When the laser light setting signal ERASE outside the writing area becomes false, the latch and data selector 44 is cleared, the image clock WCLK is turned off, and the modulation signal VIDEO is also false, and the semiconductor laser 1 is turned off.

After that, the output of the sync detection counter 45 becomes true and a signal
When DSYNC becomes true, the modulation signal VIDEO also becomes true. And
The semiconductor laser 1 is turned on to detect the synchronization of the next scan. After that, the writing process is performed.

Next, the determination of the synchronization detection position and the generation of the correction image clock will be described with reference to FIG. Incidentally, FIG. 6 (a) shows the case where the scanning beam is the scanning beam a shown in FIG. 4, and FIG. 6 (b) shows the case where the scanning beam is the scanning beam c shown in FIG. .

As described above, the signal DSYNC is false at the rear end (falling edge) of the synchronization detection signal DETP by the D-FF circuit 46, and the modulation signal VIDEO is the photodetector 8 light receiving surface 8a (hereinafter referred to as sensor light receiving surface 8a). It goes out at the same time as it goes out.

Further, the synchronization detection signal DETP enables the count of the DETP width counting counter 48, and the DETP width counting counter 48 outputs the clock from the oscillator 41 corresponding to the width of the synchronization detection signal DETP.
Count CLKN. Here, the outputs D2 to D0 of the DETP width counting counter 48 are shifted by 1 bit and input to the trigger generation counter 50.

This trigger generation counter 50 reduces the sync detection signal DETP to 1/2.
Then, the input value is loaded when the sync detection signal DETP becomes false. This load value is the sync detection signal DETP
Is the remainder when the length of is divided by 2N (N = 4 here), and is Mod {DETP length (MCLKN) / 2WCLK (2NCLKN)}.

That is, referring to FIG. 6, assuming that the length of the synchronization detection signal DETP is MCLKN, the rear end (falling edge) of the synchronization detection signal DETP from this half position, that is, the center position of the sensor light receiving surface 8a. Up to) is M / 2 CLKN. And this M / 2CL
The remainder when KN is further divided by the length of the image clock WCLK, 2NCLKN
Mod {MCLKN / 2NCLKN}, and the value obtained by subtracting this remainder from the length of the image clock WCLK is PCLKN. If the image clock WCLK rises after PCLKN from the falling edge of the sync detection signal DETP, the time when this rises. The length from the point Q to the center of the sensor light receiving surface 8a is divisible by WCLK (NCLKN). That is, the image clock WCLK is phase-synchronized with the center position of the sensor light receiving surface 8a with 1 / N dot precision.

Specifically, the trigger generation counter 50 uses the synchronization detection signal DE
The value loaded at the trailing edge of TP is further counted by the clock CLKN, and the trigger signal TRG is sent to the latch and data selector 44 at the time when it has counted up to N (N = 4 in this example). Then, the latch and data selector 44 uses the trigger signal TR
The clock CLKR that is phase-locked to the rising edge of G is selected and the image clock WCLK-1 is output.

By the way, when the synchronization detection signal DETP is long, the time from the central position of the sensor light receiving surface 8a to the trailing edge of the synchronization detection signal DETP may be longer than one image clock WCLK. Image clock WCLK is write start sync signal LSYNC, write area signal LG
Since it is the reference clock of the counter that generates the ATE and the laser light setting signal ERASE outside the writing area, the pulse must be a clock that can be accurately counted from the central position of the sensor light receiving surface 8a. In other words, M / 2CLKN to WCLKN (NCLKN)
Divide by, that is, only M / 2N correction clock WCLK−
2 needs to be generated. Therefore, here, the correction image clock WCLKN-2 is generated at a cycle of 2 × 4 = 8 CLKN while the synchronization detection signal DETP is true in the D-FF circuits 51 and 54.

Then, in the OR circuit 57, these image clocks WCLK−
1 and the image clock WCLK-2 are ORed and output as the image clock WCLK. Therefore, this image clock WCLK is the light receiving surface of the synchronization detection sensor (photodetector) 8.
The center position of 8a is logically detected as a synchronous detection position and is always output with a stable phase and a stable clock number.
In this embodiment, the number of clocks is always one less than the ideal image clock, which is the write start synchronizing signal LSYNC, the write area signal LGATE, the outside-write area laser light setting signal ERASE generation counter 61, There is no problem in that 63 and 65 should be corrected in advance.

As described above, in the optical scanning device of this embodiment, the synchronous detection signal is output based on the output of the optical sensor as the synchronous far field sensor when the light beam is received, and the width of the synchronous detection signal in the optical scanning direction is set to the clock. After counting by the signal, the position of 1/2 of the count value is calculated, and the calculated position is determined as the synchronization detection position, so that a highly accurate and stable synchronization detection position can be obtained. Therefore, it is possible to obtain a stable and clear printed image or to read an image regardless of the surface tilt accuracy of the rotary deflector and the positional accuracy of the optical sensor as the synchronization detection sensor.
In addition, a stable image clock can be obtained regardless of the size of the synchronization detection sensor (optical sensor).

Effect As described above, according to the present invention, it is possible to improve the accuracy of the synchronization detection position.

[Brief description of drawings]

1 and 2 are schematic configuration diagrams of an optical scanning device embodying the present invention and a circuit diagram of a synchronization detection signal generating circuit thereof, and FIGS. 3 and 4 are write control including the synchronization detection position determining circuit. A block diagram of the circuit and an explanatory diagram for explaining the same, and FIGS. 5 and 6 are a block diagram of the write control circuit including the synchronization detection position determining circuit and a timing chart for explaining the same. 1 ... Semiconductor laser, 4 ... Rotating polygon mirror 8 ... Optical sensor, 8a ... Light receiving surface 11 ... Synchronous detection signal generation circuit 25 ... DETP width counting circuit 26 ... DETP / 2 position calculation circuit

Claims (1)

(57) [Claims] 1. An optical scanning device for optically scanning a surface to be scanned by periodically deflecting a light beam using a rotary deflector, wherein an optical sensor for receiving the light beam is provided outside the area of the surface to be scanned. Means for outputting a synchronization detection signal based on the output of the optical sensor when receiving the light beam, and means for counting the width of the synchronization detection signal output by the means in the optical scanning direction by a clock signal. An optical scanning device, characterized in that it is provided with a means for calculating the position of 1/2 of the count value by the means, and the position calculated by the means is determined as the synchronization detection position.