JPH02181675A - Semiconductor testing device - Google Patents

Abstract

PURPOSE:To enhance general usefulness by providing a clock level converter and outputting a reference clock signal which is not converted in the case of testing a high speed element and outputting the signal which is converted in the case of testing a low speed element. CONSTITUTION:In the case of measuring the high speed element, a DUT board 1B with the clock level converters 3A and 3B is connected to the DUT board bonding part of a performance board 2. In the case of measuring the low speed element, a DUT board 1A without the converters 3A and 3B is connected thereto. The converter 3A in which the reference clock signal is inputted from a reference clock signal line 5A selects whether or not the level of the reference clock is converted, according to the signal of a control signal line 6. Then, a relay circuit 7 switches wiring corresponding to a signal which should be transmitted to the boards 1A and 1B. The board 1B and the board 1A are used in the case of measuring the high speed element and in the case of measuring the low speed element respectively, thereby enhancing the general usefulness.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a testing device for semiconductor devices.

[Conventional technology]

FIG. 2 is a schematic perspective view of a conventional semiconductor testing device.

In the figure, 1 is a device under test (hereinafter referred to as DtlT) board, and the center part of the D[JT board 1 has an OUT
There is one socket 8 for mounting the DOT board, and a relay circuit 7 surrounds the outer periphery of the socket 8, and the relay circuit 7 connects the socket 8 from a plurality of terminals arranged in a circle on the edge of the DOT board 1. It functions to switch the wiring. Dt
The IT board 1 is joined to a performance board 2 with an OUT board joint. A terminal to be connected to a terminal of the OUT board 1 is provided at the outer edge of the DtlT board joint portion of the performance board 2.
The number of terminals corresponding to the terminals of the OT board 1 is arranged. A plurality of cloth level converters 3 are connected to the terminals of the DtlT board junction. The clock level converter 3 includes a reference clock signal line 5 for transmitting a reference clock signal and clock level signal lines 4a, 4b 8 for transmitting a clock level signal specifying the level of the clock signal.
is connected, and the clock level converter 3 converts the reference clock signal input from the reference clock signal line into a clock signal of a voltage corresponding to the high or low level of the clock fJl lines 4a, 4b. The signal converted by the clock level converter 3 is transmitted to the DOT board 1 via the terminal at the OUT board junction, and depending on the switching operation of the relay circuit 7 in the DOT board 1. The selected clock signal output from the clock level converter 3 is applied to the DOT on the DUT board 1.

When testing different types of elements using the semiconductor testing device as described above, it is only necessary to create the Dll↑ board 1 with the relay circuit 7 and the wiring changed, so it is highly versatile as a semiconductor testing device.

However, in recent years, semiconductor testing equipment as shown in FIG. 3 has become popular for testing high-speed devices. That is, a plurality of clock level converters 3 are arranged on the DOT board 1, and the reference clock signal line 5 and clock level signal lines 4a and 4b connected to the clock level converter 3 are connected to the OUT board LL. The output lines of the clock level converter are wired to the relay circuit 7. On the other hand, the terminals arranged on the outer edge of the OUT board joint on the performance board 2 have
When the DOT board 1 is connected to the performance board 2, each reference clock signal line is connected to each reference clock signal line 5 and each clock signal line 4a, 4b on the OUT board 1 at a corresponding position. 5 and each clock level signal line 4a, 4b are connected. Therefore, the reference clock signal input from the test equipment main body (not shown) is propagated to the DOT board 1, and the reference clock signal is transmitted to the DOT board 1.
Clock level signal lines 4a, 4 connected to the clock level converter 3 in the upper clock level converter 3
When testing high-speed devices such as 0 or higher, which is converted into a clock signal with a voltage level specified by b and input to DOT, the clock signal from the clock level converter 3 to OUT is The wiring length is shortened.

[Problem to be solved by the invention]

However, in the semiconductor test equipment with the above configuration, even when measuring low-speed devices that do not require short wiring lengths, a clock level converter must be installed on the Ou↑ board, making the DOT board expensive. Another problem is that a conventional DOT board for measuring low-speed devices that is not equipped with a clock level converter cannot be used, resulting in loss of versatility.

The present invention was made to solve these problems, and provides a versatile performance board that maintains the versatility of the conventional DOT board for testing low-speed devices and can also test high-speed devices. The purpose of the present invention is to provide a semiconductor testing device having the following features.

[Means to solve the problem]

The semiconductor test device of the present invention allows the clock level converter on the performance board to select whether to convert the input reference clock signal to a clock signal of a predetermined level, or to output the input reference clock signal as it is without converting it. The clock level signal line wired on the performance board is connected to a terminal on the performance board to which the OUT board is connected.

[Effect]

In the semiconductor test device of the present invention, when testing low-speed devices, the clock level converter on the performance board converts the input reference clock signal to a clock signal of a predetermined level and outputs it, while when testing high-speed devices, The clock level converter outputs the input reference clock signal as it is without converting it, and inputs it to the clock level converter on the DOT board. Therefore, it is possible to use a DOT board for high-speed elements and a DOT board for low-speed elements with one performance board.

〔Example〕

The present invention will be described below based on drawings showing embodiments thereof.

FIG. 1 is a schematic perspective view of the semiconductor testing device of the present invention, in which a DtlT board IA, which does not have a clock level converter, is connected to the DUT board joint part of the performance board 2 when measuring low-speed elements. , when measuring high-speed devices, DOT with clock level converter
Board IB is joined. Said two ports UT board IA
, IB are to be bonded, and a plurality of terminals are arranged at equal intervals on the outer edge of the OUT board bonding portion. Each terminal is 3
The terminals form one set, and the clock level signal line 4a
, 4bl and a clock level converter 38 are arranged in plural sets. Further, a reference clock signal line 5A, the clock level signal line 4a+4b forming a set with the clock level converter 38, and a control signal VA6 are connected to the clock level converter 3A.

The clock level converter 3A receives a reference clock signal from the reference clock signal line 5A, and converts the input reference clock signal according to the signal on the control signal line 6 into the clock level signal on the clock level signal line 4a+ +4J. It has a configuration in which it is possible to select whether to convert the clock signal to a specified level clock signal or to output the input reference clock signal as it is. OUT board 1^ and 1B connected to performance board 2 as above
are the same as the OUT board 1 of the semiconductor testing device for low-speed device testing shown in FIG. 2 and the DOT board 1 of the semiconductor testing device for high-speed device testing shown in FIG. 3, respectively.

That is, the OUT board IA has one socket 8 for mounting a DOT in its center, a relay circuit 7 surrounding the outer periphery, and a plurality of terminals arranged around the outer periphery. The terminal is wired to the relay circuit 7. The relay circuit 7 switches the wiring according to the signal to be sent to the DOT.

On the other hand, the OUT board IB has one socket 8 in its center for mounting an OUT, the outer periphery of which is surrounded by a relay circuit 7, and a plurality of terminals arranged around the outer periphery. A clock level signal line 4a is provided in the middle of wiring between the relay circuit 7 and the terminal.

4b, and a plurality of clock level converters 3B connected to the reference clock signal line 5B are arranged in a circle.

By the way, wiring between a plurality of terminals and circuit relays arranged on the circumference of the OUT board IA is connected to an output line of a clock level converter 3^ arranged on the performance board 2. Reference clock signal line 5B on DOT board IB
is clock level converter 3 on performance board 2
The clock level signal &'i4a□, 4b3 on the DOT board IB is connected to the clock level signal line 4a+, 4b on the performance board 2. That is, the voltage level of the clock level signal lines 4ag, 4bg on the OUT board IB is the same as the voltage level of the clock level signal lines 4a, 4b on the performance board 2.
The voltage level is the same as that of b.

Operations when testing low-speed devices and high-speed devices in the semiconductor testing apparatus configured as described above will be described.

First, when testing low-speed devices, the DIIT board IA and performance board 2 are used in combination.

The clock level converter 3 is controlled by the control signal vA6.
A reference clock signal 5A is inputted at A, and the clock level converter 3A generates a clock signal of a voltage level specified by the clock level signal of the clock level signal line 4a1.4b1 connected to the clock level converter 3A.

When this clock signal is connected to the socket 8 according to the switching operation of the relay circuit 7 of the OUT board l^, it is input to the DOT attached to the socket 8.

Next, when testing high-speed devices, the OUT board IB and performance board 2 are used in combination.

The reference clock signal 5^ inputted to the clock level converter 3^ on the performance board 2 by the signal on the control signal line 6 is transferred to the clock level signal line 4a.

The clock signal is not converted to a clock signal of level 4b+, but is output as is and propagated to the reference clock signal line 5B of the OUT board IB. The reference clock signal propagated to the reference clock signal line 5B is input to the clock level converter 3B on the OUT board IB, where it is input to the clock level signal line 4a*I connected to the clock level converter 3B.
4bt voltage level i.e. performance board 2
Upper clock level hK issue &! 14a+.

The clock signal of 4b+ is converted into a clock signal of the specified voltage level. When the clock signal converted by the clock level converter is connected to the socket according to the switching operation of the relay circuit 7, it is inputted to the OUT connected to the socket.

〔Effect of the invention〕

As explained above, the semiconductor test device of the present invention operates such that the clock level converter arranged on the performance board inputs a reference clock signal according to the signal of the control signal line and outputs a clock signal whose level has been converted to a predetermined level. ,
It is possible to switch between outputting the input reference clock signal as it is, and furthermore, the clock level signal line wired on the performance board is connected to the terminal on the performance board to which the terminal of the OUT board should be connected. This makes it possible to use both a DtlT board for low-speed elements and a DuT board for high-speed elements with one performance board.

In other words, the performance board of the semiconductor testing device of the present invention has the advantage of being versatile enough to be used as both a DIIT board for low-speed devices and a DOT board for high-speed devices.

[Brief explanation of the drawing]

FIG. 1 is a schematic perspective view of a semiconductor testing device according to the present invention, and FIGS. 2 and 3 are schematic perspective views of a semiconductor testing device in the prior art. 1^IIB...DOT board 2...Performance board 3^, 3B...Clock level converter 4a
+ + 48z + 4b+ + 4bt'' Clock level signal lines 5A, 5B...Reference clock signal line
6... Control signal line In the drawings, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa

Claims (1)

[Claims] (1) A device under test board on which a semiconductor device to be tested is mounted, a clock level converter that outputs a clock signal for testing the semiconductor device, and a reference clock signal that is a reference for the clock signal, and a clock level converter that outputs a clock signal for testing the semiconductor device; A semiconductor testing device comprising a reference clock signal line input to a converter and a clock level signal line transmitting a clock level signal specifying a voltage level of the clock signal, and a performance board connected to the device under test board. In this case, the clock level converter is capable of outputting the input reference clock signal without level conversion, and the clock level signal line is connected to a terminal on the performance board to which a terminal of the device under test board is connected. A semiconductor test device characterized in that the device is connected to a terminal of the semiconductor test device.