JPH02180078A - Semiconductor nonvolatile memory cell and nonvolatile memory integrated circuit - Google Patents

Abstract

PURPOSE:To improve rewriting speed and memory retentivity by forming the impurity density and type of impurity of a channel region in which a threshold voltage when a semiconductor nonvolatile memory cell is completed is a depression type. CONSTITUTION:A P-type silicon substrate 11 is employed as a semiconductor region. A tunnel insulating film 14 as a first gate insulating film, a silicon nitride film 15 as a second gate insulating film, a silicon oxide film 16 as a third gate insulating film and a polycrystalline silicon film 17 as a conductive gate electrode are sequentially laminated on the surface of the silicon substrate 11. The impurity density and type of impurity of a channel region 13 are so composed that the threshold voltage of a nonvolatile memory cell becomes a depression type when a nonvolatile semiconductor element is not written. Thus, the memory retentivity of the semiconductor nonvolatile memory cell can be substantially improved, and its erasing speed can be increased.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to the configuration of an electrically rewritable semiconductor non-volatile memory element and a semiconductor non-volatile memory integrated circuit, and improves rewriting time and memory retention. .

The present invention relates to a semiconductor nonvolatile memory element with improved memory retention, and a semiconductor nonvolatile memory integrated circuit with improved memory retention.

[Prior art and its issues]

MNOS (Me Lal-N1tri
d+! -Qxide -5cm1conductOr
) type memory element and MNO8 type memory element, MON OS (Mctad-
Oxidc-Ni to 8emiconduct
There is an or) type memory device. In order to have a silicon oxide film with a barrier height sufficient to prevent injection of carriers from the gate electrode side as the gate insulating film of this MONO8 type memory element memory element, the total thickness of one gate insulating film is 10+1 m or less. It is possible to make the film thinner,
It has the feature that it can be rewritten at less than IOV. M
In the NOS type, a trap center (hereinafter referred to as a trap) in the silicon nitride film is used to capture carriers, but in the MONO
In the 'S type, a trap at the interface of a different type of insulating film is further used to capture the gearia.

information is stored.

Memory retention and rewriting speed mainly depend on the thickness of the first layer insulation film, called the tunnel insulation film, formed on the semiconductor substrate. First, increasing the thickness of the tunnel insulating film improves memory retention, but the replacement speed decreases.
If you change the direction to 11 of the tunnel insulating film to P,'7:<, the direction will be opposite to 1. Therefore, it has long-term memory retention and high speed (there is a limit to how much it can be replaced). TVf O using silicon nitride;
N OS type memory element (q!J Kaisho 62-17147/
In No. I), the memorization retention was improved, but it was not sufficient, and 1! There was no response to the switching speed. -1i, similarly, the present applicant et al. had previously proposed that the composition of the silicon nitride film, which is the second layer gate insulating film, was made to have an excess of silicon near the center of the film thickness, and 8F! MONO8 type memory element memory element 62-1.8998 with a composition close to stoichiometric value near the interface with the tunnel insulating film, which is a single-layer gate insulating film
No. 7), the eye-sumo speed was considerably improved, but it still required about 10 milliseconds to erase, and further speeding up was desired. This method also uses the control force blade 11 of the silicon nitride film. However, the response to mass production is not sufficient.

An object of the present invention is to provide a semiconductor non-volatile memory device and a non-volatile memory integrated circuit which eliminate such drawbacks, significantly improve rewriting speed, and improve memory retention.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a device as follows. (a) Source/drain regions of conductivity type opposite to the semiconductor region of the octopus are provided on the surface of the semiconductor region of the 1-19th conductivity type,
A tunnel insulating film capable of charge injection as a first gate insulating film, a silicon nitride film as a second gate insulating film, and a silicon oxide film as a third gate insulating film are sequentially formed on the surface of the channel region between the source and drain regions. CONIS (Conduct C0Nl5) consists of laminated insulating film layers and a conductive gate electrode provided on this insulating layer.
active tride-Jnsudator-8c
(microconducior) type semiconductor nonvolatile memory element, the impurity purity and impurity type of the channel region are such that the threshold f1b voltage of the nonvolatile memory element becomes depressed when no write operation has been performed on this nonvolatile semiconductor element. The present invention is a semiconductor nonvolatile memory element characterized in that it is configured to be a mold. Note that the threshold voltage when no I-t1 operation has been performed here refers to the "threshold voltage at the time of completion", so-called AsVth.

(b) In a nonvolatile memory integrated circuit that includes a semiconductor nonvolatile memory element, a detection circuit, and a reference signal generation element, the semiconductor nonvolatile element has a threshold voltage of a depression type when completed. , the detection circuit has a function of detecting information by comparing the reference signal supplied from the reference signal generating element with the output current from the semiconductor nonvolatile memory element or a signal created using this output current, The generating element is the same type as the semiconductor nonvolatile memory element, and)! The present invention is a nonvolatile memory integrated circuit characterized in that it is constructed from a semiconductor nonvolatile memory element that is not programmed.

[Actual bilU example]

The present invention will be described in detail below using the drawings.

FIG. 1 shows a cross-sectional structure of a semiconductor nonvolatile memory element of the present invention, in which a P-type silicon substrate 1 is used as a semiconductor region.
1 is used. Using ion implantation technology, n-type impurities such as phosphorus are implanted into the silicon substrate 11 at a low concentration, and a p-type or slightly n-type channel doped layer 13 with a concentration lower than that of the silicon substrate 11 is formed on the silicon substrate 110. Form nearby. Further, on the surface of the silicon substrate 11, a tunnel insulating film 14 is formed as a first gate insulating film, a silicon nitride film 15 is formed as a second gate insulating film,
A silicon oxide film 16 obtained by thermally oxidizing this silicon nitride film as a third gate insulating film, and a polycrystalline silicon film 17 as a conductive gate electrode are laminated in this order, and etched using a well-known photoetching technique to form the gate of the memory element. After forming the source/drain gamut 12, an n-type impurity such as arsenic or phosphorus is implanted using ion implantation technology. In this actual case, the second memory element
As the gate insulating film, a silicon nitride film having a thickness of about 14 nm and having a uniformly excessive silicon content was used. here,
As a method for depleting the A S Vt 11 of the memory element, a so-called channel doping method and a method of forming a channel doped layer 16 were used, and the reason thereof will be explained.

Generally, when memory elements are integrated in an array, it is necessary to add an address selection transistor to each memory element to prevent malfunction.
A field effect transistor (conductor) that shares the same semiconductor substrate as a memory element. In order for the address selection transistor to have the function of preventing malfunction, it must be an enhanced type transistor, so the semiconductor substrate concentration must be somewhat high. 11 is also often of the enhanced type.

Therefore, by performing channel doping after forming the gate of the address selection transistor, it is possible to
Only S V th can be depressed.

An example of this manufacturing method will be explained using FIG. 2.

As shown in FIG. 2 681, a silicon dioxide film 19 with a thickness of approximately 35 nm is formed by oxidizing the surface of a P-type silicon substrate 110, and a film is further formed by chemical vapor deposition (hereinafter referred to as CVD method). After forming the polysilicon film 18 with a thickness of about 50 nm, the polysilicon film 18 is etched using a well-known photoetching technique to form the gate of an address selection transistor, and then the polysilicon film 18 is etched using a well-known ion implantation technique. Using 18 as a mask, an n-type impurity such as phosphorus is applied to the silicon substrate 110.
An implanted channel doped layer 16 is formed near the surface, and then the silicon dioxide film 19 is etched using the polysilicon film 18 as a mask.

Next, as shown in Fig. 2 (bl), the film thickness is 2,
A tunnel insulating film 14 with a thickness of about 1.11 m is formed, and a silicon nitride film 15 with a thickness of about i 4 nm is further formed by the CVD method, and the surface of the silicon nitride film 15 is further subjected to steam oxidation treatment to a film thickness of 5 nm. Silicon oxide film of about 1
6 was formed, and further a film thickness of 450 nm was formed by CVD method.
A polycrystalline silicon film 17 of about 100 mL is formed. Note that due to the high temperature during the steam oxidation treatment, the channel doped layer 1
6 diffuses into the silicon substrate 11.

Next, as shown in FIG.
, the silicon nitride film 15 and the tunnel insulating film 14 are sequentially etched to form the gate of the memory element, and then n-type impurities such as arsenic or phosphorus are added to the polycrystalline silicon film 17 and the polysilicon film 18 using well-known ion implantation techniques.
is implanted into the silicon substrate 11 using the mask as a mask, and then heat-treated in, for example, a nitrogen atmosphere to form a highly concentrated source/drain region 12. At this time, the channel doped layer 16 other than under the gate of the memory element is converted into a source/drain region by the high concentration impurity layer.

Next, as shown in FIG. 2 (1), 20 patterns of interlayer insulation are formed, contact windows 22 are formed by photoetching, and wiring metal 21 such as aluminum is formed. At this time, the source/drain region of the source/drain region 12 sandwiched between the address selection transistor and the memory element does not need to be wired, and may be electrically floating.

In this way, between the address selection transistor and the memory element fabricated in the same silicon substrate 11, the effective impurity concentration of the semiconductor region under the gate of the memory element can be compensated for by channel doping to lower the concentration, or By using a memory element, only the ASVth of the memory element can be depressed. Note that the impurity surface concentration of the silicon substrate 11 is V th of the address selection transistor.
It is not even 5 that is configured so that it is enhanced.

In the above embodiments, the semiconductor region is the silicon substrate itself, but the semiconductor region may be a well formed on the surface of the silicon substrate of the opposite conductivity type, or an island-like semiconductor region formed on an insulating substrate. There is nothing wrong with that. Of course, even if channel doping is not performed, the A
It is possible to deplete only S V th . For example, even if the semiconductor substrate concentration causes a depression in AsVtb of a memory element, the gate oxide film thickness of the address selection MOS transistor can be made thick enough to enhance ■ t h . Address selection MOS can be created by using the work function difference between the gate and the substrate by selecting the gate removal material.
Possible methods include enhancing the transistor's V t 11 and depressing the memory element's AsVth (for example, using a P-type silicon substrate, the memory element using an n-type silicon gate, and the address selection transistor using an n-type silicon gate). However, it is not practical because it cannot cope with miniaturization of element dimensions and the process becomes complicated. The above is the reason for performing channel doping in the present invention.

Next, with reference to FIG. 3, it will be explained how memory retention is improved by depressing the memory element. FIG. 3 is a diagram comparing the memory retention properties of the memory element having the structure according to the present invention shown in FIG. 1 and a conventional memory element without channel doping. Here, in the conventional memory element, the second layer gate insulating film has a film thickness of 14. n m
Using silicon nitride removal with a uniformly silicon-excessive composition, the first layer gate insulating film has a film thickness of 2.5 mm. 1 nm tunnel insulating film, and the third layer gate insulating film has a second layer with a film thickness of about 5 nm.
It refers to a memory element that uses a silicon oxide film formed by thermally oxidizing a silicon nitride film, which is a layered gate insulating film.
. The ASVtll of the memory device of the present invention is approximately −1,OV,
The ASVth of the conventional memory element is approximately 0. In IV, both the present invention 61 and the conventional example 32 write Vt11 and erase Vth.
Memory retention was investigated by keeping the initial values of . Note that the broken line in FIG. 3 is an extrapolation line V t
In the present invention, vth at the intersection of the h attenuation curves is approximately -0,
5) In the conventional example, it is about 0.2 V, which is almost the same as the A S V th relationship of the memory element. Whether the stored information is 1 (normally on) or 0 (normally off)
The decision as to whether the memory element's
tll is slightly more negative than zero■, -0,5
It is often around V. The absolute lifetime for maintaining the value is the time until the Vth decay curve intersects, but the substantial lifetime is the time until the Vth decay curve intersects the sense level. In Figure 3, yth on the erasing side of the present invention
The time it takes for the decay curve to intersect with the sense level is considerably longer than in the conventional example, and the absolute memory retention life and the actual memory retention life are approximately equal. That is, by depressing the AsVth of the memory element, it is possible to substantially improve memory retention.

FIG. 4 shows hysteresis curves of a memory device according to the present invention and a conventional memory device without channel doping. Although there is not much difference on the usage side, the hysteresis curve of the present invention becomes larger on the erasure side.

This is because the degree to which the charge induced on the substrate surface under the memory gate by the charge injected into the memory element affects the effective substrate concentration is large when the original substrate concentration is thin (especially noticeable on the erase side). As can be seen from FIG. 4, in the memory element according to the present invention shown by the solid line 41, the change in V th during erasing is large, so the amount of change in t1 per unit time during the erasing operation becomes large. Therefore, compared to the conventional memory element shown by the broken line 42, less time is required to reach the same V th after erasing.This means an increase in the erasing speed.For example, the erasing voltage In the case of −9 V, the erasing time of the memory element of the present invention was approximately 5 m5 ec, compared to the erasing time of 10 to 5 Q m5 ec for the conventional memory element, making it possible to significantly increase the erasing speed.

Here, the erasing time is defined as the time required to reduce the threshold voltage of the memory element from a sufficiently written state to below the sense level.

In the above embodiments, an n-channel type was described, but to make a p-channel type, an n-type silicon substrate may be used, and a p-type impurity such as boron may be used as the impurity for doping the channel.

Next, a practical example of the case where the memory element having A S V th of depression according to the present invention is applied to a nonvolatile memory integrated circuit will be described with reference to FIGS. 5 and 6.

FIG. 5 shows a memory matrix consisting of memory cells 54, 55, 56, 57, a detection circuit 46, and a reference signal generating element 4.
8 is a schematic diagram of a nonvolatile memory integrated circuit including
Memory transistor 5 forming memory cell 57
6 is a diagram illustrating a system for detecting whether the information held by 6 is 1 or 0. In FIG. 5, the element marked M is a memory element in which AsVih is depletion according to the present invention, and the element marked n is an n-channel type M, OS transistor. The reference signal generating element 48 is a memory element according to the present invention in which the threshold value is always maintained at AsVth without being fully loaded.
．． 60 is a memory element according to the present invention in which writing is freely performed. In FIG. 5, a high level potential is applied to the gate of the Y-direction address selection transistor 51, a high level potential is applied to the selected word line 45, a low level potential is applied to the unselected word line 46, and a low level potential is applied to the blocking line 62. Level potential, write line 44
A low level potential is applied to the gate of the reference signal generating element 48, and a high level potential is applied to the gate of the load transistor 49. Here, load transistor 4
9 is equivalent to combining the Y-direction address selection transistor 51 and the X-direction selection transistor 50. Therefore A
The magnitude relationship between the current levels at points and points B or the potential levels determined by these current levels is determined by the difference in threshold voltage between the storage transistor 56 and the reference signal generating element 48, but the threshold voltage of the reference signal generating element 48 is Since the depletion value is always constant, points A and B are determined depending on whether the threshold value of the storage transistor 5B is enhanced or depleted from the threshold value of the reference signal generation element 48.
The current level at a point or the magnitude relationship of the potential level determined by this current level is determined. Then, the detection circuit 46 determines the magnitude relationship between the current levels at points A and B or the potential levels determined by these current levels, and if necessary, amplifies the determination result and generates an output 52, thereby increasing the memory transistor 56. It is possible to read the information held by.

J'' of memory transistor 56, one piece of information is correct f
i&W cannot be extracted (this is because the charge accumulated in the storage transistor 56 gradually disappears over time, and the threshold voltage of the storage transistor 56 becomes equal to the threshold voltage of the reference signal generation element 48). , that is, when it is equal to ASVth and multiplied by 1.The time it takes for the threshold voltage of the memory transistor 56 to become equal to ASV th due to a change over time is the biting side Vt11 and the erasing side Vth.
is the intersection of the decay curves of , that is, the absolute memory retention lifetime. Therefore, by using the memory element in which A s V th is depletion according to the present invention as the reference signal generating element and the storage transistor, the detection circuit determines the current level or A nonvolatile memory integrated circuit using a system that detects the potential level determined by this current level can make the memory retention time equal to the absolute memory retention life of the memory transistor, and has the maximum memory retention time. Can be done. Further, in the information detection system as shown in FIG.
Since it is used for comparison, it has the characteristic that it is not affected by variations during manufacturing or temperature changes.

FIG. 6 shows a memory device according to the present invention shown in FIG. 5, in which AsVt, I] is depletion, is used as a storage transistor and a reference signal generation element, and a reference signal supplied from the reference signal generation element and a storage transistor are used. Implementation when a current mirror differential amplifier is used as the detection circuit in a non-volatile memory integrated circuit that includes a detection circuit that has the function of detecting information by comparing the output current or a signal generated using the output current This is an example. Note that the elements marked P in FIG. 6 are P-channel type MOS transistors. The nonvolatile memory integrated circuit shown in FIG.
Information is detected and output is generated by comparing the potentials of points. In FIG. 6, a transistor 50 for selecting an address in the X direction, a transistor 51 for selecting an address in the X direction.
, when a high-level potential is applied to the gate of the load transistor 49 to create a reverse state, the threshold voltage of the reference signal generating element 48 is always A S V th , so 1
) point is always constant. On the other hand, the potential at point C fluctuates depending on whether the threshold voltage of the storage transistor 56 is enrichment or depression, and the threshold voltage of the reference signal generating element 48, that is, ΔSV t
If the threshold voltage of the storage transistor 56 is in depression than h, the potential at point C is lower than the potential at point D (and the threshold voltage of the storage transistor 56 is lower than A).
When the potential at point C is higher than S Vt h, the potential at point C becomes more sieved than the potential at point D. The detection circuit 61 amplifies the difference in potential between points C and D. The output value is high level when the potential at point C is lower than point D, and the output value is high level when the potential at point C is lower than point D.
When the potential is higher than the point, it outputs a low level.

The memory retention time of the non-volatile memory integrated circuit shown in FIG. Needless to say, it is not affected by variations in time or temperature changes during use.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to substantially improve the memory retention of a semiconductor nonvolatile memory element compared to the conventional one, and it is also possible to increase the erasing speed. That is, it is possible to realize high speed and long life of a semiconductor nonvolatile memory device. Furthermore, it is possible to provide a nonvolatile memory integrated circuit whose memory retention time is equal to the absolute memory retention life of the memory element and which is not affected by variations in characteristics during manufacturing or temperature changes during use.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the structure of the semiconductor nonvolatile memory device of the present invention, and FIGS. 2(a) to (d) show the semiconductor nonvolatile memory device of the present invention fabricated in the same substrate as the address selection transistor. 3 is a graph comparing the memory retention of the structure of the semiconductor nonvolatile memory device according to the present invention and a conventional structure without channel doping. FIG. A graph comparing hysteresis curves of the invention and conventional semiconductor nonvolatile memory devices,
FIG. 5 is a circuit diagram showing a nonvolatile memory integrated circuit of the present invention;
FIG. 6 is a circuit diagram showing a nonvolatile memory integrated circuit according to the present invention in which a current mirror type differential amplifier is used in the detection circuit. 12... Source/drain region, 16...
... Channel doped layer, 14 ... Tunnel insulating film, 15 ... Silicon nitride film, 16 ... Silicon oxide film, 17 ... Polycrystalline Silicon film, 48... Reference signal generating element, 49... Load transistor, 50...
・X-direction address selection transistor, 51...Y
Direction address selection transistor, 61...detection circuit.

Claims (2)

[Claims] (1) Charge can be injected as a first gate insulating film onto a source/drain region of a conductivity type opposite to that of the semiconductor region provided in a semiconductor region of a first conductivity type, and onto the surface of a channel region between the source and drain regions. The tunnel insulating film is composed of an insulating film layer in which a silicon nitride film is sequentially laminated as a second gate insulating film and a silicon oxide film as a third gate insulating film, and a conductive gate electrode provided on the insulating film layer. A semiconductor non-volatile memory element, wherein the impurity concentration and type of impurity in the channel region are configured such that the threshold voltage of the semiconductor non-volatile memory element when completed is a depression type. Non-volatile memory element. (2) In a nonvolatile memory integrated circuit including at least a semiconductor nonvolatile memory element, a detection circuit, and a reference signal generation element, the semiconductor nonvolatile memory element has a depression type threshold voltage when completed, and the detection circuit has a function of detecting information by comparing a reference signal supplied from the reference signal generating element with an output current from the nonvolatile storage element or a signal created using the output current, and the reference signal generating element A non-volatile memory integrated circuit comprising a non-volatile memory element of the same type as the non-volatile memory element and to which writing is not performed.