JPH02180071A - Solid image sensor element - Google Patents

Abstract

PURPOSE:To enable enhancing the sensitivity of an image sensor by extending a first-conductivity-type island region formed around a source region to drain regions. CONSTITUTION:An n-type well region 2 as a semiconductor layer is formed on a p-type silicon substrate 1 having a first-conductivity-type picture element. An n<+> type source region 4 and n<+> type drain regions 5 of the same conductivity type are formed in the surface of said n-type well region 2. A p-type well region 3, a first-conductivity-type island region, is formed around the source region 4 in the surface of the substrate and extended to the drain regions 5. Therefore, depth required for obtaining spectral sensitivity and depth of the island region from the substrate can be set independently by potential formed by the island region. Thereby the spectral sensitivity can be enhanced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an internal amplification type solid-state image sensor in which a source region and a drain region are formed on the surface of a semiconductor layer, and optical signal charges are amplified for each pixel. Regarding.

[Summary of the invention]

The present invention provides a pixel comprising an element in which a semiconductor layer of a second conductivity type is formed on a semiconductor substrate of a first conductivity type, a source/drain region is formed on the surface of the semiconductor layer, and a source/drain current flows parallel to the surface of the semiconductor layer. In a solid-state imaging device in which the first conductivity type is arranged in a matrix, the first conductivity type island region surrounds the source region and extends to the drain region.
This is intended to achieve higher sensitivity in imaging.

[Conventional technology]

In response to the demand for higher resolution of solid-state imaging devices, research and development of internally amplified solid-state imaging devices that amplify optical signal charges for each pixel have been progressing.

Various types of imaging device structures are known as the main types of internally amplified solid-state imaging devices, such as electrostatic induction I/Lunlister (SIT), amplified M1S imager (AMI), and charge modulation device (CMD). (For example, regarding AMI, see "Journal of the Television Society," pp. 1075-10.
Page 82, Vol 41. No. 11. 1987, CM
Regarding D, see Jezume, pages 1047 to 1053, same issue. ).

Regarding lateral electrostatic induction transistors, Japanese Patent Application Laid-open No. 6
There is a prior art described in Japanese Patent No. 1-136388.

[Problem to be solved by the invention]

However, the various devices described above each have the following drawbacks.

First, in the SIT type, the element characteristics are sensitive to the structure, and the characteristics tend to fluctuate. Furthermore, the AMI type requires three transistors in a unit cell, making it difficult to increase sensitivity and transistor gain.

In addition, in the CMD type, the thickness of the n'' evixial layer reaches 8 μm, making it deep.

Therefore, it is easily susceptible to short channel effects, and at the same time, the current capacity is also reduced. Furthermore, in the CMD type, holes are accumulated at a depth very close to the gate, so their mirror charges (electrons) are collected at the gate. Therefore, the contribution of the photohole to the conductance becomes smaller, and the current amplification factor decreases. Furthermore, regarding the CMD type photosensitivity distribution, only the gate electrode and its vicinity act as a light receiving region, and sufficient sensitivity cannot be obtained.

Further, solid-state imaging devices are required to be miniaturized and highly integrated, but in the CMD type, it is necessary to form a channel at a depth that captures photoholes, and proportional reduction is not easy.

SUMMARY OF THE INVENTION In view of the above-mentioned technical problems, the present invention aims to provide a solid-state image sensor that has excellent photosensitivity and electrical characteristics and is also capable of proportional reduction.

[Means to solve the problem]

In order to achieve the above object, the solid-state image sensor of the present invention has the following features:
A source region and a drain region of a second conductivity type are provided on the surface of a semiconductor layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type, and a gate H1 region is provided between the source region and the train region. , in a solid-state imaging device in which pixels are arranged in a matrix in which a source-drain current flows between the source region and the drain region in parallel to the surface of the semiconductor layer, the pixels are formed so as to surround the source region; The first conductivity type island region extends to the drain region.

[Effect]

In the solid-state imaging device of the present invention, the source region of the second conductivity type formed on the surface of the semiconductor layer of the second conductivity type is surrounded by the island region of the first conductivity type, and the island region is also formed on the surface. The second conductivity type drain region is also extended to the second conductivity type drain region. Here, if the first conductivity type is p type and the second conductivity type is n type, the potential distribution will have an extreme value in the p type island region, and the Holes are accumulated at 4°, and the region having spectral sensitivity extends to the depth of the minimum potential of the n-type semiconductor layer, resulting in improved sensitivity. The depth at which this photoball can be captured is the depth of the island region 5 semiconductor layer and the semiconductor substrate? ! M
The depth at which photopoles are accumulated can be set independently of the depth depending on the temperature, etc., and by making the depth shallower than the CMD type described above, it is possible to suppress short channel effects and increase current capacity. In this way, since the depth at which photosensitivity occurs and the depth at which photoholes are accumulated can be set independently, their proportional reduction can be easily performed.In addition, p-type islands can be formed in areas other than the gate and its vicinity. The area has spectral sensitivity, and its aperture ratio is greatly improved.Also, depending on the depth of the p-type island region, photoholes are accumulated near the surface, and the mirror charge is transferred to the surface side. It is easy to collect enough information, which is advantageous for non-destructive reading.

Here, the function of the solid-state image sensor of the present invention will be compared with that of a CMD-type solid-state image sensor, as shown in FIGS.
This will be explained in more detail with reference to FIG.

FIG. 8 shows a solid-state image sensor (hereinafter referred to as FWA) according to the present invention.
It is called the Floating Well Amp type. ) is a model of an n-type silicon substrate 100.
An n-type well region 101 is formed thereon, and surrounded by this n-type well region 101, an n-type well region 102 as an island region is formed. A source region 103 is formed on the substrate surface surrounded by an n-type well region 102, and a drain region 104 is formed on the substrate surface where the n-type well region 102 extends. A gate electrode 1 is formed on the substrate surface between the source region 103 and the drain region 104.
05 is formed.

FIG. 10 shows the potential distribution below the gate of the FWA type model shown in FIG.
2 is a curve at the time of reading when the level of the gate electrode is set to a high level. As shown by the curve P1, if the level of the gate electrode is low, photoholes are accumulated in the n-type well region 102 in a region shallower than the minimum point u1 of the n-type well region 101. In addition, if the level of the gate electrode is high, the balls will be concentrated at the maximum value u2, and depending on the amount of charge of the accumulated holes, a back gate (body effect) effect will be added, and the surface Reading is performed by modulating the charge.

FIG. 9 shows a model of a CMD type solid-state image sensor as a conventional example to be compared.
is formed. On the surface of the thick n-type epitaxial layer 111 are source regions 112 . each made of an n-type impurity region. A Ruin region 113 is formed, and a gate electrode 114 is formed between and above the spaced apart source/drain regions.

FIG. 11 shows the potential distribution in the lower part of Day 1 of the device shown in FIG. 9, in which curve P3 is when the gate voltage is at a low level (during accumulation), and curve P4 is when the gate voltage is at a high level. In this device, the n-type epitaxial layer 111 is formed to be thick and the bulk channel is also deep, which deteriorates the saturation current amount, photosensitivity characteristics, etc.

Now, if we give parameters to each part corresponding to each potential distribution in Figures 10 and 11 and consider it,
First, in the FWA type solid-state imaging device of the present invention, the distance from the gate electrode to the substrate surface where the electron channel is formed is Wl, the distance from the surface channel to the depth where holes are accumulated is Wz, and the distance from the gate electrode to the substrate surface where the electron channel is formed is Wz. The distance of the depletion layer is W
3, and the corresponding capacities are C+, C2, and C2, respectively.
CS, the gate voltage is Vg, the electron charge is QI, and the potential is Φ1. Similarly, let the hole charge be Q2 and its potential be Φ2.

Then, since the amount of charge is - capacitance x potential difference, considering its change, δQ+=C+(δVg-δΦ1)→-C2(δΦ2-δ
Φ1)-c, δVg (CI+C2) δΦ1+C2δ
Φ2...■δQ 2 = C2 (δΦ1-δΦ2)C
3δΦ2−CzδΦ+ (C2+ C3)δΦ2
・・・■ Simultaneous equations are obtained, and from equations ■ and ■, δ
When Φ2 is eliminated, δ and −C3δVg (CI → −C2C5/C2+
C5) δ ΦC, / (cz+Cs) δQ2...
■ is obtained.

From this 0th equation, = channel capacitance; -δQ1/δΦ6, which is important as an element characteristic. Charge sensitivity; -δQ, /δQ2. Gate sensitivity: When calculating δΦ and /δ■g, respectively, δQ−, /δΦ+ −(CI +C2C5/C2+C9
) CCW +-' + (Wz + WS)-' ・・・
■δQ, /δQz = cz/(cz+cs)o:ws/
(W2 +w,) ・=■δΦ, /δv g =c+
/ (c+ +czcs/cz+cs)cc(Wz+1
4s)/(W++Wz+IQs) -■(',' c
, −εS I/ W + + C2−εs I/”
2 + Cs-ε5□/4S).

On the other hand, similar parameters are given to the CMD device shown in Figs. 9 and 11, and the distance from the electrode to the substrate surface where holes are accumulated is wol, and the distance from the surface channel to the depth of the electron channel is W distance. 2. The distance of the depletion layer in silicon is Wss, the corresponding capacitance is C8, Co2C55, the gate voltage is Vg, and the hole charge is Q. Let the potential be I as Φ. ,
Similarly, the electron charge is Q. 2, the potential is Φ
. Set it to 2. Then, similar simultaneous equations are obtained, δQo+=Co+(δVg−δΦ01)+C02(δΦ
. 2-δΦ01)-C0, δVg-(Col+cO2
) δ ΦOI+C82δ Φ02 ”'■δQo2
=Coz(δΦ., −δΦ02) C3SδΦ. 2-
CO2δΦo+ (COm +Css)δΦ02
”'■ From these 0.0 equations, δQoz-(Co+Coz/(Co++Coz) +C
55) δΦ. 2+C02”δVg/(Co++Coz)
-Co2δΦo+/(Co++Coz)・=■This 0th
From the formula, the two-channel capacitance, which is also important as an element characteristic; -δQ, 2/δΦ. 2. Charge sensitivity; -δQo2/δQ01. Gate sensitivity; δΦ. Calculating each for 2/δVg, δQ, 2/δΦ02−(Co+Co2/(Co2C55
) 10Cs5)oc(WOI 1-WO2)-' +W
ss-”...@l) δQ02/δQo+=Co2/(C
o++Coz)OCWOI/ (Wol + WSS)
−・■δΦ. 2/δV g =Coz”/((Co
2C55)Css+Co+Coz)”(Wo++Wss
)/Woz(Wol+Woz+wss)-@(゛・
'C1=εsi/Wo+・C02:εSi/WO21C
9S”ε, i/deception S3).

Here, as the parameters configuring each element, the formula ■~
■W+ = O, lum, Wz = 10m, Ws-
Substitute each value of 5 μm and enter W in the formula [phase]~@. , -0°1 μm, WO2=2 μm, and Wss-I Qμm to calculate the channel capacitance (Cch).

Charge sensitivity (δQch/δQpho
to) and gate sensitivity (δΦch/δV
Let's compare each value in g). Furthermore, w, , wo
, (The D value is a value after correcting the dielectric constant, and for w2.w of the solid-state image sensor of the present invention, a value slightly deviated from the optimum value is substituted. The results are shown in the table.

In addition, the sensitivity of the element becomes even higher.

(Numbers are relative values) From this comparison, the FWA type of the solid-state image sensor of the present invention has a higher saturation current (Cch) than the CMD type.
16 in terms of light sensitivity (δQch/δmouth pho to)
It can be seen that the characteristics are improved by about 17 times, and the gate selectivity (δΦch/δνg) is also improved. Moreover, the characteristics can be further improved by optimizing the parameters of the FWA type.

Furthermore, as shown in FIG. 8, in the solid-state imaging device of the present invention, the p-type well region 102 extends below the source region 103 and drain region 104, and the well region 102 is filled with optical signal charges. is accumulated, so that even when light is incident on the source region 103 or the drain region 104, photosensitivity can be obtained. This will be explained with reference to the drawings.

First, the basic configuration will be explained with reference to Parts 1 to 3. As shown in Fig. 1, the solid-state image sensor of this embodiment has pixels of the first conductivity type. An n-type well region 2 as a semiconductor layer is formed on a silicon substrate 1 of the same type. On the surface of this n-type well region 2,
A source region 4 of the n1 type and a drain region 5 of the n4 type of the same conductivity type are formed, and between the source region 4 and the drain region 5, a gate electrode 7 is arranged with an insulating film 6 interposed therebetween. A region is provided. A p-type well region 3, which is an island region of the first conductivity type, is formed on the substrate surface so as to surround the source region 4, and this p-type well region 3 extends to the drain region 5. Further, in the source region 4, an aluminum wiring layer 8 is formed on the substrate surface by opening the insulating film 6. Here, the depth of each region is the depth of the center of its concentration distribution, and the n-type well region 2 is, for example, 2.
For example, the p-type well region 3 has a thickness of about 1.0 μm.
It is about μm, and the source region 4. drain region 5
is, for example, about 0.5 μm. In addition, silicon substrate 1
The concentration of is on the order of 3 x 10''cm-3.

Next, the potential distribution is as shown in FIGS. 2 and 3. FIG. 2 shows the potential distribution along the cross section taken along the line H--H in FIG. 1, and shows the solid line P. 1 indicates the potential when the gate voltage is at a low level. At this time,
The solid line P at is the minimum point S at the depth of the n-type well region 2 .

In a region shallower than that depth, photoholes are accumulated along the slope of the potential. In FIG. 2, broken line P. 2 shows the potential when the gate voltage is at a high level, and if there is accumulation of optical signal charges when the gate voltage is at a high level, -dotted chain line P. The potential distribution becomes as shown in 3. When the gate voltage is at a high level, a potential maximum point S is formed at the depth of the p-type well region 3, and a potential maximum point S is formed on the surface according to the amount of charge Qh of the foI ball accumulated at this maximum point. A channel is formed. That is, the effect of the back gate (PODI EFFEC1~) is added according to the hole charge ff1Qh, and the number of electrons in the surface channel is modulated.

The source-train current changes depending on the amount of charge Qe on the surface, and reading according to the signal charge becomes possible.

FIG. 3 shows the potential distribution in a cross section along the line ■-■ in FIG. 1, and is a curve P. 4 has p-type well regions 3 and n
A minimum value S2 is provided by the p-type well region 2 and the p-type silicon substrate. As a result, photoholes will be accumulated in a region shallower than this minimum value s2, and these accumulated photoholes will be further gathered toward the lower side of the gate where the potential is lower. Therefore,
In the solid-state imaging device of this embodiment, even the N region below the drain region 5 and source region 4 where the gate electrode 7 is not formed has photosensitivity, and the sensitivity is improved. .

In a device like No. 1, the region having spectral sensitivity is n
The depth is up to the extreme value S o + S 2 of the well region 2 of the mold, and the sensitivity is improved.

The depth of the p-type well region 3. The n-type well region Mi2, the depth of the silicon substrate 1, the concentration, etc. can be set independently of the depth (s) at which photoholes are accumulated, and its proportional reduction can be easily performed.
By reducing the depth at which the channel is formed,
It becomes possible to suppress short channel effects and increase current capacity. Furthermore, parts other than the gate and its vicinity also have photosensitivity, and the aperture ratio is significantly improved.

It is also advantageous for non-destructive reading.

Next, an example of the planar layout of the solid-state image sensor of this example will be described with reference to FIG. 4. In the solid-state imaging device of this embodiment, since it is necessary to reset the signal charges accumulated particularly in the p-type well region, a reset means is added.

As shown in FIG. 4, the planar layout is a p-type well region 3 formed in a square shape, indicated by a dashed line in the figure.
A gate electrode 7 is routed from the periphery of the p-type well region 3 to the inner part thereof. This gate electrode 7
is formed surrounding a substantially square source region 4 according to the shape of the well region 3, and one side 7 of the source region 4 is shaped like a square.
In a, it is extended in the horizontal direction in the figure to connect to the scanning circuit. This approximately square gate electrode 7
An aluminum interconnection layer 8, which will become a vertical signal line, is connected to the source region 4 inside the substrate via a contact hole 9.

By the way, as mentioned above, in the solid-state image sensor of this example,
Photoholes are accumulated in the p-type well region 3,
The number of electrons in the surface channel is modulated. Therefore, when resetting a signal, it is necessary to apply a reset 1- voltage to the p-type well region 3. Therefore, in the solid-state imaging device of this embodiment, the reset means 10 is formed to be connected to the p-type well region 3. This reset means 10 also functions to control overflow and is connected to the set gate electrode 11.
Reset and overflow are controlled by the potential of .

Specifically, this reset means 10 is
A configuration as shown in the figure can be adopted. In addition, the fifth
Figures a and b correspond to the cross section taken along the line V-V in Figure 4.

FIG. 5a shows an example of the reset means 10, which sweeps out unnecessary charges to the p-type silicon substrate 1. That is, the source/drain regions 12a of the reset transistor are formed on the substrate surface on both end sides of the reset gate electrode 11,
12b is formed, one of the source/drain regions 1
2a is connected to the p-type well region 3. The other source/drain region 12b is an n-type well 11M2.
．． 2 to the p-type silicon substrate 1 via a region 13. By lowering the potential of the reset gate electrode 11, a channel is formed between the source/drain regions 12a and 12b, and the charges are further swept out to the p-type silicon substrate 1 via the region 13.

With such a structure, overflow control is possible when receiving light. Also, when resetting,
It is also possible to reset the pixel charges accumulated in the p-type well region 3.

FIG. 5 shows another example of the reset means 10,
This is an example in which unnecessary charges are swept out to the electrode 15. Its structure is such that the source/drain regions 14a of the reset transistor are provided on the substrate surface on both end sides of the reset transistor 1 and the gate electrode 11.
, 14b are formed, and one of the source/drain regions 14a is connected to the p-type well region 3. Further, a contact pole is formed on the other source/drain region 14b, and the electrode 15 is connected thereto.

FIG. 6 is a diagram showing the potential function of the reset means shown in FIG.
Level 2 is the level when no photoballs are accumulated, and level Φ is the level when the photoballs are full.

By controlling the level of Φ0FCG, unnecessary charges (holes) are swept out to the source/drain N region 14b and the electrode 15, which function as an overflow drain. Further, at the time of reset, the level of the reset gate electrode 11 changes, the potential of Φ0FCG changes, and the level of the p-type well region 3 is returned to the level Φ2.

Next, an example of the circuit configuration of the solid-state image sensor of this example will be briefly described with reference to FIG.

The circuit configuration is such that each pixel has an amplifying transistor 22 and a photodiode 21 arranged in series with a capacitor 24.
is arranged on the channel side of the photodiode 21, and the electric charge from the photodiode 21 modulates the current of the amplification transistor 22. The reset transistor 23 is connected to one end of the photodiode 21 (p-type well region 3), and performs signal charge accumulation 1. Each such pixel is
Vertical gate lines ■G, , vG, . . . 1. ..., the signal from the amplification transistor 22 is transferred to the vertical signal line H7.
, 111□, ... appear. The reset means includes vertical reset lines VRゎ, VR4,
1, . . . and the reset transistor 23
A reset operation is performed by changing the gate voltage of . It is also possible to control overflow at the time of light reception using this reset line. Each vertical signal line H-, H-+,...
The signals appearing in . . 35.

(Effects of the Invention) As described above, the solid-state imaging device of the present invention includes an island region of the first conductivity type extending from the source region of the second conductivity type to the drain region formed on the surface of the semiconductor layer of the second conductivity type. is formed, and the potential formed by this island region allows the depth of the island region from the substrate to be set independently of the depth required to obtain spectral sensitivity.Therefore, its proportional reduction is easy. It is possible to increase the spectral sensitivity. Also, by reducing the depth at which the channel is formed, it is possible to suppress the short channel effect and increase the current capacity. By providing the island region, parts other than the gate and its vicinity have photosensitivity, and the aperture ratio is significantly improved.

It is also advantageous for non-destructive reading.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of an example of the solid-state image sensor of the present invention, FIG. 2 is a potential distribution diagram along the cross section taken along the line ■-■ in FIG. 1, and FIG. 3 is a diagram showing the potential distribution along the line ■-■ in FIG. 4 is a plan view showing an example of the planar layout of the above element; FIG. 5a is a sectional view showing an example of the reset means; FIG. FIG. 6 is an explanatory diagram for explaining the potential that goes into the beam means, FIG. 7 is a circuit diagram showing an example of the circuit configuration of the solid-state image sensor of the present invention, and FIG. FIG. 9 is a sectional view showing the structure of a model of the solid-state image sensor of the invention, FIG. 9 is a sectional view showing the structure of a model of a conventional solid-state image sensor, FIG. 1] Fig.+31 This is a potential distribution diagram just below the gate of the device shown in Fig. 9. 1... N-type silicon substrate 2... N-type well region 3... N-type well region 4... Source region 5... Train region 6... Insulating film 7... Gate To Electrode Patent Applicant: Akira Koike (and 2 others), Patent Attorney for Sony Corporation Figure 5b Figure 8 P3 Figure 11 Figure 9 Figure 10

Claims (1)

[Claims] A source region and a drain region of a second conductivity type are provided on the surface of a semiconductor layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type, and a source region and a drain region of a second conductivity type are provided between the source region and the drain region. In a solid-state imaging device in which pixels are arranged in a matrix, the pixels are arranged in a matrix, and each element has a gate region, and a source-drain current flows parallel to the surface of the semiconductor layer between the source region and the drain region. 1. A solid-state image sensing device, characterized in that an island region of a first conductivity type formed to surround the drain region extends to the drain region.