JP2692218B2 - Solid-state imaging device - Google Patents

Description

The present invention relates to an internal amplification type solid-state imaging device in which a source region and a drain region are formed on a surface of a semiconductor layer and an optical signal charge is amplified for each pixel. Regarding

[Summary of the Invention]

The present invention is a pixel including an element in which a semiconductor layer of a second conductivity type is formed on a semiconductor substrate of a first conductivity type, a source / drain region is formed on the surface thereof, and a source / drain current flowing in parallel to the surface flows. In a solid-state image sensor in which the elements are arranged in a matrix, the first conductivity type island-shaped region surrounds the source region and extends to the drain region, thereby realizing high sensitivity of imaging.

[Conventional technology]

Research on an internal amplification type solid-state image sensor that amplifies the optical signal charge for each pixel according to the demand for higher resolution of the solid-state image sensor.
Development is underway.

The main components of this internal amplification type solid-state imaging device are static induction transistor (SIT), amplification type MIS imager (AM
I), various imaging device structures such as charge modulation device (CMD), etc. (for example, regarding AMI, “Journal of the Television Society”, pages 1075 to 1082, Vol 41, No. 11, 1987).
For the year and CMD, see the same magazine, pages 1047 to 1053, and the same issue. ).

Regarding the lateral static induction transistor, Japanese Patent Laid-Open No.
There is a prior art described in JP-A 61-136388.

[Problems to be solved by the invention]

However, the above-mentioned various devices have the following drawbacks.

First, in the SIT type, the device characteristics are sensitive to the structure, and the characteristics are likely to change. Further, the AMI type requires three transistors in the unit cell, and it is difficult to increase the sensitivity and the gain of the transistor.

In the CMD type, the thickness of the n ^- epitaxial layer is 8μ.
It has reached m and is deep. For this reason, it is easy to receive the short channel effect, and at the same time, the current capacity is reduced. Further, in the CMD type, holes are accumulated at a depth very close to the gate, so that the mirror charges (electrons) are collected in the gate. Therefore, the contribution of the photohole to the conductance decreases, and the current amplification rate decreases. Further, regarding the CMD type photosensitivity distribution, the light receiving region functions only in the gate electrode and its vicinity, and sufficient sensitivity cannot be obtained. Further, in the solid-state imaging device, miniaturization and high integration are required, but in the CMD type, it is necessary to form a channel at a depth to capture a photohole, and comparison reduction is not easy.

Therefore, in view of the above technical problems, the present invention has an object to provide a solid-state imaging device which is excellent in photosensitivity and electrical characteristics, and is capable of proportional reduction and the like.

[Means for solving the problem]

In order to achieve the above object, in the solid-state imaging device of the present invention, a second conductivity type source region and a drain region are provided on the surface of a second conductivity type semiconductor layer formed on a first conductivity type semiconductor substrate. At the same time, a gate region is provided between the source region and the drain region, and pixels formed of elements in which a source / drain current flows between the source region and the drain region in parallel with the surface of the semiconductor layer are arranged in a matrix. In the arrayed solid-state imaging device, a first conductivity type island region formed so as to surround the source region is extended to the drain region.

[Action]

In the solid-state imaging device of the present invention, the source region of the second conductivity type formed on the surface of the semiconductor layer of the second conductivity type is surrounded by the island region of the first conductivity type, and the island region is also formed on the surface. It extends to the drain region of the second conductivity type. here,
When the first conductivity type is p-type and the second conductivity type is n-type, the potential distribution has an extreme value in the p-type island region, and photoholes are accumulated in the p-type island region. It will be. Then, the region having the spectral sensitivity reaches the depth of the minimum value of the potential of the n-type semiconductor layer, and the sensitivity is improved. The depth at which the photoholes can be captured can be set independently of the depth at which the photoholes are accumulated depending on the depth, concentration, etc. of the island region, semiconductor layer, semiconductor substrate, etc. By making it shallow, it is possible to suppress the short channel effect and increase the current capacity. In addition, the depth with photosensitivity,
Since the depth at which photo holes are accumulated can be set independently, the proportional reduction can be easily performed. In addition, the p-type island region and the like also have spectral sensitivity in portions other than the gate and the vicinity thereof, and the aperture ratio is greatly improved. Also,
Depending on the depth of the p-type island region, it is easy to accumulate a photohole at a position close to the surface and sufficiently collect the mirror charge on the surface side, which is advantageous for nondestructive readout.

Here, the operation of such a solid-state image pickup device of the present invention will be described with reference to FIGS.
This will be described in more detail with reference to FIG.

FIG. 8 shows a solid-state image sensor (hereinafter, FWA (Flo
ating Well Amplifier) type. ) Model, an n-type well region 101 is formed on a p-type silicon substrate 100, and a p-type well region 102 as an island region is formed surrounded by the n-type well region 101. A source region 103 is formed on the surface of the substrate surrounded by a p-type well region 102, and a drain region 104 is formed on the surface of the substrate on which the p-type well region 102 extends. These source regions 1
Gate electrode 1 on the substrate surface between 03 and drain region 104
05 is formed.

FIG. 10 shows the potential distribution under the gate of the FWA-type model shown in FIG. 8, the curve P ₁ is the curve at the time of accumulation when the level of the gate electrode is low, and the curve P ₂ is the gate. It is a curve at the time of reading when the level of the electrode is high. As shown by the curve P ₁ , if the level of the gate electrode is low, the minimum point u ₁ due to the n-type well region 101
In the shallower region, the photo hole is a p-type well region.
Accumulated in 102. If the level of the gate electrode is high, holes will be collected at the maximum value u ₂ , and the effect of the back gate (body effect) will be added according to the accumulated charge of the holes. Readout is performed by modulating the surface charge.

FIG. 9 shows a model of a CMD type solid-state image pickup device as a conventional example to be compared.
A thick n-type epitaxial layer 111 having a thickness of about 10 μm is formed. On the surface of the thick n-type epitaxial layer 111,
A source region 112 and a drain region 113, each of which is an n ⁺ impurity region, are formed, and a gate electrode 114 is formed above the separated source / drain regions.

FIG. 11 shows the potential distribution under the gate of the device of FIG. 9, where curve P ₃ is when the gate voltage is at a low level (accumulation), and curve P ₄ is when the gate voltage is at a high level. In this element, since the n-type epitaxial layer 111 is formed thick and the bulk mode channel becomes deep, the saturation current amount and the photosensitivity characteristic are deteriorated.

Here, considering parameters by giving parameters to each part corresponding to each potential distribution in FIGS. 10 and 11, first, in the FWA type solid-state imaging device of the present invention, the electron channel from the gate electrode is The distance to the substrate surface to be formed
w ₁ , the distance from the surface channel to the depth at which holes are accumulated is w ₂ , the distance of the depletion layer in silicon is w _s, and the corresponding capacitances are C ₁ , C ₂ , and C _s , respectively.
Let the gate voltage be Vg, the electron charge be Q ₁ , its potential be Φ ₁ , and the hole charge be Q ₂ and its potential be Φ ₂ .

Then, since the charge amount = capacity × potential difference, considering the changing amount, δQ ₁ = C ₁ (δVg−δΦ ₁ ) + C ₂ (δΦ ₂ −δΦ ₁ ) = C ₁ δVg− (C ₁ + C _{2) δΦ 1 + C 2 δΦ} 2 ... δQ 2 = C 2 (δΦ 1 -δΦ 2) -C s δΦ 2 = C 2 δΦ 1 - (C 2 + C s) δΦ 2 ... simultaneous equations are obtained, wherein Therefore, when δΦ ₂ is eliminated, δQ ₁ = C ₁ δVg− (C ₁ + C ₂ C _s / C ₂ + C _s ) δΦ ₁ −C ₂ / (C ₂ + C _s ) δQ ₂ ... Is obtained.

From this formula, it is important as device characteristics: channel capacitance; −δQ ₁ / δΦ ₁ , charge sensitivity; −δQ ₁ / δQ ₂ , gate sensitivity;
When calculated respectively for _{δΦ 1 / δVg, -δQ 1 /} δΦ 1 = (C 1 + C 2 C s / C 2 + C s) αw 1 -1 + (w 2 + w s) -1 ... -δQ 1 / δQ 2 = C ₂ / (C ₂ + C _s ) ∝w _s / (w ₂ + w _s ) ... δΦ ₁ / δVg = C ₁ / (C ₁ + C ₂ C _s / C ₂ + C _s ) ∝ (w ₂ + w _s ) / (W ₁ + w ₂ + w _s ) ... (∵C ₁ = ε _si / w ₁ , C ₂ = ε _si / w ₂ , C _s = ε _si / w _s ).

On the other hand, the same parameters were given to the CMD elements of FIGS. 9 and 11, and the distance from the gate electrode to the substrate surface where holes were accumulated was w ₀₁ , and the distance from the surface channel to the electron channel depth. Is w ₀₂ , the distance of the depletion layer in silicon is w _ss, and the corresponding capacitance is C
Let ₀₁ , C ₀₂ , and C _ss be, the gate voltage be Vg, the hole charge be Q ₀₁ , the potential be Φ ₀₁ , and the electron charge be Q ₀₂ , and the potential be Φ ₀₂ . Then, a similar simultaneous equation is obtained, and δQ ₀₁ = C ₀₁ (δVg−δΦ ₀₁ ) + C ₀₂ (δΦ ₀₂ −δΦ ₀₁ ) = C ₀₁ δVg− (C ₀₁ + C ₀₂ ) δΦ ₀₁ + C ₀₂ δΦ ₀₂ … δQ ₀₂ = C ₀₂ (δΦ ₀₁ −δΦ ₀₂ ) −C _ss δΦ ₀₂ ＝ C ₀₂ δΦ ₀₁ − (C ₀₂ + C _ss ) δΦ ₀₂ … From these equations, δQ ₀₂ = − (C ₀₁ C ₀₂ / (C ₀₁ + C ₀₂ ) + C _ss ) δΦ ₀₂ + C ₀₂ ² δVg / (C ₀₁ + C ₀₂ ) -C ₀₂ δΦ ₀₁ / (C ₀₁ + C ₀₂ ) ... From this equation, it is also important as device characteristics: channel capacitance; −δQ ₀₂ / δΦ ₀₂ , charge sensitivity; −δQ ₀₂ / δQ ₀₁ , gate sensitivity; δΦ ₀₂ / δVg, −δQ ₀₂ / δΦ ₀₂ = (C ₀₁ C ₀₂ / (C ₀₁ + C ₀₂ ) + C _ss ) ∝ (w ₀₁ ＋ w ₀₂ ) ^-1 ＋ w _ss ^-1 … －δQ ₀₂ ／ δQ ₀₁ ＝ C ₀₂ ／ (C ₀₁ ＋ C ₀₂ ) ∝w ₀₁ ／ （w ₀₁ ＋ W _ss ） …… δΦ ₀₂ ／ δVg ＝ C ₀₂ ² / ((C ₀₁ + C ₀₂ ) C _ss ＋ C ₀₁ C ₀₂ ) ∝ (w ₀₁ ＋ w _ss ) / w ₀₂ (w ₀₁ ＋ w ₀₂ ＋ w _ss ) …… (∵C ₀₁ ＝ ε _si ／ w ₀₁ 、 C ₀₂ ＝ ε _si ／ w ₀₂ 、 C _ss ＝ ε _si ／
w _ss ).

Here, as the parameters constituting each element, the numerical values of w ₁ = 0.1 μm, w ₂ = 1 μm, w _s = 5 μm are substituted into the formula to, and w ₀₁ = 0.1 μm, w ₀₂ = 2 μm, w _ss = 10 μm
Substituting each numerical value of, the channel capacitance (Cc
h), charge sensitivity (δQch / δQphoto)
And gate sensitivity (δΦch / δVg) are compared for each value. The values of w ₁ and w ₀₁ are values obtained by correcting the dielectric constant, and are related to the solid-state image sensor of the present invention.
For w ₂ and w _s , numerical values slightly different from the optimum values are substituted. The results are shown in the table.

By such comparison, the FWA type according to the solid-state image pickup device of the present invention can improve the characteristics about 16 to 17 times in terms of saturation current amount (Cch) and photosensitivity (ΔQch / ΔQphoto) compared to the CMD type. Therefore, the gate selectivity (δΦch / δVg)
It can also be seen that it also improves. Moreover, the characteristics are further improved by optimizing the parameters of the FWA type.

Further, as shown in FIG. 8, in the solid-state imaging device of the present invention, the p-type well region 102 also extends below the source region 103 and the drain region 104.
Since the optical signal charge is accumulated in 02, even when light is incident on the source region 103 and the drain region 104, the photosensitivity can be obtained, and the sensitivity of the device is further increased in addition to the above-mentioned characteristic improvement. Become.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

First, the basic configuration will be described with reference to FIGS. 1 to 3. As shown in FIG. 1, in the solid-state imaging device of the present embodiment, the pixel is of the first conductivity type p. An n-type well region 2 as a semiconductor layer is formed on a type silicon substrate 1. On the surface of the n-type well region 2, an n ⁺ -type source region 4 and an n ⁺ -type drain region 5 of the same conductivity type are formed, and between the source region 4 and the drain region 5, an upper part is formed. A gate region in which the gate electrode 7 is arranged is provided via the insulating film 6. Then, a p-type well region 3 which is a first conductivity type island region is formed so as to surround the source region 4 on the substrate surface, and the p-type well region 3 extends to the drain region 5. In the source region 4, an aluminum wiring layer 8 is formed on the substrate surface with an opening in the insulating film 6. Here, the depth of each region is the depth of the center of its concentration distribution, and the n-type well region 2 has a depth of 2.5, for example.
μm, and the p-type well region 3 has, for example, 1.0 μm
The source fishing season 4 and the drain region 5 are, for example, about 0.5 μm. The concentration of the silicon substrate 1 is about 3 × 10 ¹⁴ cm ^-3 .

Next, the potential distribution is as shown in FIGS. 2 and 3. FIG. 2 is a potential distribution along the II-II line cross section of FIG. 1, and the solid line P ₀₁ shows the potential when the gate voltage is at a low level. At this time,
The solid line P ₀₁ has a minimum point s ₀ at the depth of the n-type well region 2, and photoholes are accumulated along the potential gradient in the region shallower than that depth. In FIG. 2, broken line P ₀₂
Indicates the potential when the gate voltage is at a high level, and when there is accumulation of optical signal charges when the gate voltage is at a high level, the potential distribution is as indicated by the one-dot chain line P ₀₃ .
When the gate voltage is at a high level, a maximum potential point s ₁ is formed in the depth of the p-type well region 3, and a channel is formed on the surface according to the charge amount Qh of the photohole accumulated at this maximum point. To be done. That is, the effect of the back gate (body effect) is added according to the charge amount Qh of the holes, and the number of electrons in the surface channel is modulated. The source / drain current changes depending on the amount of charge Qe on the surface, and eventually, reading according to the signal charge becomes possible.

FIG. 3 is a potential distribution of a cross section along the line III-III in FIG. 1, and the curve P ₀₄ has a minimum due to the p-type well region 3, the n-type well region 2 and the p-type silicon substrate 1. The value s ₂ is provided. As a result, photoholes will be accumulated in a region shallower than this minimum value s ₂ .
The accumulated photoholes will be collected on the lower side of the gate having a lower potential. Therefore, in the solid-state image sensor of the present embodiment, even in the region below the drain region 5 and the source region 4 where the gate electrode 7 is not formed,
Since it has photosensitivity, its sensitivity is improved.

In such an element, the region having the spectral sensitivity is up to the depth of the extreme values s ₀ and s ₂ of the n-type well region 2, and the sensitivity is improved. Further, the depth can be set independently of the depth (s ₁ ) at which photoholes are accumulated depending on the depth and concentration of the p-type well region 3, the n-type well region 2, the silicon substrate 1, The proportional reduction can be easily performed, and the short channel effect can be suppressed and the current capacity can be increased by reducing the depth where the channel is formed. In addition, the gate and the portion other than the vicinity thereof have photosensitivity, and the aperture ratio is greatly improved. In addition, it is advantageous for non-destructive reading.

Next, an example of the plane layout of the solid-state image sensor of the present embodiment will be described with reference to FIG. The solid-state image sensor of the present embodiment has a configuration in which reset means is added because it is necessary to reset the signal charge accumulated in the p-type well region.

As shown in FIG. 4, the planar layout has a p-type well region 3 formed in a square shape as shown by the alternate long and short dash line in the drawing, and extends from the perimeter of the p-type well region 3 to the inside. The gate electrode 7 is routed. The shape of the gate electrode 7 is formed so as to surround the source region 4 having a substantially square shape in accordance with the shape of the well region 3, and one side thereof is formed.
In 7a, it is extended to connect to the scanning circuit in the horizontal direction in the drawing. The gate electrode 7 laid out in this substantially square shape
An aluminum wiring layer 8 serving as a vertical signal line is connected from a source region 4 inside the via a contact hole 9.

By the way, as described above, in the solid-state imaging device of the present embodiment, photoholes are accumulated in the p-type well region 3 and the number of electrons in the surface channel is modulated. Therefore, when resetting a signal, it is necessary to apply a reset voltage to the p-type well region 3. Therefore, in the solid-state image sensor of this embodiment, the reset means 10 connected to the p-type well region 3 is formed. This reset means
10 also functions to control overflow, and reset and overflow are controlled by the potential of the reset gate electrode 11 connected to this reset means 10.

The reset means 10 is specifically shown in FIG.
The configuration shown in FIG. The fifth
FIGS. A and b correspond to the VV line cross section of FIG.

FIG. 5a shows an example of the reset means 10, which is an example of sweeping unnecessary charges into the p-type silicon substrate 1. That is, the source / drain regions 12a and 12b of the reset transistor are formed on the substrate surface on both ends of the reset gate electrode 11, and one of the source / drain regions 12a is connected to the p-type well region 3. Also, the other source
The drain region 12b is connected to the p-type silicon substrate 1 via the region 13 between the n-type well regions 2 and 2. Then, by lowering the potential of the reset gate electrode 11, a channel is formed between the source / drain regions 12a and 12b, and the charges are swept out to the p-type silicon substrate 1 through the region 13.

With such a structure, overflow control can be performed when light is received. Further, at the time of resetting, it is possible to reset the charges of the pixels accumulated in the p-type well region 3.

FIG. 5b shows another example of the reset means 10,
This is an example in which unnecessary charges are swept out to the electrode 15. The structure is such that the source / drain regions 14a and 14b of the reset transistor are formed on the substrate surface on both ends of the reset gate electrode 11, and one of the source / drain regions 14a is connected to the p-type well region 3. Also, the other source
A contact hole is formed on the drain region 14b to connect the electrode 15.

FIG. 6 is a diagram showing the function of the potential of the reset means of FIG. 5b, in which the broken line ΦOFCG shows the potential barrier by the reset gate electrode 11, and the level Φ ₂ is the level when there is no accumulation of photoholes. And the level Φ _f is the level when the photohole is full. ΦOF
By controlling the level of CG, unnecessary charges (holes) are swept out to the source / drain region 14b functioning as an overflow drain and the electrode 15. At the time of reset, the level of the reset gate electrode 11 changes and the potential of ΦOFCG changes, and the level of the p-type well region 3 is returned to the level Φ _z .

Next, with reference to FIG. 7, an example of the circuit configuration of the solid-state imaging device of the present embodiment will be briefly described.

The circuit configuration is such that each pixel has a transistor 22 for amplification, a photodiode 21 arranged in series with a capacitor 24 is arranged on the channel side, and the current from the transistor 22 for amplification is changed by the charge from the photodiode 21. Is modulated. The reset transistor 23 is a photodiode 21.
To one end (p-type well region 3) to reset the signal charge. Such pixels are arranged in a matrix and the vertical gate lines VG _n and V from the first vertical scanning circuit 32 are arranged.
The signals from the amplifying transistor 22 appear on the vertical signal lines H _m , H _{m + 1} , ... By G _{n + 1} ,. The reset operation is performed by the vertical reset lines VR _n , VR _{n + 1} , ... From the second vertical scanning circuit 33.
Then, the gate voltage of the reset transistor 23 changes, and the reset operation is performed. The overflow can be controlled by the reset line at the time of light reception. The signals appearing on the vertical signal lines H _m , H _{m + 1} , ... Are turned on by the horizontal switch 34 selected by the horizontal scanning circuit 31.
When turned off, the amplifier 35 is sequentially read onto the horizontal signal line VL and provided so as to terminate the horizontal signal line VL.
Will be output via.

〔The invention's effect〕

In the solid-state imaging device of the present invention, as described above, the first conductivity type island region extending from the second conductivity type source region to the drain region formed on the surface of the second conductivity type semiconductor layer is formed. The depth required to obtain the spectral sensitivity and the depth of the island region from the substrate can be independently set by the potential formed by the island region. Therefore, the proportional reduction can be easily performed and the spectral sensitivity can be increased. Further, by making the depth of the channel shallow, it is possible to suppress the short channel effect and increase the current capacity. Further, by providing the island region of the opposite conductivity type, the area other than the gate and the vicinity thereof also has photosensitivity, and the aperture ratio thereof is significantly improved. It is also advantageous for non-destructive reading.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an essential part of an example of the solid-state image pickup device of the present invention, FIG. 2 is a potential distribution diagram along the line II-II in FIG. 1, and FIG. 3 is a line III-III in FIG. FIG. 4 is a cross-sectional view showing an example of the reset means, FIG. 5b is a cross-sectional view showing another example of the reset means, and FIG. FIG. 6 is a cross-sectional view showing an example, FIG. 6 is an explanatory view for explaining the potential in the reset means, FIG. 7 is a circuit diagram showing a circuit configuration example of the solid-state image pickup device of the present invention, and FIG. 8 is a solid-state image of the present invention. FIG. 9 is a sectional view showing the structure of the model of the image pickup device, FIG. 9 is a sectional view showing the structure of the model of the conventional solid-state image pickup device, and FIG. 10 is a potential distribution diagram just below the gate of the device of FIG.
FIG. 11 is a potential distribution diagram just below the gate of the device of FIG. DESCRIPTION OF SYMBOLS 1 ... P-type silicon substrate 2 ... N-type well region 3 ... P-type well region 4 ... Source region 5 ... Drain region 6 ... Insulating film 7 ... Gate electrode

Claims (1)

(57) [Claims] 1. A second substrate formed on a semiconductor substrate of the first conductivity type.
The source region and the drain region of the second conductivity type are provided on the surface of the conductivity type semiconductor layer, and the gate region is provided between the source region and the drain region, and the semiconductor layer of the semiconductor layer is provided between the source region and the drain region. In a solid-state imaging device in which pixels are arranged in a matrix in which source / drain currents flow in parallel to the surface, a first conductivity type island region formed so as to surround the source region extends to the drain region. A solid-state image sensor characterized by being present.