US20230019977A1 - Gate-Controlled Charge Modulated Device for CMOS Image Sensors - Google Patents
Gate-Controlled Charge Modulated Device for CMOS Image Sensors Download PDFInfo
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- US20230019977A1 US20230019977A1 US17/684,124 US202217684124A US2023019977A1 US 20230019977 A1 US20230019977 A1 US 20230019977A1 US 202217684124 A US202217684124 A US 202217684124A US 2023019977 A1 US2023019977 A1 US 2023019977A1
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- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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Definitions
- This application relates generally to semiconductor devices and circuits. More particularly, the disclosed embodiments relate to semiconductor devices and circuits for sensing short-wave infrared light.
- Digital image sensors have gained significant popularity in recent years. For example, many digital cameras, mobile computers, and mobile phones include digital image sensors for capturing images.
- CMOS complementary metal-oxide-semiconductor
- CMD charge modulation device
- some embodiments involve a device for sensing light.
- the device includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type.
- the second semiconductor region is positioned above the first semiconductor region; and the first type is distinct from the second type.
- the device includes a gate insulation layer positioned above the second semiconductor region; a gate positioned above the gate insulation layer; a source electrically coupled with the second semiconductor region; and a drain electrically coupled with the second semiconductor region.
- the second semiconductor region has a top surface that is positioned toward the gate insulation layer, and the second semiconductor region has a bottom surface that is positioned opposite to the top surface of the second semiconductor region.
- the second semiconductor region has an upper portion that includes the top surface of the second semiconductor region.
- the second semiconductor region also has a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion.
- the first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.
- the first semiconductor region is in contact with the upper portion of the second semiconductor region at least at a location positioned under the gate.
- the first type is an n-type and the second type is a p-type.
- the first type is a p-type and the second type is an n-type.
- the second semiconductor region has a first lateral surface that extends from the source to the drain and is distinct from the top surface and the bottom surface.
- the second semiconductor region has a second lateral surface that extends from the source to the drain and is distinct from the top surface and the bottom surface.
- the first semiconductor region is in contact with the upper portion of the second semiconductor region through a portion of the first lateral surface.
- the first semiconductor region is in contact with the upper portion of the second semiconductor region through a portion of the second lateral surface.
- the first semiconductor region includes germanium.
- the second semiconductor region includes germanium.
- the gate insulation layer includes an oxide layer.
- the device includes a substrate insulation layer positioned below the first semiconductor region.
- the substrate insulation layer includes one or more of: SiO 2 , GeO x , ZrO x , HfO x , Si x N y , Si x O y N z , Ta x O y , Sr x O y and Al x O y .
- the device includes a third semiconductor region that includes germanium doped with a dopant of the second type.
- the third semiconductor region is positioned below the first semiconductor region.
- a doping concentration of the dopant of the second type in the second semiconductor region is higher than a doping concentration of the dopant of the second type in the third semiconductor region.
- the device includes a silicon substrate.
- the gate includes one or more of: polygermanium, amorphous germanium, polysilicon, amorphous silicon, silicon carbide, and metal.
- the second semiconductor region extends from the source to the drain.
- the first semiconductor region extends from the source to the drain.
- the gate insulation layer extends from the source to the drain.
- the second semiconductor region defines multiple channels between the source and the drain.
- the second semiconductor region has a thickness less than 100 nm.
- the first semiconductor region has a thickness less than 1000 nm.
- a sensor array includes a plurality of devices formed on a common silicon substrate, wherein each device of the plurality of devices corresponds to any of the above-described devices.
- the plurality of devices has the first semiconductor region on a common plane.
- the plurality of devices has the second semiconductor region on a common plane.
- the plurality of devices has the third semiconductor region on a common plane.
- the plurality of devices is separated by one or more trenches.
- the plurality of devices is positioned on separate germanium islands formed on the common silicon substrate.
- the sensor array includes a passivation layer over the plurality of devices.
- the sensor array includes a passivation layer between the plurality of devices.
- a method of forming a device for sensing light includes forming a first semiconductor region, above a silicon substrate, doped with a dopant of a first type and forming a second semiconductor region, above the silicon substrate, doped with a dopant of a second type.
- the second semiconductor region is positioned above the first semiconductor region.
- the first type is distinct from the second type.
- the method also includes forming a gate insulation layer above the second semiconductor region. One or more portions of the second semiconductor region are exposed from the gate insulation layer to define a source and a drain.
- the second semiconductor region has a top surface that faces the gate insulation layer.
- the second semiconductor region has a bottom surface that is opposite to the top surface of the second semiconductor region.
- the second semiconductor region has an upper portion that includes the top surface of the second semiconductor region.
- the second semiconductor region has a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion.
- the first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.
- the first semiconductor region is in contact with the upper portion of the second semiconductor region at least at a location positioned under the gate.
- the method further includes forming a gate positioned above the gate insulation layer.
- the first semiconductor region is formed by epitaxially growing the first semiconductor region.
- the first semiconductor region is doped in-situ with the dopant of the first type while the first semiconductor region is grown.
- the first semiconductor region is doped with the dopant of the first type using an ion implantation process or a gas phase diffusion process.
- the second semiconductor region is formed by epitaxially growing the second semiconductor region.
- the second semiconductor region is doped in-situ with the dopant of the second type while the second semiconductor region is grown.
- the second semiconductor region is doped with the dopant of the second type using an ion implantation process or a gas phase diffusion process.
- the second semiconductor region is doped with the dopant of the second type using an ion implantation process after the first semiconductor region is doped with the dopant of the first type using an ion implantation process or a gas phase diffusion process.
- a method of forming a sensor array includes concurrently forming a plurality of devices on a common silicon substrate using any of the above-described methods.
- a sensor circuit includes a photo-sensing element, the photo-sensing element having a source terminal, a gate terminal, a drain terminal, and a body terminal.
- the sensor circuit also includes a selection transistor having a source terminal, a gate terminal, and a drain terminal. The drain terminal of the selection transistor is electrically coupled with the source terminal of the photo-sensing element or the source terminal of the selection transistor is electrically coupled with the drain terminal of the photo-sensing element.
- the photo-sensing element is any of the above-described devices.
- the source terminal or the drain terminal, of the photo-sensing element, that is not electrically coupled with the source terminal or the drain terminal of the selection transistor is connected to a ground.
- the source terminal or the drain terminal, of the photo-sensing element, that is electrically coupled with the source terminal or the drain terminal of the selection transistor is not connected to a ground.
- the source terminal or the drain terminal, of the photo-sensing element, that is electrically coupled with the source terminal or the drain terminal of the selection transistor is electrically coupled with a voltage source.
- the voltage source provides a fixed voltage.
- the sensor circuit includes no more than two transistors, the two transistors including the selection transistor.
- the sensor circuit includes no more than one transistor, the one transistor being the selection transistor.
- a converter circuit includes a first transimpedance amplifier having an input terminal electrically coupled with the source terminal or the drain terminal, of the selection transistor of a first sensor circuit that corresponds to any of the above-described sensor circuits, that is not electrically coupled with the source terminal or the drain terminal of the photo-sensing element.
- the first transimpedance amplifier is configured to convert a current input from the photo-sensing element into a voltage output.
- the converter circuit also includes a differential amplifier having two input terminals, a first input terminal of the two input terminals electrically coupled with the voltage output of the first transimpedance amplifier and a second input terminal of the two input terminals electrically coupled with a voltage source that is configured to provide a voltage corresponding to a base current provided by the photo-sensing element.
- the differential amplifier is configured to output a voltage based on a voltage difference between the voltage output and the voltage provided by the voltage source.
- the first transimpedance amplifier includes an operational amplifier.
- the base current corresponds to a current provided by the photo-sensing element while the photo-sensing element receives substantially no light.
- the voltage source is a second transimpedance amplifier having an input terminal electrically coupled with a second sensor circuit that corresponds to any of the above-described sensor circuits and is distinct from the first sensor circuit.
- the input terminal of the second transimpedance amplifier is electrically coupled with the source terminal or the drain terminal of the selection transistor of the second sensor circuit.
- the second transimpedance amplifier includes an operational amplifier.
- the photo-sensing element of the second sensor circuit is optically covered so that the photo-sensing element of the second sensor circuit is prevented from receiving light.
- the voltage source is a digital-to-analog converter.
- the converter circuit includes an analog-to-digital converter electrically coupled to an output of the differential amplifier, the analog-to-digital converter configured to convert the output of the differential amplifier into a digital signal.
- the first transimpedance amplifier is configured to electrically couple with a respective sensor circuit of a plurality of sensor circuits through a multiplexer.
- an image sensor device includes an array of sensors.
- a respective sensor in the array of sensors includes any of the above-described sensor circuits.
- the image sensor device includes any of the above-described converter circuits.
- the array of sensors includes multiple rows of sensors; and, for sensors in a respective row, gate terminals of selection transistors are electrically coupled to a common selection line.
- the array of sensors includes multiple columns of sensors; and, for sensors in a respective column, one of source terminals or drain terminals of selection transistors are electrically coupled to a common column line.
- a method includes exposing the photo-sensing element of any of the above-described sensor circuits. The method also includes providing a fixed voltage to the source terminal of the photo-sensing element; and measuring a drain current of the photo-sensing element.
- the method includes determining an intensity of the light based on the drain current of the photo-sensing element.
- measuring the drain current includes converting the drain current to a voltage signal.
- converting the drain current to the voltage signal includes using a transimpedance amplifier to convert the drain current to the voltage signal.
- measuring the drain current includes using any of the above-described converter circuits.
- the method includes activating the selection transistor of the sensor circuit.
- the fixed voltage is provided to the source terminal of the photo-sensing element prior to exposing the photo-sensing element to light.
- the fixed voltage is provided to the source terminal of the photo-sensing element subsequent to exposing the photo-sensing element to light.
- a method includes exposing the array of sensors of any of the above-described image sensor devices to a pattern of light. The method also includes, for a photo-sensing element of a respective sensor in the array of sensors, providing a respective voltage to the source terminal of the photo-sensing element of the respective sensor; and measuring a drain current of the photo-sensing element.
- the source terminals of the photo-sensing elements in the array of sensors concurrently receive respective voltages.
- the source terminals of the photo-sensing elements in the array of sensors sequentially receive respective voltages.
- the source terminals of photo-sensing elements in the array of sensors receive a same voltage.
- the drain currents of the photo-sensing elements in the array of sensors are measured in batches.
- the drain currents of the photo-sensing elements in the array of sensors are concurrently measured.
- the drain currents of the photo-sensing elements in the array of sensors are sequentially measured.
- FIG. 1 A is a partial cross-sectional view of a semiconductor optical sensor device in accordance with some embodiments.
- FIG. 1 B is a partial cross-sectional view of the semiconductor optical sensor device illustrated in FIG. 1 A , in accordance with some embodiments.
- FIG. 2 A is a schematic diagram illustrating an operation of a semiconductor optical sensor device in accordance with some embodiments.
- FIG. 2 B is a schematic diagram illustrating the operation of the semiconductor optical sensor device illustrated in FIG. 2 A , in accordance with some embodiments.
- FIG. 3 illustrates exemplary band diagrams in accordance with some embodiments.
- FIG. 4 A is a schematic diagram illustrating a single channel configuration of a semiconductor optical sensor device in accordance with some embodiments.
- FIG. 4 B is a schematic diagram illustrating a multi-channel configuration of a semiconductor optical sensor device in accordance with some embodiments.
- FIG. 5 is a partial cross-sectional view of semiconductor optical sensor devices in accordance with some embodiments.
- FIG. 6 illustrates an exemplary sensor circuit in accordance with some embodiments.
- FIG. 7 A illustrates an exemplary 3T-APS circuit in accordance with some embodiments.
- FIG. 7 B illustrates an exemplary 1T-MAPS circuit in accordance with some embodiments.
- FIGS. 8 A- 8 H illustrate exemplary sensor circuits in accordance with some embodiments.
- FIGS. 9 A- 9 C illustrate exemplary converter circuits in accordance with some embodiments.
- FIG. 10 illustrates an exemplary image sensor device in accordance with some embodiments.
- FIGS. 11 A- 11 E illustrate an exemplary method for making a semiconductor optical sensor device in accordance with some embodiments.
- CMOS complementary metal-oxide-semiconductor
- the structures described herein are particularly useful for detecting short-wave infrared light. However, such structures may be used for detecting visible light.
- first semiconductor region could be termed a second semiconductor region, and, similarly, a second semiconductor region could be termed a first semiconductor region, without departing from the scope of the claims.
- the first semiconductor and the second semiconductor region are both semiconductor regions, but they are not the same semiconductor regions.
- FIG. 1 A is a partial cross-sectional view of a semiconductor optical sensor device 100 in accordance with some embodiments.
- the device 100 is called a gate-controlled charge modulated device (GCMD).
- GCMD gate-controlled charge modulated device
- the device 100 includes a first semiconductor region 104 doped with a dopant of a first type (e.g., an n-type semiconductor, such as phosphorus or arsenic) and a second semiconductor region 106 doped with a dopant of a second type (e.g., a high concentration of a p-type semiconductor, such as boron, which is often indicated using a p+ symbol).
- the second semiconductor region 106 is positioned above the first semiconductor region 104 .
- the first type e.g., n-type
- the second semiconductor region 106 is positioned over the first semiconductor region 104 .
- the device includes a gate insulation layer 110 positioned above the second semiconductor region 106 and a gate 112 positioned above the gate insulation layer 110 .
- the gate insulation layer 110 is positioned over the second semiconductor region 106 .
- the gate insulation layer 110 is in contact with the second semiconductor region 106 .
- the gate 112 positioned over the gate insulation layer 110 .
- the gate 112 is in contact with the gate insulation layer 110 .
- the device also includes a source 114 electrically coupled with the second semiconductor region 106 and a drain 116 electrically coupled with the second semiconductor region 106 .
- the second semiconductor region 106 has a top surface 120 that is positioned toward the gate insulation layer 110 .
- the second semiconductor region 106 also has a bottom surface 122 that is positioned opposite to the top surface 120 of the second semiconductor region 106 .
- the second semiconductor region 106 has an upper portion 124 that includes the top surface 120 of the second semiconductor region 106 .
- the second semiconductor region 106 also has a lower portion 126 that includes the bottom surface 122 of the second semiconductor region 106 .
- the lower portion 126 is mutually exclusive with the upper portion 124 .
- the upper portion 124 and the lower portion 126 refer to different portions of the second semiconductor region 106 . Thus, in some embodiments, there is no physical separation of the upper portion 124 and the lower portion 126 .
- the lower portion 126 refers to a portion of the second semiconductor region 106 that is not the upper portion 124 .
- the upper portion 124 has a thickness less than 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm.
- the upper portion 124 has a uniform thickness from the source 114 to the drain 116 .
- the upper portion 124 and the lower portion 126 have a same thickness at a horizontal location directly below the gate 112 .
- the first type is an n-type and the second type is a p-type.
- the first semiconductor region is doped with an n-type semiconductor and the source 114 , the drain 116 , and a channel between the source 114 and the drain 116 are doped with a p-type semiconductor, which is called a PMOS structure.
- the first type is a p-type and the second type is an n-type.
- the first semiconductor region is doped with a p-type semiconductor and the source 114 , the drain 116 , and a channel between the source 114 and the drain 116 are doped with an n-type semiconductor, which is called an NMOS structure.
- the first semiconductor region 104 includes germanium.
- the second semiconductor region 106 includes germanium.
- the direct band gap energy of germanium is around 0.8 eV at room temperature, which corresponds to a wavelength of 1550 nm.
- the gate insulation layer 110 includes an oxide layer (e.g., SiO 2 , GeO x , ZrO x , HfO x , Si x N y , Si x O y N z , Ta x O y , Sr x O y or Al x O y ).
- the gate insulation layer 110 includes an oxynitride layer (e.g., SiON).
- the gate insulation layer 110 includes a high- ⁇ dielectric material, such as HfO 2 , HfSiO, or Al 2 O 3 .
- the device includes a substrate insulation layer 108 positioned below the first semiconductor region 104 .
- the substrate insulation layer includes one or more of: SiO 2 , GeO x , ZrO x , HfO x , Si x N y , Si x O y N z , Ta x O y , Sr x O y and Al x O y .
- the substrate insulation layer 108 includes a high- ⁇ dielectric material.
- the first semiconductor region 104 is positioned over the substrate insulation layer 108 .
- the first semiconductor region 104 is in contact with the substrate insulation layer 108 .
- the substrate insulation layer 108 is positioned over the substrate 102 (e.g., a silicon substrate). In some embodiments, the substrate insulation layer 108 is in contact with the substrate 102 .
- the device includes a third semiconductor region 108 that includes germanium doped with a dopant of the second type (e.g., p-type).
- the third semiconductor region 108 is positioned below the first semiconductor region 104 .
- a doping concentration of the dopant of the second type in the second semiconductor region 106 is higher than a doping concentration of the dopant of the second type in the third semiconductor region 108 .
- the second semiconductor region 106 has a p+ doping (e.g., at a concentration of one dopant atom per ten thousand atoms or more) and the third semiconductor region 108 has a p doping (e.g., at a concentration of one dopant atom per hundred million atoms).
- the device includes a silicon substrate 102 .
- the third semiconductor region 108 , the first semiconductor region 104 , and the second semiconductor region 106 are formed over the silicon substrate 102 .
- the gate 112 includes one or more of: polysilicon, amorphous silicon, silicon carbide, and metal. In some embodiments, the gate 112 consists of one or more of: polygermanium, amorphous germanium, polysilicon, amorphous silicon, silicon carbide, and metal.
- the second semiconductor region 106 extends from the source 114 to the drain 116 .
- the first semiconductor region 104 extends from the source 114 to the drain 116 .
- the gate insulation layer 110 extends from the source 114 to the drain 116 .
- the second semiconductor region 106 has a thickness less than 100 nm. In some embodiments, the second semiconductor region 106 has a thickness between 1 nm than 100 nm. In some embodiments, the second semiconductor region 106 has a thickness between 5 nm than 50 nm. In some embodiments, the second semiconductor region 106 has a thickness between 50 nm than 100 nm. In some embodiments, the second semiconductor region 106 has a thickness between 10 nm than 40 nm. In some embodiments, the second semiconductor region 106 has a thickness between 10 nm than 30 nm. In some embodiments, the second semiconductor region 106 has a thickness between 10 nm than 20 nm.
- the second semiconductor region 106 has a thickness between 20 nm than 30 nm. In some embodiments, the second semiconductor region 106 has a thickness between 30 nm than 40 nm. In some embodiments, the second semiconductor region 106 has a thickness between 40 nm than 50 nm.
- the first semiconductor region 104 has a thickness less than 1000 nm. In some embodiments, the first semiconductor region 104 has a thickness between 1 nm and 1000 nm. In some embodiments, the first semiconductor region 104 has a thickness between 5 nm and 500 nm. In some embodiments, the first semiconductor region 104 has a thickness between 500 nm and 1000 nm. In some embodiments, the first semiconductor region 104 has a thickness between 10 nm and 500 nm. In some embodiments, the first semiconductor region 104 has a thickness between 10 nm and 400 nm. In some embodiments, the first semiconductor region 104 has a thickness between 10 nm and 300 nm.
- the first semiconductor region 104 has a thickness between 10 nm and 200 nm. In some embodiments, the first semiconductor region 104 has a thickness between 20 nm and 400 nm. In some embodiments, the first semiconductor region 104 has a thickness between 20 nm and 300 nm. In some embodiments, the first semiconductor region 104 has a thickness between 20 nm and 200 nm. In some embodiments, the first semiconductor region 104 has a thickness between 20 nm and 400 nm. In some embodiments, the first semiconductor region 104 has a thickness between 20 nm and 300 nm. In some embodiments, the first semiconductor region 104 has a thickness between 20 nm and 200 nm. In some embodiments, the first semiconductor region 104 has a thickness between 20 nm and 100 nm.
- FIG. 1 A also indicates plane AA upon which the view illustrated in FIG. 1 B is taken.
- FIG. 1 B is a partial cross-sectional view of the semiconductor optical sensor device illustrated in FIG. 1 A , in accordance with some embodiments.
- FIG. 1 B the first semiconductor region 104 , the second semiconductor region 106 , the gate insulation layer 110 , the gate 112 , the substrate insulation layer or third semiconductor region 108 , and the substrate 102 are illustrated. For brevity, the description of these elements are not repeated herein.
- the first semiconductor region 104 is in contact with both the upper portion 124 and the lower portion 126 of the second semiconductor region 106 .
- the first semiconductor region 104 is in contact with the upper portion 124 of the second semiconductor region 106 at least at a location positioned under the gate 112 .
- the first semiconductor region 104 is in contact with the upper portion 124 of the second semiconductor region 106 at least at a location positioned directly under the gate 112 .
- the first semiconductor region 104 is in contact with the top surface 120 of the second semiconductor region 106 at least on an edge of the top surface 120 of the second semiconductor region 106 .
- the first semiconductor region 104 is in contact with the top surface 120 of the second semiconductor region 106 at least on an edge of the top surface 120 of the second semiconductor region 106 at a location directly under the gate 112 .
- the second semiconductor region 106 has a first lateral surface (e.g., a combination of a lateral surface 128 of the upper portion 124 and a lateral surface 130 of the lower portion 126 ) that extends from the source 114 ( FIG. 1 A ) to the drain 116 ( FIG. 1 A ) and is distinct from the top surface 120 and the bottom surface 122 .
- the second semiconductor region 106 has a second lateral surface (e.g., a combination of a lateral surface 132 of the upper portion 124 and a lateral surface 134 of the lower portion 126 ) that extends from the source 114 ( FIG. 1 A ) to the drain 116 ( FIG.
- first semiconductor region 104 is in contact with the upper portion 124 of the second semiconductor region 106 through a portion 128 of the first lateral surface. In some embodiments, the first semiconductor region 104 is in contact with the upper portion 124 of the second semiconductor region 106 through a portion 132 of the second lateral surface.
- the first semiconductor region 104 is in contact with the upper portion 124 of the second semiconductor region 106 through a portion 128 of the first lateral surface at a location directly under the gate 112 and the first semiconductor region 104 is also in contact with the upper portion 124 of the second semiconductor region 106 through a portion 132 of the second lateral surface at a location directly under the gate 112 .
- the lateral surface 128 of the upper portion 124 has a thickness less than 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm. In some embodiments, the lateral surface 132 of the upper portion 124 has a thickness less than 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm. In some embodiments, the lateral surface 128 of the upper portion 124 has a thickness less a thickness of the lateral surface 130 of the lower portion 126 . In some embodiments, the lateral surface 132 of the upper portion 124 has a thickness less a thickness of the lateral surface 134 of the lower portion 126 .
- FIGS. 2 A- 2 B are used below to illustrate operational principles of the semiconductor optical sensor device in accordance with some embodiments. However, FIGS. 2 A- 2 B and the described principles are not intended to limit the scope of claims.
- FIG. 2 A is a schematic diagram illustrating an operation of a semiconductor optical sensor device in accordance with some embodiments.
- FIG. 2 A The device illustrated in FIG. 2 A is similar the device illustrated in FIG. 1 A .
- the description of the elements described above with respect to FIG. 1 A is not repeated herein.
- the first semiconductor region 104 is doped with an n-type semiconductor.
- the second semiconductor region 106 is heavily doped with a p-type semiconductor.
- the third semiconductor region 108 is doped with a p-type semiconductor. In some embodiments, the third semiconductor region 108 is lightly doped with the p-type semiconductor.
- a potential well 202 is formed between the second semiconductor region 106 and the gate insulation layer 110 . While the device (in particular, the first semiconductor region 104 ) is exposed to light, photo-generated carriers are generated. While voltage V G is applied to the gate 112 , the photo-generated carriers migrate to the potential well 202 .
- FIG. 2 B is a schematic diagram illustrating the operation of the semiconductor optical sensor device illustrated in FIG. 2 A , in accordance with some embodiments.
- FIG. 2 B is similar to FIG. 2 A .
- the description of the same elements described above with respect to FIG. 1 B is not repeated herein.
- the migration path of the photo-generated carriers to the potential well 202 located between the second semiconductor region 106 and the gate insulation layer 110 is indicated.
- the photo-generated carriers get into the potential well 202 through lateral surfaces of second semiconductor region 106 .
- at least a portion of the photo-generated carriers directly pass through a bottom surface of the second semiconductor region 106 to reach the potential well 202 . This is possible because the second semiconductor region 106 is thin and the barrier between the second semiconductor region 106 and the potential well 202 is low (e.g., less than band gap of Ge).
- carrier recombination may take place in the second semiconductor region 106 .
- a thick first semiconductor region 104 may be used for increasing the quantum efficiency, while the photo-generated carriers are effectively transported to the potential well 202 for increasing the on/off signal modulation.
- the device In the absence of an exposure to light, the device would have a certain drain current (called herein I off ). However, when the device is exposed to light, the photo-generated carriers modulate the drain current (e.g., the drain current increases to I on ).
- FIG. 3 illustrates exemplary band diagrams in accordance with some embodiments. Although FIG. 3 is used to illustrate operational principles of the semiconductor optical sensor device, FIG. 3 and the described principles are not intended to limit the scope of claims.
- the band diagrams in FIG. 3 represent electron energy levels from the gate of the semiconductor optical sensor device to the substrate of the semiconductor optical sensor device.
- a GCMD can be represented as having a small capacitance and a large capacitance connected around a channel.
- the band diagram (a) represents that the device is in the off state.
- the band diagram (b) represents that the incident light is absorbed in the substrate region, and carriers are photo-generated in the small capacitance. There is a quasi-Fermi level split in the buried hole channel and substrate.
- the band diagram (c) represents that the photo-generated carriers from the low capacitance region are transferred to the large capacitance region (oxide-surface interface) automatically with a proper gate bias.
- the transferred photo-generated carriers in the oxide-surface interface reduce band bending between the source/drain and the buried hole channel, ultimately increasing the drain current.
- the band of the channel with incident light is similar to the band with a lower gate voltage, which is represented in the band diagram (d).
- FIGS. 4 A and 4 B are schematic diagrams illustrating a single channel configuration and a multi-channel configuration of a semiconductor optical sensor device.
- the schematic diagrams in FIGS. 4 A and 4 B are based on top-down views of the semiconductor optical sensor device. However, it should be noted that the schematic diagrams in FIGS. 4 A and 4 B are used to represent relative sizes and positions of various elements and that the schematic diagrams in FIGS. 4 A and 4 B are not cross-sectional views.
- FIG. 4 A is a schematic diagram illustrating a single channel configuration of a semiconductor optical sensor device in accordance with some embodiments.
- FIG. 4 A illustrates that the device has a gate 406 , a source 402 , and a drain 404 .
- the device also includes a channel 412 that extends from the source 402 to the drain 404 .
- the channel 412 is typically defined by the second semiconductor region.
- the shape of the channel 412 is determined by a pattern of ion implantation in forming the second semiconductor region.
- the source 402 has multiple contacts 408 with the channel 412 and the drain 404 has multiple contacts 408 with the channel 412 .
- FIG. 4 B is a schematic diagram illustrating a multi-channel configuration of a semiconductor optical sensor device in accordance with some embodiments.
- FIG. 4 B is similar to FIG. 4 A except that the device has multiple channels 414 between the source 402 and the drain 404 .
- the second semiconductor region defines multiple channels 414 between the source 402 and the drain 404 .
- Each channel 414 in FIG. 4 B connects a single contact 408 of the source 402 and a single contact 410 of the drain 404 .
- a width of the channel 414 in FIG. 4 B is less than a width of the channel 412 in FIG. 4 A .
- the reduced width of a channel is believed to facilitate a transfer of a photo-generated carrier to a large capacitance region (e.g., an interface of the second semiconductor region and the gate insulation layer) of the device.
- FIG. 5 is a partial cross-sectional view of semiconductor optical sensor devices in accordance with some embodiments.
- FIG. 5 illustrates that a plurality of semiconductor optical sensor devices (e.g., devices 502 - 1 and 502 - 2 ) are formed on a common substrate.
- the multiple devices form a sensor array.
- FIG. 5 illustrates two semiconductor optical sensor devices, the sensor array may include more than two semiconductor optical sensor devices.
- the sensor array includes a two-dimensional array of semiconductor optical sensor devices.
- FIG. 5 also illustrates that vias 506 are formed to connect the gate 112 , the source, and the drain of the devices 502 - 1 and 502 - 2 .
- the plurality of devices (e.g., devices 502 - 1 and 502 - 2 ) has the first semiconductor region 104 on a common plane.
- the first semiconductor region 104 of the plurality of devices is formed concurrently (e.g., using epitaxial growth of the first semiconductor region 104 ).
- the plurality of devices (e.g., devices 502 - 1 and 502 - 2 ) has the second semiconductor region 106 on a common plane.
- the second semiconductor region 106 of the plurality of devices is formed concurrently (e.g., using ion implantation).
- the plurality of devices (e.g., devices 502 - 1 and 502 - 2 ) has the third semiconductor region 108 on a common plane.
- the third semiconductor region 108 of the plurality of devices is formed concurrently (e.g., using epitaxial growth of germanium islands).
- the plurality of devices is separated by one or more trenches.
- the device 502 - 1 and the device 502 - 2 are separate by a trench.
- the one or more trenches are filled with an insulator.
- a trench is a shallow trench isolator.
- the plurality of devices is positioned on separate germanium islands formed on the common silicon substrate 102 .
- third semiconductor regions 108 e.g., germanium islands
- the rest of devices 502 - 1 and 502 - 2 are formed over the third semiconductor regions 108 .
- the sensor array includes a passivation layer over the plurality of devices.
- the passivation layer 504 is positioned over the devices 502 - 1 and 502 - 2 in FIG. 5 .
- the sensor array includes a passivation layer 504 between the plurality of devices.
- the passivation layer 504 is positioned between the devices 502 - 1 and 502 - 2 in FIG. 5 .
- FIG. 6 illustrates an exemplary sensor circuit in accordance with some embodiments.
- the sensor circuit includes a photo-sensing element 602 .
- the photo-sensing element 602 has a source terminal, a gate terminal, a drain terminal, and body terminal 605 .
- the sensor circuit also includes a selection transistor 604 having a source terminal, a gate terminal, and a drain terminal.
- the drain terminal of the selection transistor 604 is electrically coupled (e.g., at a point 606 ) with the source terminal of the photo-sensing element 602 .
- the source terminal of the selection transistor 604 is electrically coupled (e.g., at the point 606 ) with the drain terminal of the photo-sensing element 602 .
- the photo-sensing element is a GCMD (e.g., the device 100 , FIG. 1 A ).
- the source terminal or the drain terminal, of the photo-sensing element 602 that is not electrically coupled with the source terminal or the drain terminal of the selection transistor 604 is connected to a ground.
- V 2 is connected to a ground.
- the source terminal or the drain terminal, of the photo-sensing element 602 that is electrically coupled with the source terminal or the drain terminal of the selection transistor 604 is not connected to a ground.
- the point 606 is not connected to a ground.
- the source terminal or the drain terminal, of the photo-sensing element 602 that is electrically coupled with the source terminal or the drain terminal of the selection transistor 604 is electrically coupled with a first voltage source.
- V 2 is connected to the first voltage source.
- the first voltage source provides a first fixed voltage, such as a voltage that is distinct from the ground.
- the source terminal or the drain terminal, of the selection transistor 604 that is not electrically coupled with the source terminal or the drain terminal of the photo-sensing element 620 is electrically coupled with a second voltage source.
- V 1 is connected to the second voltage source.
- the second voltage source provides a second fixed voltage.
- the sensor circuit includes no more than two transistors, the two transistors including the selection transistor 604 . In some embodiments, the sensor circuit also includes a gate control transistor that is electrically coupled to the gate of the photo-sensing element.
- the sensor circuit includes no more than one transistor, the one transistor being the selection transistor 604 .
- the sensor circuit in FIG. 6 is called herein one-transistor modified active-pixel sensor (1T-MAPS), because the sensor circuit includes a single transistor and a modified active-pixel sensor.
- 1T-MAPS one-transistor modified active-pixel sensor
- 3T-APS three-transistor active-pixel sensor
- FIG. 7 A illustrates an exemplary 3T-APS circuit in accordance with some embodiments.
- the 3T-APS circuit includes a photo-sensing element (e.g., a photodiode) and three transistors: a reset transistor Mrst, a source-follower transistor Msf, and a select transistor Msel.
- a photo-sensing element e.g., a photodiode
- three transistors e.g., a reset transistor Mrst, a source-follower transistor Msf, and a select transistor Msel.
- the reset transistor Mrst works as a reset switch.
- Mrst receives a gate signal RST, which allows a reset voltage, Vrst, to be provided to the photo-sensing element to reset the photo-sensing element.
- the source-follower transistor Msf acts as a buffer.
- Msf receives an input (e.g., a voltage input) from the photo-sensing element, which allows a high voltage Vdd to be output to the source of the select transistor Msel.
- the select transistor Msel works as a readout switch. For example, Msel receives a row selection signal ROW, which allows an output from the source-follower transistor Msf to be provided to a column line.
- FIG. 7 B illustrates an exemplary 1T-MAPS circuit in accordance with some embodiments.
- the 1T-MAPS circuit includes one photo-sensing element (e.g., GCMD) and one transistor, namely a select transistor Msel.
- GCMD photo-sensing element
- Msel select transistor
- the select transistor Msel receives a row selection signal ROW, which allows a current from the column line to flow to an input of the photo-sensing element.
- the row selection signal ROW provided to the select transistor Msel, allows a current from the photo-sensing element to flow to the column line.
- the column line is set to a fixed voltage.
- the 1T-MAPS circuit does not require a reset switch, because photo-generated carriers stored in the GCMD dissipate in a short period of time (e.g., 0.1 second).
- a 1T-MAPS circuit is more cost advantageous than a 3T-APS circuit made of a same material.
- more 1T-MAPS circuits can be placed on a same area of a die than 3T-APS circuits, thereby increasing a number of pixels on the die.
- FIGS. 8 A- 8 H illustrate exemplary sensor circuits in accordance with some embodiments.
- a switch symbol represents a select transistor.
- FIGS. 8 A- 8 D illustrate exemplary sensor circuits that include a PMOS-type GCMD.
- the gate of the GCMD is connected to a ground V G
- the drain of the GCMD is connected to a low voltage source V 1 (e.g., ground).
- the source of the GCMD is connected to a switch (or a select transistor), which is connected to a fixed voltage, V constant2 .
- the body is connected to a high voltage source VDD.
- the gate of the GCMD is connected to a fixed voltage V constant1
- the drain of the GCMD is connected to a low voltage source V 1 (e.g., ground).
- the source of the GCMD is connected to a switch (or a select transistor), which is connected to a fixed voltage, V constant2 .
- the body is connected to a high voltage source V DD .
- the gate of the GCMD is connected to a fixed voltage V constant1
- the source of the GCMD is connected to a high voltage source V DD .
- the drain of the GCMD is connected to a switch (or a select transistor), which is connected to a fixed voltage, V constant2 .
- the body is connected to a high voltage source V DD2 .
- the gate of the GCMD is connected to a fixed voltage V constant1
- the source of the GCMD is connected to a high voltage source V DD .
- the drain of the GCMD is connected to a switch (or a select transistor), which is connected to a variable voltage, V variable .
- the body is connected to a high voltage source V DD2 .
- FIGS. 8 E- 8 H illustrate exemplary sensor circuits that include NMOS type GCMD.
- the gate and the drain of the GCMD are connected to a high voltage source V DD .
- the source of the GCMD is connected to a switch (or a select transistor), which is connected to a fixed voltage, V constant2 .
- the body is connected to a ground.
- the gate of the GCMD is connected to a fixed voltage V constant1
- the drain of the GCMD is connected to a high voltage source V DD .
- the source of the GCMD is connected to a switch (or a select transistor), which is connected to a fixed voltage, V constant2 .
- the body is connected to a ground.
- the gate of the GCMD is connected to a fixed voltage V constant1 , and the source of the GCMD is connected to a ground.
- the drain of the GCMD is connected to a switch (or a select transistor), which is connected to a fixed voltage, V constant2 .
- the body is connected to a ground.
- the gate of the GCMD is connected to a fixed voltage V constant1 , and the source of the GCMD is connected to a ground.
- the drain of the GCMD is connected to a switch (or a select transistor), which is connected to a variable voltage, V variable .
- the body is connected to a ground.
- the drain current in the GCMD changes depending on whether the GCMD is exposed to light.
- the GCMD is modeled as a current source that provides Ion when the GCMD is exposed to light and provide I off when the GCMD is not exposed to light.
- FIGS. 9 A- 9 C illustrate exemplary converter circuits in accordance with some embodiments.
- FIG. 9 A illustrates an exemplary converter circuit 902 in accordance with some embodiments.
- the converter circuit 902 includes a first transimpedance amplifier 904 (e.g., an operational amplifier) that has an input terminal (e.g., an input terminal receiving I GC MD from the photo-sensing element, such as the GCMD) electrically coupled with the source terminal or the drain terminal of the selection transistor of a first sensor circuit (e.g., the sensor circuit in FIG. 6 ), that is not electrically coupled with the source terminal or the drain terminal of the photo-sensing element (e.g., the terminal having a voltage V 1 in FIG. 6 ).
- the first transimpedance amplifier 904 is configured to convert a current input (e.g., I GCMD ) from the photo-sensing element into a voltage output (e.g., V tamp ).
- the converter circuit 902 also includes a differential amplifier 906 having two input terminals.
- a first input terminal of the two input terminals is electrically coupled with the voltage output (e.g., V tamp ) of the first transimpedance amplifier 904 and a second input terminal of the two input terminals is electrically coupled with a voltage source that is configured to provide a voltage (e.g., V BASE ) corresponding to a base current provided by the photo-sensing element.
- the differential amplifier is configured to output a voltage (e.g., V damp ) based on a voltage difference between the voltage output (e.g., V tamp ) and the voltage provided by the voltage source (e.g., V BASE ).
- the differential amplifier 906 includes an operational amplifier.
- the differential amplifier 906 includes a transistor long tailed pair.
- the converter circuit 922 includes an analog-to-digital converter 908 electrically coupled to an output of the differential amplifier 906 (e.g., V tamp ), the analog-to-digital converter configured to convert the output (e.g., a voltage output) of the differential amplifier 906 (e.g., V tamp ) into a digital signal.
- an analog-to-digital converter 908 electrically coupled to an output of the differential amplifier 906 (e.g., V tamp ), the analog-to-digital converter configured to convert the output (e.g., a voltage output) of the differential amplifier 906 (e.g., V tamp ) into a digital signal.
- FIG. 9 B illustrates an exemplary converter circuit 912 in accordance with some embodiments.
- the converter circuit 912 is similar to the converter circuit 902 illustrated in FIG. 9 A .
- Some of the features described with respect to FIG. 9 A are applicable to the converter circuit 912 .
- the description of such features is not repeated herein.
- FIG. 9 B illustrates that, in some embodiments, the first transimpedance amplifier 904 in the converter circuit 912 includes an operational amplifier 910 .
- the operational amplifier 910 has a non-inverting input terminal that is electrically coupled with the source terminal or the drain terminal of the selection transistor of the first sensor circuit (E.g., the terminal having a voltage V 1 in FIG. 6 ).
- the operational amplifier 910 also has an inverting input terminal that is electrically coupled with a reference voltage source that provides a reference voltage V REF .
- the operational amplifier 910 has an output terminal, and a resistor with a resistance value R is electrically coupled to the non-inverting input terminal on a first end of the resistor and to the output terminal on the second end, opposite to the first end, of the resistor.
- V tamp the voltage output V tamp is determined as follows:
- V tamp V REF +R ⁇ I GCMD
- the current from the GCMD can be modeled as follows:
- I GCMD I off (no light)
- I GCMD I ⁇ +I off (light)
- the base current corresponds to a current provided by the photo-sensing element while the photo-sensing element receives substantially no light (e.g., I off ).
- I off is converted by the first transimpedance amplifier 904 , a corresponding voltage V BASE is determined as follows:
- V BASE V REF +R ⁇ I off
- V tamp ⁇ V BASE R ⁇ I ⁇
- the voltage output V damp of the differential amplifier 906 is as follows:
- V damp A ⁇ R ⁇ I ⁇
- A is a differential gain of the differential amplifier 906 .
- the differential gain is one of: one, two, three, five, ten, twenty, fifty, and one hundred.
- FIG. 9 B also illustrates that, in some embodiments, the voltage source is a digital-to-analog converter (DAC) 916 .
- the DAC 916 is configured to provide V BASE .
- FIG. 9 C illustrates an exemplary converter circuit 922 in accordance with some embodiments.
- the converter circuit 922 is similar to the converter circuit 902 illustrated in FIG. 9 A and the converter circuit 912 illustrated in FIG. 9 B . Some of the features described with respect to FIGS. 9 A and 9 B are applicable to the converter circuit 922 .
- the converter circuit 922 includes the digital-to-analog converter 916 .
- the first transimpedance amplifier 904 includes an operational amplifier 910 . For brevity, the description of such features is not repeated herein.
- FIG. 9 C illustrates that the voltage source (that provides V BASE ) is a second transimpedance amplifier 914 having an input terminal electrically coupled with a second sensor circuit that is distinct from the first sensor circuit.
- the input terminal of the second transimpedance amplifier 914 is electrically coupled with the source terminal or the drain terminal of the selection transistor of the second sensor circuit.
- the photo-sensing element of the second sensor circuit is optically covered so that the photo-sensing element of the second sensor circuit is prevented from receiving light.
- the second sensor circuit provides T off to the second transimpedance amplifier 914 .
- the second transimpedance amplifier 914 converts I off to V BASE .
- the second transimpedance amplifier 914 includes an operational amplifier.
- the first transimpedance amplifier 904 is configured to electrically couple with a respective sensor circuit of a plurality of sensor circuits through a multiplexer.
- the converter circuit 922 is coupled to a multiplexer 916 .
- the multiplexer receives a column address to select one of a plurality of column lines. Each column line is connected to multiple sensor circuits, each having a selection transistor that receives a ROW signal. Thus, based on a column address and a ROW signal, one sensor circuit in a two-dimensional array of sensor circuits is selected, and a current output from the selected sensor circuit is provided to the first transimpedance amplifier 904 through the multiplexer 916 .
- FIGS. 9 A- 9 C illustrate selected embodiments, it should be noted that a converter circuit may include a subset of the features described in FIGS. 9 A- 9 C (e.g., the converter circuit 922 may be coupled with the multiplexer 916 without having the second transimpedance amplifier 914 ). In some embodiments, a converter circuit includes additional features not described with respect to FIGS. 9 A- 9 C .
- FIG. 10 illustrates an exemplary image sensor device in accordance with some embodiments.
- the image sensor device includes an array of sensors.
- a respective sensor in the array of sensors includes a sensor circuit (e.g., FIGS. 8 A- 8 H ).
- the image sensor device includes a converter circuit (e.g., FIGS. 9 A- 9 C ).
- the array of sensors includes multiple rows of sensors (e.g., at least two rows of sensors are illustrated in FIG. 10 ).
- gate terminals of selection transistors are electrically coupled to a common selection line.
- gate terminals of sensor circuits in a top row are electrically coupled to a same signal line.
- the array of sensors includes multiple columns of sensors (e.g., at least three columns of sensors are illustrated in FIG. 10 ).
- one of source terminals or drain terminals of selection transistors i.e., either the source terminals of the selection transistors or the drain terminals of the selection transistors
- a common column line For example, as shown in FIG. 10 , the drain terminals of the selection transistors in a left column of sensors are electrically coupled to a same column line.
- FIGS. 11 A- 11 E illustrate an exemplary method for making a semiconductor optical sensor device in accordance with some embodiments.
- FIG. 11 A illustrates forming the semiconductor optical sensor device includes forming a third semiconductor region 108 on a silicon substrate 102 .
- the third semiconductor region 108 is epitaxially grown on the substrate 102 .
- FIG. 11 B illustrates forming a first semiconductor region 104 , above the silicon substrate 102 , doped with a dopant of a first type.
- the first semiconductor region 104 is formed by epitaxially growing the first semiconductor region 104 .
- the first semiconductor region 104 is doped in-situ with the dopant of the first type (e.g., n-type) while the first semiconductor region 104 is grown.
- the dopant of the first type e.g., n-type
- the first semiconductor region 104 is doped with the dopant of the first type (e.g., n-type) using an ion implantation process or a gas phase diffusion process. In some embodiments, the first semiconductor region 104 is doped with the dopant of the first type (e.g., n-type) using an ion implantation process. In some embodiments, the first semiconductor region 104 is doped with the dopant of the first type (e.g., n-type) using a gas phase diffusion process.
- FIG. 11 C illustrates forming a second semiconductor region 106 , above the silicon substrate 102 , doped with a dopant of a second type.
- the second semiconductor region 106 is positioned above the first semiconductor region 104 .
- the first type e.g., n-type
- the second type e.g., p-type
- the second semiconductor region 106 is formed by epitaxially growing the second semiconductor region 106 .
- the second semiconductor region 106 is doped in-situ with the dopant of the second type (e.g., p-type, and in particular, p+) while the second semiconductor region 106 is grown.
- the dopant of the second type e.g., p-type, and in particular, p+
- the second semiconductor region 106 is doped with the dopant of the second type (e.g., p-type, and in particular, p+) using an ion implantation process or a gas phase diffusion process. In some embodiments, the second semiconductor region 106 is doped with the dopant of the second type (e.g., p-type, and in particular, p+) using an ion implantation process. In some embodiments, the second semiconductor region 106 is doped with the dopant of the second type (e.g., p-type, and in particular, p+) using a gas phase diffusion process.
- the dopant of the second type e.g., p-type, and in particular, p+
- the second semiconductor region 106 is doped with the dopant of the second type (e.g., p-type, and in particular, p+) using an ion implantation process after the first semiconductor region 104 is doped with the dopant of the first type using an ion implantation process or a gas phase diffusion process. In some embodiments, the second semiconductor region 106 is doped with the dopant of the second type (e.g., p-type, and in particular, p+) using an ion implantation process after the first semiconductor region 104 is doped with the dopant of the first type using an ion implantation process.
- the dopant of the second type e.g., p-type, and in particular, p+
- the second semiconductor region 106 is doped with the dopant of the second type (e.g., p-type, and in particular, p+) using an ion implantation process after the first semiconductor region 104 is doped with the dopant of the first type using a gas phase diffusion process.
- the dopant of the second type e.g., p-type, and in particular, p+
- FIG. 11 D illustrates forming a gate insulation layer 110 above the second semiconductor region 106 .
- One or more portions of the second semiconductor region 106 are exposed from the gate insulation layer 110 to define a source and a drain.
- the gate insulation layer 110 is pattern etched (e.g., using a mask) to expose the source and the drain.
- the second semiconductor region 106 has a top surface that faces the gate insulation layer 110 .
- the second semiconductor region 106 has a bottom surface that is opposite to the top surface of the second semiconductor region 106 .
- the second semiconductor region 106 has an upper portion that includes the top surface of the second semiconductor region 106 .
- the second semiconductor region 106 has a lower portion that includes the bottom surface of the second semiconductor region 106 and is mutually exclusive with the upper portion.
- the first semiconductor region 104 is in contact with both the upper portion and the lower portion of the second semiconductor region 106 .
- the first semiconductor region 104 is in contact with the upper portion of the second semiconductor region 106 at least at a location positioned under the gate 112 .
- FIG. 11 E illustrates forming a gate 112 positioned above the gate insulation layer 110 .
- a method of forming a sensor array includes concurrently forming a plurality of devices on a common silicon substrate. For example, third semiconductor regions of multiple devices may be formed concurrently in a single epitaxial growth process. Subsequently, first semiconductor regions of the multiple devices may be formed concurrently in a single epitaxial growth process. Thereafter, second semiconductor regions of the multiple devices may be formed concurrently in a single ion implantation process. Similarly, gate insulation layers of the multiple devices may be formed concurrently, and gates of the multiple devices may be formed concurrently.
- a method for sensing light includes exposing a photo-sensing element (e.g., GCMD in FIG. 6 ) to the light.
- a photo-sensing element e.g., GCMD in FIG. 6
- the method also includes providing a fixed voltage to the source terminal of the photo-sensing element (e.g., by applying a fixed voltage V 1 and applying V R to the selection transistor 604 ( FIG. 6 ). Based on an intensity of light on the GCMD, a drain current of the GCMD changes.
- the method includes determining an intensity of the light based on the drain current of the photo-sensing element (e.g., GCMD).
- a change in the drain current indicates whether light is detected by the photo-sensing element.
- measuring the drain current includes converting the drain current to a voltage signal (e.g., converting the drain current I GCMD to V tamp , FIG. 9 A ).
- converting the drain current to the voltage signal includes using a transimpedance amplifier (e.g., transimpedance amplifier 904 , FIG. 9 A ) to convert the drain current to the voltage signal.
- a transimpedance amplifier e.g., transimpedance amplifier 904 , FIG. 9 A
- measuring the drain current includes using any converter circuit described herein (e.g., FIGS. 9 A- 9 C ).
- the method includes activating the selection transistor of the sensor circuit (e.g., the selection transistor 604 , FIG. 6 ). Activating the selection transistor allows a drain current to flow through the selection transistor, thereby allowing a measurement of the drain current.
- the fixed voltage is provided to the source terminal of the photo-sensing element prior to exposing the photo-sensing element to light.
- the selection transistor 604 is activated before exposing the photo-sensing element 602 to light.
- the fixed voltage is provided to the source terminal of the photo-sensing element subsequent to exposing the photo-sensing element to light.
- the selection transistor 604 is activated after exposing the photo-sensing element 602 to light.
- a method for detecting an optical image includes exposing any array of sensors described herein (e.g., FIG. 10 ) to a pattern of light.
- the method also includes, for a photo-sensing element of a respective sensor in the array of sensors, providing a respective voltage to the source terminal of the photo-sensing element of the respective image sensor.
- a selection transistor e.g., the selection transistor 604 , FIG. 6
- the respective sensor is activated to provide the respective voltage, thereby allowing a measurement of a drain current of the respective sensor.
- the method further includes measuring a drain current of the photo-sensing element (e.g., the photo-sensing element 602 ).
- the source terminals of the photo-sensing elements in the array of sensors concurrently receive respective voltages.
- respective voltages are concurrently applied to multiple photo-sensing elements (e.g., photo-sensing elements in a same row) for a concurrent reading of the multiple photo-sensing elements.
- the source terminals of the photo-sensing elements in the array of sensors sequentially receive respective voltages.
- respective voltages are sequentially applied to multiple photo-sensing elements (e.g., photo-sensing elements in a same column) for sequential reading of the multiple photo-sensing elements.
- the source terminals of photo-sensing elements in the array of sensors receive a same voltage.
- the drain currents of the photo-sensing elements in the array of sensors are measured in batches.
- the drain currents of photo-sensing elements in a same row are measured in a batch (e.g., as a set).
- the drain currents of the photo-sensing elements in the array of sensors are concurrently measured.
- the drain currents of the photo-sensing elements in a same row are concurrently measured.
- the drain currents of the photo-sensing elements in the array of sensors are sequentially measured. For example, the drain currents of the photo-sensing elements in a same column are concurrently measured.
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Abstract
A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.
Description
- This application is a continuation application of U.S. patent application Ser. No. 16/167,241, filed Oct. 22, 2018, which is a continuation application of U.S. patent application Ser. No. 14/967,262, filed Dec. 11, 2015, now U.S. Pat. No. 10,109,662, issued on Oct. 23, 2018, which is a continuation application of the international application number PCT/US2014/043421, filed Jun. 20, 2014, which claims priority to U.S. Provisional Patent Application Ser. No. 61/837,557, filed Jun. 20, 2013 and U.S. Provisional Patent Application Ser. No. 62/002,045, filed May 22, 2014. All of these applications are incorporated by reference herein in their entireties.
- This application relates generally to semiconductor devices and circuits. More particularly, the disclosed embodiments relate to semiconductor devices and circuits for sensing short-wave infrared light.
- Digital image sensors have gained significant popularity in recent years. For example, many digital cameras, mobile computers, and mobile phones include digital image sensors for capturing images.
- However, traditional digital image sensors, such as complementary metal-oxide-semiconductor (CMOS) sensors, utilize photodiodes and suffer from dark current associated with photodiodes. The dark current contributes to increased shot noise, which is undesirable.
- Although a charge modulation device (CMD) has been proposed as a solution to the dark current problem, charge modulation devices suffer from a small change in on/off signals. In addition, charge modulation devices are limited with a trade-off of a quantum efficiency and a weak channel modulation.
- Thus, there is a need for an optical sensor that has a low dark current, a high quantum efficiency, and a strong channel modulation.
- A number of embodiments (e.g., of server systems, client systems or devices, and methods of operating such systems or devices) that overcome the limitations and disadvantages described above are presented in more detail below. These embodiments provide devices, circuits, and methods for making and using devices, for sensing infrared light.
- As described in more detail below, some embodiments involve a device for sensing light. The device includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region; and the first type is distinct from the second type. The device includes a gate insulation layer positioned above the second semiconductor region; a gate positioned above the gate insulation layer; a source electrically coupled with the second semiconductor region; and a drain electrically coupled with the second semiconductor region. The second semiconductor region has a top surface that is positioned toward the gate insulation layer, and the second semiconductor region has a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region. The second semiconductor region also has a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region. The first semiconductor region is in contact with the upper portion of the second semiconductor region at least at a location positioned under the gate.
- In some embodiments, the first type is an n-type and the second type is a p-type.
- In some embodiments, the first type is a p-type and the second type is an n-type.
- In some embodiments, the second semiconductor region has a first lateral surface that extends from the source to the drain and is distinct from the top surface and the bottom surface. The second semiconductor region has a second lateral surface that extends from the source to the drain and is distinct from the top surface and the bottom surface. The first semiconductor region is in contact with the upper portion of the second semiconductor region through a portion of the first lateral surface. The first semiconductor region is in contact with the upper portion of the second semiconductor region through a portion of the second lateral surface.
- In some embodiments, the first semiconductor region includes germanium.
- In some embodiments, the second semiconductor region includes germanium.
- In some embodiments, the gate insulation layer includes an oxide layer.
- In some embodiments, the device includes a substrate insulation layer positioned below the first semiconductor region. The substrate insulation layer includes one or more of: SiO2, GeOx, ZrOx, HfOx, SixNy, SixOyNz, TaxOy, SrxOy and AlxOy.
- In some embodiments, the device includes a third semiconductor region that includes germanium doped with a dopant of the second type. The third semiconductor region is positioned below the first semiconductor region.
- In some embodiments, a doping concentration of the dopant of the second type in the second semiconductor region is higher than a doping concentration of the dopant of the second type in the third semiconductor region.
- In some embodiments, the device includes a silicon substrate.
- In some embodiments, the gate includes one or more of: polygermanium, amorphous germanium, polysilicon, amorphous silicon, silicon carbide, and metal.
- In some embodiments, the second semiconductor region extends from the source to the drain.
- In some embodiments, the first semiconductor region extends from the source to the drain.
- In some embodiments, the gate insulation layer extends from the source to the drain.
- In some embodiments, the second semiconductor region defines multiple channels between the source and the drain.
- In some embodiments, the second semiconductor region has a thickness less than 100 nm.
- In some embodiments, the first semiconductor region has a thickness less than 1000 nm.
- In accordance with some embodiments, a sensor array includes a plurality of devices formed on a common silicon substrate, wherein each device of the plurality of devices corresponds to any of the above-described devices.
- In some embodiments, the plurality of devices has the first semiconductor region on a common plane.
- In some embodiments, the plurality of devices has the second semiconductor region on a common plane.
- In some embodiments, the plurality of devices has the third semiconductor region on a common plane.
- In some embodiments, the plurality of devices is separated by one or more trenches.
- In some embodiments, the plurality of devices is positioned on separate germanium islands formed on the common silicon substrate.
- In some embodiments, the sensor array includes a passivation layer over the plurality of devices.
- In some embodiments, the sensor array includes a passivation layer between the plurality of devices.
- In accordance with some embodiments, a method of forming a device for sensing light includes forming a first semiconductor region, above a silicon substrate, doped with a dopant of a first type and forming a second semiconductor region, above the silicon substrate, doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The first type is distinct from the second type. The method also includes forming a gate insulation layer above the second semiconductor region. One or more portions of the second semiconductor region are exposed from the gate insulation layer to define a source and a drain. The second semiconductor region has a top surface that faces the gate insulation layer. The second semiconductor region has a bottom surface that is opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region. The second semiconductor region has a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region. The first semiconductor region is in contact with the upper portion of the second semiconductor region at least at a location positioned under the gate. The method further includes forming a gate positioned above the gate insulation layer.
- In some embodiments, the first semiconductor region is formed by epitaxially growing the first semiconductor region.
- In some embodiments, the first semiconductor region is doped in-situ with the dopant of the first type while the first semiconductor region is grown.
- In some embodiments, the first semiconductor region is doped with the dopant of the first type using an ion implantation process or a gas phase diffusion process.
- In some embodiments, the second semiconductor region is formed by epitaxially growing the second semiconductor region.
- In some embodiments, the second semiconductor region is doped in-situ with the dopant of the second type while the second semiconductor region is grown.
- In some embodiments, the second semiconductor region is doped with the dopant of the second type using an ion implantation process or a gas phase diffusion process.
- In some embodiments, the second semiconductor region is doped with the dopant of the second type using an ion implantation process after the first semiconductor region is doped with the dopant of the first type using an ion implantation process or a gas phase diffusion process.
- In accordance with some embodiments, a method of forming a sensor array includes concurrently forming a plurality of devices on a common silicon substrate using any of the above-described methods.
- In accordance with some embodiments, a sensor circuit includes a photo-sensing element, the photo-sensing element having a source terminal, a gate terminal, a drain terminal, and a body terminal. The sensor circuit also includes a selection transistor having a source terminal, a gate terminal, and a drain terminal. The drain terminal of the selection transistor is electrically coupled with the source terminal of the photo-sensing element or the source terminal of the selection transistor is electrically coupled with the drain terminal of the photo-sensing element.
- In some embodiments, the photo-sensing element is any of the above-described devices.
- In some embodiments, the source terminal or the drain terminal, of the photo-sensing element, that is not electrically coupled with the source terminal or the drain terminal of the selection transistor is connected to a ground.
- In some embodiments, the source terminal or the drain terminal, of the photo-sensing element, that is electrically coupled with the source terminal or the drain terminal of the selection transistor is not connected to a ground.
- In some embodiments, the source terminal or the drain terminal, of the photo-sensing element, that is electrically coupled with the source terminal or the drain terminal of the selection transistor is electrically coupled with a voltage source.
- In some embodiments, the voltage source provides a fixed voltage.
- In some embodiments, the sensor circuit includes no more than two transistors, the two transistors including the selection transistor.
- In some embodiments, the sensor circuit includes no more than one transistor, the one transistor being the selection transistor.
- In accordance with some embodiments, a converter circuit includes a first transimpedance amplifier having an input terminal electrically coupled with the source terminal or the drain terminal, of the selection transistor of a first sensor circuit that corresponds to any of the above-described sensor circuits, that is not electrically coupled with the source terminal or the drain terminal of the photo-sensing element. The first transimpedance amplifier is configured to convert a current input from the photo-sensing element into a voltage output. The converter circuit also includes a differential amplifier having two input terminals, a first input terminal of the two input terminals electrically coupled with the voltage output of the first transimpedance amplifier and a second input terminal of the two input terminals electrically coupled with a voltage source that is configured to provide a voltage corresponding to a base current provided by the photo-sensing element. The differential amplifier is configured to output a voltage based on a voltage difference between the voltage output and the voltage provided by the voltage source.
- In some embodiments, the first transimpedance amplifier includes an operational amplifier.
- In some embodiments, the base current corresponds to a current provided by the photo-sensing element while the photo-sensing element receives substantially no light.
- In some embodiments, the voltage source is a second transimpedance amplifier having an input terminal electrically coupled with a second sensor circuit that corresponds to any of the above-described sensor circuits and is distinct from the first sensor circuit.
- In some embodiments, the input terminal of the second transimpedance amplifier is electrically coupled with the source terminal or the drain terminal of the selection transistor of the second sensor circuit.
- In some embodiments, the second transimpedance amplifier includes an operational amplifier.
- In some embodiments, the photo-sensing element of the second sensor circuit is optically covered so that the photo-sensing element of the second sensor circuit is prevented from receiving light.
- In some embodiments, the voltage source is a digital-to-analog converter.
- In some embodiments, the converter circuit includes an analog-to-digital converter electrically coupled to an output of the differential amplifier, the analog-to-digital converter configured to convert the output of the differential amplifier into a digital signal.
- In some embodiments, the first transimpedance amplifier is configured to electrically couple with a respective sensor circuit of a plurality of sensor circuits through a multiplexer.
- In accordance with some embodiments, an image sensor device includes an array of sensors. A respective sensor in the array of sensors includes any of the above-described sensor circuits.
- In some embodiments, the image sensor device includes any of the above-described converter circuits.
- In some embodiments, the array of sensors includes multiple rows of sensors; and, for sensors in a respective row, gate terminals of selection transistors are electrically coupled to a common selection line.
- In some embodiments, the array of sensors includes multiple columns of sensors; and, for sensors in a respective column, one of source terminals or drain terminals of selection transistors are electrically coupled to a common column line.
- In accordance with some embodiments, a method includes exposing the photo-sensing element of any of the above-described sensor circuits. The method also includes providing a fixed voltage to the source terminal of the photo-sensing element; and measuring a drain current of the photo-sensing element.
- In some embodiments, the method includes determining an intensity of the light based on the drain current of the photo-sensing element.
- In some embodiments, measuring the drain current includes converting the drain current to a voltage signal.
- In some embodiments, converting the drain current to the voltage signal includes using a transimpedance amplifier to convert the drain current to the voltage signal.
- In some embodiments, measuring the drain current includes using any of the above-described converter circuits.
- In some embodiments, the method includes activating the selection transistor of the sensor circuit.
- In some embodiments, the fixed voltage is provided to the source terminal of the photo-sensing element prior to exposing the photo-sensing element to light.
- In some embodiments, the fixed voltage is provided to the source terminal of the photo-sensing element subsequent to exposing the photo-sensing element to light.
- In accordance with some embodiments, a method includes exposing the array of sensors of any of the above-described image sensor devices to a pattern of light. The method also includes, for a photo-sensing element of a respective sensor in the array of sensors, providing a respective voltage to the source terminal of the photo-sensing element of the respective sensor; and measuring a drain current of the photo-sensing element.
- In some embodiments, the source terminals of the photo-sensing elements in the array of sensors concurrently receive respective voltages.
- In some embodiments, the source terminals of the photo-sensing elements in the array of sensors sequentially receive respective voltages.
- In some embodiments, the source terminals of photo-sensing elements in the array of sensors receive a same voltage.
- In some embodiments, the drain currents of the photo-sensing elements in the array of sensors are measured in batches.
- In some embodiments, the drain currents of the photo-sensing elements in the array of sensors are concurrently measured.
- In some embodiments, the drain currents of the photo-sensing elements in the array of sensors are sequentially measured.
- For a better understanding of the aforementioned aspects as well as additional aspects and embodiments thereof, reference should be made to the Description of Embodiments below, in conjunction with the following drawings.
-
FIG. 1A is a partial cross-sectional view of a semiconductor optical sensor device in accordance with some embodiments. -
FIG. 1B is a partial cross-sectional view of the semiconductor optical sensor device illustrated inFIG. 1A , in accordance with some embodiments. -
FIG. 2A is a schematic diagram illustrating an operation of a semiconductor optical sensor device in accordance with some embodiments. -
FIG. 2B is a schematic diagram illustrating the operation of the semiconductor optical sensor device illustrated inFIG. 2A , in accordance with some embodiments. -
FIG. 3 illustrates exemplary band diagrams in accordance with some embodiments. -
FIG. 4A is a schematic diagram illustrating a single channel configuration of a semiconductor optical sensor device in accordance with some embodiments. -
FIG. 4B is a schematic diagram illustrating a multi-channel configuration of a semiconductor optical sensor device in accordance with some embodiments. -
FIG. 5 is a partial cross-sectional view of semiconductor optical sensor devices in accordance with some embodiments. -
FIG. 6 illustrates an exemplary sensor circuit in accordance with some embodiments. -
FIG. 7A illustrates an exemplary 3T-APS circuit in accordance with some embodiments. -
FIG. 7B illustrates an exemplary 1T-MAPS circuit in accordance with some embodiments. -
FIGS. 8A-8H illustrate exemplary sensor circuits in accordance with some embodiments. -
FIGS. 9A-9C illustrate exemplary converter circuits in accordance with some embodiments. -
FIG. 10 illustrates an exemplary image sensor device in accordance with some embodiments. -
FIGS. 11A-11E illustrate an exemplary method for making a semiconductor optical sensor device in accordance with some embodiments. - Like reference numerals refer to corresponding parts throughout the figures.
- Unless noted otherwise, the figures are not drawn to scale.
- As explained above, traditional optical sensors, such as complementary metal-oxide-semiconductor (CMOS) sensors and charge modulation devices, suffer from dark current and a trade-off between a quantum efficiency and a weak channel modulation.
- In addition, the problems are exacerbated when short-wave infrared light is to be detected. Traditional sensors made of silicon are not adequate for sensing and imaging short-wave infrared light (e.g., light within a wavelength range of 1400 nm to 3000 mm), because silicon is deemed to be transparent to light having a wavelength longer than 1100 nm (which corresponds with the bandgap of silicon).
- Infrared sensors made of Indium Gallium Arsenide (InGaAs) and Germanium (Ge) suffer from high dark current. Many InGaAs and sensors are cooled to operate in a low temperature (e.g., −70° C.). However, cooling is disadvantageous for many reasons, such as cost of the cooling unit, an increased size of the device due to the cooling unit, an increased operation time for cooling the device, and increased power consumption for cooling the device.
- Devices, circuits, and methods that address the above problems are described herein. By providing a structure that allows transport of photo-generated carriers toward a gate insulation layer, the charge modulation effect is significantly increased compared to conventional charge modulation devices while maintaining a high quantum efficiency. The structures described herein when implemented using material that are better suited for detecting short-wave infrared light than silicon (e.g., germanium) can provide improved performance (e.g., lower noise, higher quantum efficiency, and higher on/off signal ratio) in detecting short-wave infrared light.
- For these reasons, the structures described herein are particularly useful for detecting short-wave infrared light. However, such structures may be used for detecting visible light.
- Reference will be made to certain embodiments, examples of which are illustrated in the accompanying drawings. While the underlying principles will be described in conjunction with the embodiments, it will be understood that it is not intended to limit the scope of claims to these particular embodiments alone. On the contrary, the claims are intended to cover alternatives, modifications and equivalents that are within the scope of the claims.
- Moreover, in the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the invention may be practiced without these particular details. In other instances, methods, procedures, components, and networks that are well-known to those of ordinary skill in the art are not described in detail to avoid obscuring aspects of the underlying principles.
- It will also be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms.
- These terms are only used to distinguish one element from another. For example, a first semiconductor region could be termed a second semiconductor region, and, similarly, a second semiconductor region could be termed a first semiconductor region, without departing from the scope of the claims. The first semiconductor and the second semiconductor region are both semiconductor regions, but they are not the same semiconductor regions.
- The terminology used in the description of the embodiments herein is for the purpose of describing particular embodiments only and is not intended to limiting of the scope of claims. As used in the description and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
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FIG. 1A is a partial cross-sectional view of a semiconductoroptical sensor device 100 in accordance with some embodiments. - In some embodiments, the
device 100 is called a gate-controlled charge modulated device (GCMD). - The
device 100 includes afirst semiconductor region 104 doped with a dopant of a first type (e.g., an n-type semiconductor, such as phosphorus or arsenic) and asecond semiconductor region 106 doped with a dopant of a second type (e.g., a high concentration of a p-type semiconductor, such as boron, which is often indicated using a p+ symbol). Thesecond semiconductor region 106 is positioned above thefirst semiconductor region 104. The first type (e.g., n-type) is distinct from the second type (e.g., p-type). In some embodiments, thesecond semiconductor region 106 is positioned over thefirst semiconductor region 104. - The device includes a
gate insulation layer 110 positioned above thesecond semiconductor region 106 and agate 112 positioned above thegate insulation layer 110. In some embodiments, thegate insulation layer 110 is positioned over thesecond semiconductor region 106. In some embodiments, thegate insulation layer 110 is in contact with thesecond semiconductor region 106. In some embodiments, thegate 112 positioned over thegate insulation layer 110. In some embodiments, thegate 112 is in contact with thegate insulation layer 110. - The device also includes a
source 114 electrically coupled with thesecond semiconductor region 106 and adrain 116 electrically coupled with thesecond semiconductor region 106. - The
second semiconductor region 106 has atop surface 120 that is positioned toward thegate insulation layer 110. Thesecond semiconductor region 106 also has abottom surface 122 that is positioned opposite to thetop surface 120 of thesecond semiconductor region 106. Thesecond semiconductor region 106 has anupper portion 124 that includes thetop surface 120 of thesecond semiconductor region 106. Thesecond semiconductor region 106 also has alower portion 126 that includes thebottom surface 122 of thesecond semiconductor region 106. Thelower portion 126 is mutually exclusive with theupper portion 124. As used herein, theupper portion 124 and thelower portion 126 refer to different portions of thesecond semiconductor region 106. Thus, in some embodiments, there is no physical separation of theupper portion 124 and thelower portion 126. In some embodiments, thelower portion 126 refers to a portion of thesecond semiconductor region 106 that is not theupper portion 124. In some embodiments, theupper portion 124 has a thickness less than 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm. In some embodiments, theupper portion 124 has a uniform thickness from thesource 114 to thedrain 116. In some embodiments, theupper portion 124 and thelower portion 126 have a same thickness at a horizontal location directly below thegate 112. - In some embodiments, the first type is an n-type and the second type is a p-type. For example, the first semiconductor region is doped with an n-type semiconductor and the
source 114, thedrain 116, and a channel between thesource 114 and thedrain 116 are doped with a p-type semiconductor, which is called a PMOS structure. - In some embodiments, the first type is a p-type and the second type is an n-type. For example, the first semiconductor region is doped with a p-type semiconductor and the
source 114, thedrain 116, and a channel between thesource 114 and thedrain 116 are doped with an n-type semiconductor, which is called an NMOS structure. - In some embodiments, the
first semiconductor region 104 includes germanium. In some embodiments, thesecond semiconductor region 106 includes germanium. The direct band gap energy of germanium is around 0.8 eV at room temperature, which corresponds to a wavelength of 1550 nm. Thus, a semiconductor optical sensor device that includes germanium (e.g., in the first and second semiconductor regions) is more sensitive to short-wave infrared light than a semiconductor optical sensor device that includes silicon only (e.g., without germanium). - In some embodiments, the
gate insulation layer 110 includes an oxide layer (e.g., SiO2, GeOx, ZrOx, HfOx, SixNy, SixOyNz, TaxOy, SrxOy or AlxOy). In some embodiments, thegate insulation layer 110 includes an oxynitride layer (e.g., SiON). In some embodiments, thegate insulation layer 110 includes a high-κ dielectric material, such as HfO2, HfSiO, or Al2O3. - In some embodiments, the device includes a
substrate insulation layer 108 positioned below thefirst semiconductor region 104. The substrate insulation layer includes one or more of: SiO2, GeOx, ZrOx, HfOx, SixNy, SixOyNz, TaxOy, SrxOy and AlxOy. In some embodiments, thesubstrate insulation layer 108 includes a high-κ dielectric material. In some embodiments, thefirst semiconductor region 104 is positioned over thesubstrate insulation layer 108. In some embodiments, thefirst semiconductor region 104 is in contact with thesubstrate insulation layer 108. In some embodiments, thesubstrate insulation layer 108 is positioned over the substrate 102 (e.g., a silicon substrate). In some embodiments, thesubstrate insulation layer 108 is in contact with thesubstrate 102. - In some embodiments, the device includes a
third semiconductor region 108 that includes germanium doped with a dopant of the second type (e.g., p-type). Thethird semiconductor region 108 is positioned below thefirst semiconductor region 104. - In some embodiments, a doping concentration of the dopant of the second type in the
second semiconductor region 106 is higher than a doping concentration of the dopant of the second type in thethird semiconductor region 108. For example, thesecond semiconductor region 106 has a p+ doping (e.g., at a concentration of one dopant atom per ten thousand atoms or more) and thethird semiconductor region 108 has a p doping (e.g., at a concentration of one dopant atom per hundred million atoms). - In some embodiments, the device includes a
silicon substrate 102. For example, thethird semiconductor region 108, thefirst semiconductor region 104, and thesecond semiconductor region 106 are formed over thesilicon substrate 102. - In some embodiments, the
gate 112 includes one or more of: polysilicon, amorphous silicon, silicon carbide, and metal. In some embodiments, thegate 112 consists of one or more of: polygermanium, amorphous germanium, polysilicon, amorphous silicon, silicon carbide, and metal. - In some embodiments, the
second semiconductor region 106 extends from thesource 114 to thedrain 116. - In some embodiments, the
first semiconductor region 104 extends from thesource 114 to thedrain 116. - In some embodiments, the
gate insulation layer 110 extends from thesource 114 to thedrain 116. - In some embodiments, the
second semiconductor region 106 has a thickness less than 100 nm. In some embodiments, thesecond semiconductor region 106 has a thickness between 1 nm than 100 nm. In some embodiments, thesecond semiconductor region 106 has a thickness between 5 nm than 50 nm. In some embodiments, thesecond semiconductor region 106 has a thickness between 50 nm than 100 nm. In some embodiments, thesecond semiconductor region 106 has a thickness between 10 nm than 40 nm. In some embodiments, thesecond semiconductor region 106 has a thickness between 10 nm than 30 nm. In some embodiments, thesecond semiconductor region 106 has a thickness between 10 nm than 20 nm. In some embodiments, thesecond semiconductor region 106 has a thickness between 20 nm than 30 nm. In some embodiments, thesecond semiconductor region 106 has a thickness between 30 nm than 40 nm. In some embodiments, thesecond semiconductor region 106 has a thickness between 40 nm than 50 nm. - In some embodiments, the
first semiconductor region 104 has a thickness less than 1000 nm. In some embodiments, thefirst semiconductor region 104 has a thickness between 1 nm and 1000 nm. In some embodiments, thefirst semiconductor region 104 has a thickness between 5 nm and 500 nm. In some embodiments, thefirst semiconductor region 104 has a thickness between 500 nm and 1000 nm. In some embodiments, thefirst semiconductor region 104 has a thickness between 10 nm and 500 nm. In some embodiments, thefirst semiconductor region 104 has a thickness between 10 nm and 400 nm. In some embodiments, thefirst semiconductor region 104 has a thickness between 10 nm and 300 nm. In some embodiments, thefirst semiconductor region 104 has a thickness between 10 nm and 200 nm. In some embodiments, thefirst semiconductor region 104 has a thickness between 20 nm and 400 nm. In some embodiments, thefirst semiconductor region 104 has a thickness between 20 nm and 300 nm. In some embodiments, thefirst semiconductor region 104 has a thickness between 20 nm and 200 nm. In some embodiments, thefirst semiconductor region 104 has a thickness between 20 nm and 400 nm. In some embodiments, thefirst semiconductor region 104 has a thickness between 20 nm and 300 nm. In some embodiments, thefirst semiconductor region 104 has a thickness between 20 nm and 200 nm. In some embodiments, thefirst semiconductor region 104 has a thickness between 20 nm and 100 nm. -
FIG. 1A also indicates plane AA upon which the view illustrated inFIG. 1B is taken. -
FIG. 1B is a partial cross-sectional view of the semiconductor optical sensor device illustrated inFIG. 1A , in accordance with some embodiments. - In
FIG. 1B , thefirst semiconductor region 104, thesecond semiconductor region 106, thegate insulation layer 110, thegate 112, the substrate insulation layer orthird semiconductor region 108, and thesubstrate 102 are illustrated. For brevity, the description of these elements are not repeated herein. - As shown in
FIG. 1B , thefirst semiconductor region 104 is in contact with both theupper portion 124 and thelower portion 126 of thesecond semiconductor region 106. Thefirst semiconductor region 104 is in contact with theupper portion 124 of thesecond semiconductor region 106 at least at a location positioned under thegate 112. In some embodiments, thefirst semiconductor region 104 is in contact with theupper portion 124 of thesecond semiconductor region 106 at least at a location positioned directly under thegate 112. In some embodiments, thefirst semiconductor region 104 is in contact with thetop surface 120 of thesecond semiconductor region 106 at least on an edge of thetop surface 120 of thesecond semiconductor region 106. In some embodiments, thefirst semiconductor region 104 is in contact with thetop surface 120 of thesecond semiconductor region 106 at least on an edge of thetop surface 120 of thesecond semiconductor region 106 at a location directly under thegate 112. - In some embodiments, the
second semiconductor region 106 has a first lateral surface (e.g., a combination of alateral surface 128 of theupper portion 124 and alateral surface 130 of the lower portion 126) that extends from the source 114 (FIG. 1A ) to the drain 116 (FIG. 1A ) and is distinct from thetop surface 120 and thebottom surface 122. Thesecond semiconductor region 106 has a second lateral surface (e.g., a combination of alateral surface 132 of theupper portion 124 and alateral surface 134 of the lower portion 126) that extends from the source 114 (FIG. 1A ) to the drain 116 (FIG. 1A ) and is distinct from thetop surface 120 and thebottom surface 122. The first lateral surface and the second lateral surface are located on opposite sides of thesecond semiconductor region 106. In some embodiments, thefirst semiconductor region 104 is in contact with theupper portion 124 of thesecond semiconductor region 106 through aportion 128 of the first lateral surface. In some embodiments, thefirst semiconductor region 104 is in contact with theupper portion 124 of thesecond semiconductor region 106 through aportion 132 of the second lateral surface. In some embodiments, thefirst semiconductor region 104 is in contact with theupper portion 124 of thesecond semiconductor region 106 through aportion 128 of the first lateral surface at a location directly under thegate 112 and thefirst semiconductor region 104 is also in contact with theupper portion 124 of thesecond semiconductor region 106 through aportion 132 of the second lateral surface at a location directly under thegate 112. - In some embodiments, the
lateral surface 128 of theupper portion 124 has a thickness less than 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm. In some embodiments, thelateral surface 132 of theupper portion 124 has a thickness less than 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm. In some embodiments, thelateral surface 128 of theupper portion 124 has a thickness less a thickness of thelateral surface 130 of thelower portion 126. In some embodiments, thelateral surface 132 of theupper portion 124 has a thickness less a thickness of thelateral surface 134 of thelower portion 126. -
FIGS. 2A-2B are used below to illustrate operational principles of the semiconductor optical sensor device in accordance with some embodiments. However,FIGS. 2A-2B and the described principles are not intended to limit the scope of claims. -
FIG. 2A is a schematic diagram illustrating an operation of a semiconductor optical sensor device in accordance with some embodiments. - The device illustrated in
FIG. 2A is similar the device illustrated inFIG. 1A . For brevity, the description of the elements described above with respect toFIG. 1A is not repeated herein. - In
FIG. 2A , thefirst semiconductor region 104 is doped with an n-type semiconductor. Thesecond semiconductor region 106 is heavily doped with a p-type semiconductor. Thethird semiconductor region 108 is doped with a p-type semiconductor. In some embodiments, thethird semiconductor region 108 is lightly doped with the p-type semiconductor. - While voltage VG is applied to the
gate 112, apotential well 202 is formed between thesecond semiconductor region 106 and thegate insulation layer 110. While the device (in particular, the first semiconductor region 104) is exposed to light, photo-generated carriers are generated. While voltage VG is applied to thegate 112, the photo-generated carriers migrate to thepotential well 202. -
FIG. 2B is a schematic diagram illustrating the operation of the semiconductor optical sensor device illustrated inFIG. 2A , in accordance with some embodiments. -
FIG. 2B is similar toFIG. 2A . For brevity, the description of the same elements described above with respect toFIG. 1B is not repeated herein. - In
FIG. 2B , the migration path of the photo-generated carriers to thepotential well 202 located between thesecond semiconductor region 106 and thegate insulation layer 110 is indicated. The photo-generated carriers get into thepotential well 202 through lateral surfaces ofsecond semiconductor region 106. In some embodiments, at least a portion of the photo-generated carriers directly pass through a bottom surface of thesecond semiconductor region 106 to reach thepotential well 202. This is possible because thesecond semiconductor region 106 is thin and the barrier between thesecond semiconductor region 106 and thepotential well 202 is low (e.g., less than band gap of Ge). When the photo-generated carriers migrate through the bottom surface of thesecond semiconductor region 106, carrier recombination may take place in thesecond semiconductor region 106. - This direct contact between the
first semiconductor region 104 and thepotential well 202 significantly increases migration of the photo-generated carriers from thefirst semiconductor region 104 to thepotential well 202. Thus, a thickfirst semiconductor region 104 may be used for increasing the quantum efficiency, while the photo-generated carriers are effectively transported to thepotential well 202 for increasing the on/off signal modulation. - In the absence of an exposure to light, the device would have a certain drain current (called herein Ioff). However, when the device is exposed to light, the photo-generated carriers modulate the drain current (e.g., the drain current increases to Ion).
-
FIG. 3 illustrates exemplary band diagrams in accordance with some embodiments. AlthoughFIG. 3 is used to illustrate operational principles of the semiconductor optical sensor device,FIG. 3 and the described principles are not intended to limit the scope of claims. - The band diagrams in
FIG. 3 represent electron energy levels from the gate of the semiconductor optical sensor device to the substrate of the semiconductor optical sensor device. - A GCMD can be represented as having a small capacitance and a large capacitance connected around a channel.
- The band diagram (a) represents that the device is in the off state.
- The band diagram (b) represents that the incident light is absorbed in the substrate region, and carriers are photo-generated in the small capacitance. There is a quasi-Fermi level split in the buried hole channel and substrate.
- The band diagram (c) represents that the photo-generated carriers from the low capacitance region are transferred to the large capacitance region (oxide-surface interface) automatically with a proper gate bias. The transferred photo-generated carriers in the oxide-surface interface reduce band bending between the source/drain and the buried hole channel, ultimately increasing the drain current.
- The band of the channel with incident light is similar to the band with a lower gate voltage, which is represented in the band diagram (d).
-
FIGS. 4A and 4B are schematic diagrams illustrating a single channel configuration and a multi-channel configuration of a semiconductor optical sensor device. The schematic diagrams inFIGS. 4A and 4B are based on top-down views of the semiconductor optical sensor device. However, it should be noted that the schematic diagrams inFIGS. 4A and 4B are used to represent relative sizes and positions of various elements and that the schematic diagrams inFIGS. 4A and 4B are not cross-sectional views. -
FIG. 4A is a schematic diagram illustrating a single channel configuration of a semiconductor optical sensor device in accordance with some embodiments. -
FIG. 4A illustrates that the device has agate 406, asource 402, and adrain 404. The device also includes achannel 412 that extends from thesource 402 to thedrain 404. Thechannel 412 is typically defined by the second semiconductor region. For example, the shape of thechannel 412 is determined by a pattern of ion implantation in forming the second semiconductor region. Thesource 402 hasmultiple contacts 408 with thechannel 412 and thedrain 404 hasmultiple contacts 408 with thechannel 412. -
FIG. 4B is a schematic diagram illustrating a multi-channel configuration of a semiconductor optical sensor device in accordance with some embodiments. -
FIG. 4B is similar toFIG. 4A except that the device hasmultiple channels 414 between thesource 402 and thedrain 404. In some embodiments, the second semiconductor region definesmultiple channels 414 between thesource 402 and thedrain 404. Eachchannel 414 inFIG. 4B connects asingle contact 408 of thesource 402 and asingle contact 410 of thedrain 404. Thus, a width of thechannel 414 inFIG. 4B is less than a width of thechannel 412 inFIG. 4A . The reduced width of a channel is believed to facilitate a transfer of a photo-generated carrier to a large capacitance region (e.g., an interface of the second semiconductor region and the gate insulation layer) of the device. -
FIG. 5 is a partial cross-sectional view of semiconductor optical sensor devices in accordance with some embodiments. -
FIG. 5 illustrates that a plurality of semiconductor optical sensor devices (e.g., devices 502-1 and 502-2) are formed on a common substrate. The multiple devices form a sensor array. AlthoughFIG. 5 illustrates two semiconductor optical sensor devices, the sensor array may include more than two semiconductor optical sensor devices. In some embodiments, the sensor array includes a two-dimensional array of semiconductor optical sensor devices. -
FIG. 5 also illustrates thatvias 506 are formed to connect thegate 112, the source, and the drain of the devices 502-1 and 502-2. - In some embodiments, the plurality of devices (e.g., devices 502-1 and 502-2) has the
first semiconductor region 104 on a common plane. In some embodiments, thefirst semiconductor region 104 of the plurality of devices is formed concurrently (e.g., using epitaxial growth of the first semiconductor region 104). - In some embodiments, the plurality of devices (e.g., devices 502-1 and 502-2) has the
second semiconductor region 106 on a common plane. In some embodiments, thesecond semiconductor region 106 of the plurality of devices is formed concurrently (e.g., using ion implantation). - In some embodiments, the plurality of devices (e.g., devices 502-1 and 502-2) has the
third semiconductor region 108 on a common plane. In some embodiments, thethird semiconductor region 108 of the plurality of devices is formed concurrently (e.g., using epitaxial growth of germanium islands). - In some embodiments, the plurality of devices is separated by one or more trenches. For example, the device 502-1 and the device 502-2 are separate by a trench. In some embodiments, the one or more trenches are filled with an insulator. In some embodiments, a trench is a shallow trench isolator.
- In some embodiments, the plurality of devices is positioned on separate germanium islands formed on the
common silicon substrate 102. For example, in some embodiments, third semiconductor regions 108 (e.g., germanium islands) are formed on thesubstrate 102 and the rest of devices 502-1 and 502-2 are formed over thethird semiconductor regions 108. - In some embodiments, the sensor array includes a passivation layer over the plurality of devices. For example, the
passivation layer 504 is positioned over the devices 502-1 and 502-2 inFIG. 5 . - In some embodiments, the sensor array includes a
passivation layer 504 between the plurality of devices. For example, thepassivation layer 504 is positioned between the devices 502-1 and 502-2 inFIG. 5 . -
FIG. 6 illustrates an exemplary sensor circuit in accordance with some embodiments. - The sensor circuit includes a photo-
sensing element 602. The photo-sensing element 602 has a source terminal, a gate terminal, a drain terminal, andbody terminal 605. The sensor circuit also includes aselection transistor 604 having a source terminal, a gate terminal, and a drain terminal. In some embodiments, the drain terminal of theselection transistor 604 is electrically coupled (e.g., at a point 606) with the source terminal of the photo-sensing element 602. In some embodiments, the source terminal of theselection transistor 604 is electrically coupled (e.g., at the point 606) with the drain terminal of the photo-sensing element 602. - In some embodiments, the photo-sensing element is a GCMD (e.g., the
device 100,FIG. 1A ). - In some embodiments, the source terminal or the drain terminal, of the photo-
sensing element 602, that is not electrically coupled with the source terminal or the drain terminal of theselection transistor 604 is connected to a ground. For example, V2 is connected to a ground. - In some embodiments, the source terminal or the drain terminal, of the photo-
sensing element 602, that is electrically coupled with the source terminal or the drain terminal of theselection transistor 604 is not connected to a ground. For example, thepoint 606 is not connected to a ground. - In some embodiments, the source terminal or the drain terminal, of the photo-
sensing element 602, that is electrically coupled with the source terminal or the drain terminal of theselection transistor 604 is electrically coupled with a first voltage source. For example, V2 is connected to the first voltage source. - In some embodiments, the first voltage source provides a first fixed voltage, such as a voltage that is distinct from the ground.
- In some embodiments, the source terminal or the drain terminal, of the
selection transistor 604, that is not electrically coupled with the source terminal or the drain terminal of the photo-sensing element 620 is electrically coupled with a second voltage source. For example, V1 is connected to the second voltage source. In some embodiments, the second voltage source provides a second fixed voltage. - In some embodiments, the sensor circuit includes no more than two transistors, the two transistors including the
selection transistor 604. In some embodiments, the sensor circuit also includes a gate control transistor that is electrically coupled to the gate of the photo-sensing element. - In some embodiments, the sensor circuit includes no more than one transistor, the one transistor being the
selection transistor 604. - The sensor circuit in
FIG. 6 is called herein one-transistor modified active-pixel sensor (1T-MAPS), because the sensor circuit includes a single transistor and a modified active-pixel sensor. The difference between 1T-MAPS and a conventional sensor circuit called three-transistor active-pixel sensor (3T-APS) is described below with respect toFIGS. 7A-7B . -
FIG. 7A illustrates an exemplary 3T-APS circuit in accordance with some embodiments. - The 3T-APS circuit includes a photo-sensing element (e.g., a photodiode) and three transistors: a reset transistor Mrst, a source-follower transistor Msf, and a select transistor Msel.
- The reset transistor Mrst works as a reset switch. For example, Mrst receives a gate signal RST, which allows a reset voltage, Vrst, to be provided to the photo-sensing element to reset the photo-sensing element.
- The source-follower transistor Msf acts as a buffer. For example, Msf receives an input (e.g., a voltage input) from the photo-sensing element, which allows a high voltage Vdd to be output to the source of the select transistor Msel.
- The select transistor Msel works as a readout switch. For example, Msel receives a row selection signal ROW, which allows an output from the source-follower transistor Msf to be provided to a column line.
-
FIG. 7B illustrates an exemplary 1T-MAPS circuit in accordance with some embodiments. - As explained above with respect to
FIG. 6 , the 1T-MAPS circuit includes one photo-sensing element (e.g., GCMD) and one transistor, namely a select transistor Msel. - The select transistor Msel receives a row selection signal ROW, which allows a current from the column line to flow to an input of the photo-sensing element. Alternatively, the row selection signal ROW, provided to the select transistor Msel, allows a current from the photo-sensing element to flow to the column line. In some embodiments, the column line is set to a fixed voltage.
- In some embodiments, the 1T-MAPS circuit does not require a reset switch, because photo-generated carriers stored in the GCMD dissipate in a short period of time (e.g., 0.1 second).
- A comparison of the 3T-APS circuit illustrated in
FIG. 7A and the 1T-MAPS circuit illustrated inFIG. 7B shows that the 1T-MAPS circuit has a much smaller size than the 3T-APS circuit. Thus, a 1T-MAPS circuit is more cost advantageous than a 3T-APS circuit made of a same material. In addition, due to the smaller size, more 1T-MAPS circuits can be placed on a same area of a die than 3T-APS circuits, thereby increasing a number of pixels on the die. -
FIGS. 8A-8H illustrate exemplary sensor circuits in accordance with some embodiments. InFIGS. 8A-8H , a switch symbol represents a select transistor. -
FIGS. 8A-8D illustrate exemplary sensor circuits that include a PMOS-type GCMD. - In
FIG. 8A , the gate of the GCMD is connected to a ground VG, and the drain of the GCMD is connected to a low voltage source V1 (e.g., ground). The source of the GCMD is connected to a switch (or a select transistor), which is connected to a fixed voltage, Vconstant2. In some embodiments, the body is connected to a high voltage source VDD. - In
FIG. 8B , the gate of the GCMD is connected to a fixed voltage Vconstant1, and the drain of the GCMD is connected to a low voltage source V1 (e.g., ground). The source of the GCMD is connected to a switch (or a select transistor), which is connected to a fixed voltage, Vconstant2. In some embodiments, the body is connected to a high voltage source VDD. - In
FIG. 8C , the gate of the GCMD is connected to a fixed voltage Vconstant1, and the source of the GCMD is connected to a high voltage source VDD. The drain of the GCMD is connected to a switch (or a select transistor), which is connected to a fixed voltage, Vconstant2. In some embodiments, the body is connected to a high voltage source VDD2. - In
FIG. 8D , the gate of the GCMD is connected to a fixed voltage Vconstant1, and the source of the GCMD is connected to a high voltage source VDD. The drain of the GCMD is connected to a switch (or a select transistor), which is connected to a variable voltage, Vvariable. In some embodiments, the body is connected to a high voltage source VDD2. -
FIGS. 8E-8H illustrate exemplary sensor circuits that include NMOS type GCMD. - In
FIG. 8E , the gate and the drain of the GCMD are connected to a high voltage source VDD. The source of the GCMD is connected to a switch (or a select transistor), which is connected to a fixed voltage, Vconstant2. In some embodiments, the body is connected to a ground. - In
FIG. 8F , the gate of the GCMD is connected to a fixed voltage Vconstant1, and the drain of the GCMD is connected to a high voltage source VDD. The source of the GCMD is connected to a switch (or a select transistor), which is connected to a fixed voltage, Vconstant2. In some embodiments, the body is connected to a ground. - In
FIG. 8G , the gate of the GCMD is connected to a fixed voltage Vconstant1, and the source of the GCMD is connected to a ground. The drain of the GCMD is connected to a switch (or a select transistor), which is connected to a fixed voltage, Vconstant2. In some embodiments, the body is connected to a ground. - In
FIG. 8H , the gate of the GCMD is connected to a fixed voltage Vconstant1, and the source of the GCMD is connected to a ground. The drain of the GCMD is connected to a switch (or a select transistor), which is connected to a variable voltage, Vvariable. In some embodiments, the body is connected to a ground. - In
FIGS. 8A-8H , the drain current in the GCMD changes depending on whether the GCMD is exposed to light. Thus, in some embodiments, the GCMD is modeled as a current source that provides Ion when the GCMD is exposed to light and provide Ioff when the GCMD is not exposed to light. -
FIGS. 9A-9C illustrate exemplary converter circuits in accordance with some embodiments. -
FIG. 9A illustrates anexemplary converter circuit 902 in accordance with some embodiments. - The
converter circuit 902 includes a first transimpedance amplifier 904 (e.g., an operational amplifier) that has an input terminal (e.g., an input terminal receiving IGCMD from the photo-sensing element, such as the GCMD) electrically coupled with the source terminal or the drain terminal of the selection transistor of a first sensor circuit (e.g., the sensor circuit inFIG. 6 ), that is not electrically coupled with the source terminal or the drain terminal of the photo-sensing element (e.g., the terminal having a voltage V1 inFIG. 6 ). Thefirst transimpedance amplifier 904 is configured to convert a current input (e.g., IGCMD) from the photo-sensing element into a voltage output (e.g., Vtamp). - The
converter circuit 902 also includes adifferential amplifier 906 having two input terminals. A first input terminal of the two input terminals is electrically coupled with the voltage output (e.g., Vtamp) of thefirst transimpedance amplifier 904 and a second input terminal of the two input terminals is electrically coupled with a voltage source that is configured to provide a voltage (e.g., VBASE) corresponding to a base current provided by the photo-sensing element. The differential amplifier is configured to output a voltage (e.g., Vdamp) based on a voltage difference between the voltage output (e.g., Vtamp) and the voltage provided by the voltage source (e.g., VBASE). In some embodiments, thedifferential amplifier 906 includes an operational amplifier. In some embodiments, thedifferential amplifier 906 includes a transistor long tailed pair. - In some embodiments, the
converter circuit 922 includes an analog-to-digital converter 908 electrically coupled to an output of the differential amplifier 906 (e.g., Vtamp), the analog-to-digital converter configured to convert the output (e.g., a voltage output) of the differential amplifier 906 (e.g., Vtamp) into a digital signal. -
FIG. 9B illustrates anexemplary converter circuit 912 in accordance with some embodiments. Theconverter circuit 912 is similar to theconverter circuit 902 illustrated inFIG. 9A . Some of the features described with respect toFIG. 9A are applicable to theconverter circuit 912. For brevity, the description of such features is not repeated herein. -
FIG. 9B illustrates that, in some embodiments, thefirst transimpedance amplifier 904 in theconverter circuit 912 includes anoperational amplifier 910. Theoperational amplifier 910 has a non-inverting input terminal that is electrically coupled with the source terminal or the drain terminal of the selection transistor of the first sensor circuit (E.g., the terminal having a voltage V1 inFIG. 6 ). Theoperational amplifier 910 also has an inverting input terminal that is electrically coupled with a reference voltage source that provides a reference voltage VREF. Theoperational amplifier 910 has an output terminal, and a resistor with a resistance value R is electrically coupled to the non-inverting input terminal on a first end of the resistor and to the output terminal on the second end, opposite to the first end, of the resistor. - In operation, the voltage output Vtamp is determined as follows:
-
V tamp =V REF +R·I GCMD - Furthermore, the current from the GCMD can be modeled as follows:
-
I GCMD =I off (no light) -
I GCMD =I Δ +I off (light) - In some embodiments, the base current corresponds to a current provided by the photo-sensing element while the photo-sensing element receives substantially no light (e.g., Ioff). When Ioff is converted by the
first transimpedance amplifier 904, a corresponding voltage VBASE is determined as follows: -
V BASE =V REF +R·I off - Then, the voltage difference between Vtamp and VBASE is as follows:
-
V tamp −V BASE =R·I Δ - The voltage output Vdamp of the
differential amplifier 906 is as follows: -
Vdamp=A·R·I Δ - where A is a differential gain of the
differential amplifier 906. In some embodiments, the differential gain is one of: one, two, three, five, ten, twenty, fifty, and one hundred. -
FIG. 9B also illustrates that, in some embodiments, the voltage source is a digital-to-analog converter (DAC) 916. For example, theDAC 916 is configured to provide VBASE. -
FIG. 9C illustrates anexemplary converter circuit 922 in accordance with some embodiments. Theconverter circuit 922 is similar to theconverter circuit 902 illustrated inFIG. 9A and theconverter circuit 912 illustrated inFIG. 9B . Some of the features described with respect toFIGS. 9A and 9B are applicable to theconverter circuit 922. For example, in some embodiments, theconverter circuit 922 includes the digital-to-analog converter 916. In some embodiments, thefirst transimpedance amplifier 904 includes anoperational amplifier 910. For brevity, the description of such features is not repeated herein. -
FIG. 9C illustrates that the voltage source (that provides VBASE) is asecond transimpedance amplifier 914 having an input terminal electrically coupled with a second sensor circuit that is distinct from the first sensor circuit. In some embodiments, the input terminal of thesecond transimpedance amplifier 914 is electrically coupled with the source terminal or the drain terminal of the selection transistor of the second sensor circuit. In some embodiments, the photo-sensing element of the second sensor circuit is optically covered so that the photo-sensing element of the second sensor circuit is prevented from receiving light. Thus, the second sensor circuit provides Toff to thesecond transimpedance amplifier 914. Thesecond transimpedance amplifier 914 converts Ioff to VBASE. In some embodiments, thesecond transimpedance amplifier 914 includes an operational amplifier. - In some embodiments, the
first transimpedance amplifier 904 is configured to electrically couple with a respective sensor circuit of a plurality of sensor circuits through a multiplexer. For example, theconverter circuit 922 is coupled to amultiplexer 916. The multiplexer receives a column address to select one of a plurality of column lines. Each column line is connected to multiple sensor circuits, each having a selection transistor that receives a ROW signal. Thus, based on a column address and a ROW signal, one sensor circuit in a two-dimensional array of sensor circuits is selected, and a current output from the selected sensor circuit is provided to thefirst transimpedance amplifier 904 through themultiplexer 916. - Although
FIGS. 9A-9C illustrate selected embodiments, it should be noted that a converter circuit may include a subset of the features described inFIGS. 9A-9C (e.g., theconverter circuit 922 may be coupled with themultiplexer 916 without having the second transimpedance amplifier 914). In some embodiments, a converter circuit includes additional features not described with respect toFIGS. 9A-9C . -
FIG. 10 illustrates an exemplary image sensor device in accordance with some embodiments. - In accordance with some embodiments, the image sensor device includes an array of sensors. A respective sensor in the array of sensors includes a sensor circuit (e.g.,
FIGS. 8A-8H ). - In some embodiments, the image sensor device includes a converter circuit (e.g.,
FIGS. 9A-9C ). - In some embodiments, the array of sensors includes multiple rows of sensors (e.g., at least two rows of sensors are illustrated in
FIG. 10 ). For sensors in a respective row, gate terminals of selection transistors are electrically coupled to a common selection line. For example, as shown inFIG. 10 , gate terminals of sensor circuits in a top row are electrically coupled to a same signal line. - In some embodiments, the array of sensors includes multiple columns of sensors (e.g., at least three columns of sensors are illustrated in
FIG. 10 ). For sensors in a respective column, one of source terminals or drain terminals of selection transistors (i.e., either the source terminals of the selection transistors or the drain terminals of the selection transistors) are electrically coupled to a common column line. For example, as shown inFIG. 10 , the drain terminals of the selection transistors in a left column of sensors are electrically coupled to a same column line. -
FIGS. 11A-11E illustrate an exemplary method for making a semiconductor optical sensor device in accordance with some embodiments. -
FIG. 11A illustrates forming the semiconductor optical sensor device includes forming athird semiconductor region 108 on asilicon substrate 102. In some embodiments, thethird semiconductor region 108 is epitaxially grown on thesubstrate 102. -
FIG. 11B illustrates forming afirst semiconductor region 104, above thesilicon substrate 102, doped with a dopant of a first type. - In some embodiments, the
first semiconductor region 104 is formed by epitaxially growing thefirst semiconductor region 104. - In some embodiments, the
first semiconductor region 104 is doped in-situ with the dopant of the first type (e.g., n-type) while thefirst semiconductor region 104 is grown. - In some embodiments, the
first semiconductor region 104 is doped with the dopant of the first type (e.g., n-type) using an ion implantation process or a gas phase diffusion process. In some embodiments, thefirst semiconductor region 104 is doped with the dopant of the first type (e.g., n-type) using an ion implantation process. In some embodiments, thefirst semiconductor region 104 is doped with the dopant of the first type (e.g., n-type) using a gas phase diffusion process. -
FIG. 11C illustrates forming asecond semiconductor region 106, above thesilicon substrate 102, doped with a dopant of a second type. Thesecond semiconductor region 106 is positioned above thefirst semiconductor region 104. The first type (e.g., n-type) is distinct from the second type (e.g., p-type). - In some embodiments, the
second semiconductor region 106 is formed by epitaxially growing thesecond semiconductor region 106. - In some embodiments, the
second semiconductor region 106 is doped in-situ with the dopant of the second type (e.g., p-type, and in particular, p+) while thesecond semiconductor region 106 is grown. - In some embodiments, the
second semiconductor region 106 is doped with the dopant of the second type (e.g., p-type, and in particular, p+) using an ion implantation process or a gas phase diffusion process. In some embodiments, thesecond semiconductor region 106 is doped with the dopant of the second type (e.g., p-type, and in particular, p+) using an ion implantation process. In some embodiments, thesecond semiconductor region 106 is doped with the dopant of the second type (e.g., p-type, and in particular, p+) using a gas phase diffusion process. - In some embodiments, the
second semiconductor region 106 is doped with the dopant of the second type (e.g., p-type, and in particular, p+) using an ion implantation process after thefirst semiconductor region 104 is doped with the dopant of the first type using an ion implantation process or a gas phase diffusion process. In some embodiments, thesecond semiconductor region 106 is doped with the dopant of the second type (e.g., p-type, and in particular, p+) using an ion implantation process after thefirst semiconductor region 104 is doped with the dopant of the first type using an ion implantation process. In some embodiments, thesecond semiconductor region 106 is doped with the dopant of the second type (e.g., p-type, and in particular, p+) using an ion implantation process after thefirst semiconductor region 104 is doped with the dopant of the first type using a gas phase diffusion process. -
FIG. 11D illustrates forming agate insulation layer 110 above thesecond semiconductor region 106. One or more portions of thesecond semiconductor region 106 are exposed from thegate insulation layer 110 to define a source and a drain. For example, thegate insulation layer 110 is pattern etched (e.g., using a mask) to expose the source and the drain. - As described with respect to
FIGS. 1A and 1B , thesecond semiconductor region 106 has a top surface that faces thegate insulation layer 110. Thesecond semiconductor region 106 has a bottom surface that is opposite to the top surface of thesecond semiconductor region 106. Thesecond semiconductor region 106 has an upper portion that includes the top surface of thesecond semiconductor region 106. Thesecond semiconductor region 106 has a lower portion that includes the bottom surface of thesecond semiconductor region 106 and is mutually exclusive with the upper portion. Thefirst semiconductor region 104 is in contact with both the upper portion and the lower portion of thesecond semiconductor region 106. Thefirst semiconductor region 104 is in contact with the upper portion of thesecond semiconductor region 106 at least at a location positioned under thegate 112. -
FIG. 11E illustrates forming agate 112 positioned above thegate insulation layer 110. - In some embodiments, a method of forming a sensor array includes concurrently forming a plurality of devices on a common silicon substrate. For example, third semiconductor regions of multiple devices may be formed concurrently in a single epitaxial growth process. Subsequently, first semiconductor regions of the multiple devices may be formed concurrently in a single epitaxial growth process. Thereafter, second semiconductor regions of the multiple devices may be formed concurrently in a single ion implantation process. Similarly, gate insulation layers of the multiple devices may be formed concurrently, and gates of the multiple devices may be formed concurrently.
- In accordance with some embodiments, a method for sensing light includes exposing a photo-sensing element (e.g., GCMD in
FIG. 6 ) to the light. - The method also includes providing a fixed voltage to the source terminal of the photo-sensing element (e.g., by applying a fixed voltage V1 and applying VR to the selection transistor 604 (
FIG. 6 ). Based on an intensity of light on the GCMD, a drain current of the GCMD changes. - In some embodiments, the method includes determining an intensity of the light based on the drain current of the photo-sensing element (e.g., GCMD). A change in the drain current indicates whether light is detected by the photo-sensing element.
- In some embodiments, measuring the drain current includes converting the drain current to a voltage signal (e.g., converting the drain current IGCMD to Vtamp,
FIG. 9A ). - In some embodiments, converting the drain current to the voltage signal includes using a transimpedance amplifier (e.g.,
transimpedance amplifier 904,FIG. 9A ) to convert the drain current to the voltage signal. - In some embodiments, measuring the drain current includes using any converter circuit described herein (e.g.,
FIGS. 9A-9C ). - In some embodiments, the method includes activating the selection transistor of the sensor circuit (e.g., the
selection transistor 604,FIG. 6 ). Activating the selection transistor allows a drain current to flow through the selection transistor, thereby allowing a measurement of the drain current. - In some embodiments, the fixed voltage is provided to the source terminal of the photo-sensing element prior to exposing the photo-sensing element to light. For example, in
FIG. 6 , theselection transistor 604 is activated before exposing the photo-sensing element 602 to light. - In some embodiments, the fixed voltage is provided to the source terminal of the photo-sensing element subsequent to exposing the photo-sensing element to light. For example, in
FIG. 6 , theselection transistor 604 is activated after exposing the photo-sensing element 602 to light. - In accordance with some embodiments, a method for detecting an optical image includes exposing any array of sensors described herein (e.g.,
FIG. 10 ) to a pattern of light. - The method also includes, for a photo-sensing element of a respective sensor in the array of sensors, providing a respective voltage to the source terminal of the photo-sensing element of the respective image sensor. For example, a selection transistor (e.g., the
selection transistor 604,FIG. 6 ) of the respective sensor is activated to provide the respective voltage, thereby allowing a measurement of a drain current of the respective sensor. - The method further includes measuring a drain current of the photo-sensing element (e.g., the photo-sensing element 602).
- In some embodiments, the source terminals of the photo-sensing elements in the array of sensors concurrently receive respective voltages. For example, respective voltages are concurrently applied to multiple photo-sensing elements (e.g., photo-sensing elements in a same row) for a concurrent reading of the multiple photo-sensing elements.
- In some embodiments, the source terminals of the photo-sensing elements in the array of sensors sequentially receive respective voltages. For example, respective voltages are sequentially applied to multiple photo-sensing elements (e.g., photo-sensing elements in a same column) for sequential reading of the multiple photo-sensing elements.
- In some embodiments, the source terminals of photo-sensing elements in the array of sensors receive a same voltage.
- In some embodiments, the drain currents of the photo-sensing elements in the array of sensors are measured in batches. For example, the drain currents of photo-sensing elements in a same row are measured in a batch (e.g., as a set).
- In some embodiments, the drain currents of the photo-sensing elements in the array of sensors are concurrently measured. For example, the drain currents of the photo-sensing elements in a same row are concurrently measured.
- In some embodiments, the drain currents of the photo-sensing elements in the array of sensors are sequentially measured. For example, the drain currents of the photo-sensing elements in a same column are concurrently measured.
- The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.
Claims (1)
1. A device for sensing light, the device comprising:
a first semiconductor region doped with a dopant of a first type;
a second semiconductor region doped with a dopant of a second type, wherein:
the second semiconductor region is positioned above the first semiconductor region; and
the first type is distinct from the second type;
a gate insulation layer positioned above the second semiconductor region;
a gate positioned above the gate insulation layer;
a source electrically coupled with the second semiconductor region; and
a drain electrically coupled with the second semiconductor region, wherein:
the second semiconductor region has a top surface that is positioned toward the gate insulation layer;
the second semiconductor region has a bottom surface that is positioned opposite to the top surface of the second semiconductor region;
the second semiconductor region has an upper portion that includes the top surface of the second semiconductor region;
the second semiconductor region has a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion;
the upper portion of the second semiconductor region extends from the source to the drain;
the lower portion of the second semiconductor region extends from the source to the drain;
the first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region; and
the first semiconductor region is in contact with the upper portion of the second semiconductor region at least at a location positioned under the gate.
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US17/684,124 US20230019977A1 (en) | 2013-06-20 | 2022-03-01 | Gate-Controlled Charge Modulated Device for CMOS Image Sensors |
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JP6326487B2 (en) | 2018-05-16 |
CN105518861A (en) | 2016-04-20 |
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US11264418B2 (en) | 2022-03-01 |
JP2018129536A (en) | 2018-08-16 |
EP3528288A1 (en) | 2019-08-21 |
CN105518861B (en) | 2018-10-02 |
US20190221595A1 (en) | 2019-07-18 |
US20160099372A1 (en) | 2016-04-07 |
KR102373389B1 (en) | 2022-03-10 |
KR102246766B1 (en) | 2021-04-29 |
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