JPH02179985A - Time code signal delay processing circuit - Google Patents

Abstract

PURPOSE:To add a delay quantity according to a tape reproducing speed to a regenerative time code signal by presetting offset data corresponding to the reproducing speed for a tape to an address generating counter means. CONSTITUTION:A measuring counter means 6 calculates the interval between the leading edge and the trailing edge of the regenerative time code signal based on a detecting output by means of an edge detecting means 3. Timing detecting means 8 and 9 detect the 1/4 position timing and 3/4 position timing of the measured edge interval as the latch timing of the regenerative time code signal, and by counting detected output pulses by means of the timing detecting means 8 and 9, an address generating counter means 16 forms the write/read address data to be applied to a memory means 2. Further, the offset data corresponding to the reproducing speed for the memory means 2 are preset to the address generating counter means 16. Thus the regenerative time code signal to have applied the delay quantity corresponding to the reproducing speed for the tape can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Industrial Field of Application The present invention provides a time code that gives a reproduced time code signal obtained by reproducing a time code recorded in the longitudinal direction of a tape an amount of delay corresponding to the reproduction speed with respect to the tape. The present invention relates to a signal delay processing circuit, and is applied to, for example, an editing device using a digital video tape recorder.

B0 Summary of the Invention The present invention provides a method of measuring the interval between rising edges of the reproduced time code signal when giving a delay amount in a memory means to the reproduced time code signal obtained by reproducing the time code recorded in the longitudinal direction of the tape. 1/4 of this edge spacing
The address generation counter means detects the position timing of and the position timing of 3/4, and counts the detected output pulses by the address generation counter means to form the address data of the memory means, corresponding to the playback speed for the tape. By presetting the offset data, it is possible to apply a delay amount corresponding to the playback speed of the tape to the playback time code signal in the memory means.

C1 Prior Art In general, in a videotape editing device, it is necessary to determine with high precision the position of each video track on a videotape on which video signals are recorded obliquely, so a time code serving as an address signal is recorded on the tape. The signal is recorded in advance, and editing work is performed while reading the time code signal. The above-mentioned time codes include longitudinal time code (so-called LTC) recorded along the longitudinal direction of the video tape, that is, along the tape running direction, and vertical time code (so-called VITC) recorded in the vertical synchronization section on the video track. These are hours, minutes, seconds,
A type of address information indicating a frame etc. is recorded as a time code signal such as a bi-phase modulation code.

Furthermore, in a digital video tape recorder that digitally records a video signal on each video track on a video tape, various processes such as error correction processing are performed on the video data obtained by converting the video signal into digital data, and the video data is recorded on the tape. While the time code (LTC) that can be played back in real time can be played back in real time, the playback of video signals recorded digitally on tape requires processing time for various processes such as on-board recording correction processing. It is known that a shift normally occurs between the video signal reproduced from the tape and the time code (LTC).

For example, as disclosed in Japanese Unexamined Patent Publication No. 62-241192, the present applicant has proposed that in a digital video tape recorder with LTC recording, the LTC is set in advance by the time delay of the video signal with respect to the time code (LTC) in the playback system. By delaying and recording the data in the recording system, there is a video tape recorder that allows the video signal and time code to be obtained without a hitch during playback, and as Tokukai No. 62-188839, the time code in the playback system is He previously proposed a video tape recorder in which the playback system performs arithmetic processing (delay processing) on the time code so that the time delay of the video signal is in units of frames.

D0 Problems to be Solved by the Invention By the way, in a digital video tape recorder with LTC recording, the time delay of the video signal with respect to the time code in the playback system changes depending on the tape playback speed, so hH collection work including variable speed playback mode is difficult. When performing this, there was a problem in that the editing point could not be specified with high precision using the time code reproduced from the tape.

In view of the above-mentioned conventional problems, the present invention enables editing work including a variable speed playback mode by specifying editing points with high precision using the time code played back from the tape in a digital video tape recorder with LTC recording. The present invention aims to provide a time code signal delay processing circuit that gives a reproduced time code signal reproduced from a tape a delay amount corresponding to the tape reproduction speed.

Means for Solving the Problems In order to solve the above-mentioned problems, the time code signal delay processing circuit according to the present invention provides a time code signal that reproduces a time code recorded in the longitudinal direction of a tape. a memory means supplied; an edge detection means for detecting rising edges and falling edges of the reproduced time code signal; a measurement counter means for measuring the interval between each edge detected by the edge detection means; Timing detection means for detecting 1/4 position timing and 3/4 position timing of the edge interval measured by the counter means, and offset data corresponding to the playback speed for the tape are preset, and the timing detection means and address generation counter means for counting detection output pulses to form address data for the memory means, wherein the memory means gives the reproduced time code signal a delay amount corresponding to the reproduction speed with respect to the tape. There is.

F0 operation In the time code signal delay processing circuit according to the present invention, the rising edge and the falling edge of the reproduced time code signal obtained by reproducing the time code recorded in the longitudinal direction of the tape are detected by the edge detection means, and the measurement counter is detected. The means measures the interval between the rising edge and the falling edge of the reproduced time code signal based on the detection output from the edge detecting means. The timing detection means detects the position timing of 1/4 and the position timing of 3/4 of the edge interval measured by the measurement counter means as the latch timing of the reproduction time code signal. The address generation counter means forms fortune-telling/read address data to be applied to the memory means by counting the detection output pulses from the timing detecting means. By presetting the address generation counter means with offset data corresponding to the playback speed of the tape, a playback time code signal giving a delay amount corresponding to the playback speed of the tape is obtained via the memory means. It will be done.

G. Embodiment Hereinafter, an embodiment of the time code signal delay processing circuit according to the present invention will be described in detail with reference to the drawings.

The time code signal delay processing circuit shown in the block diagram of FIG. 1 plays back the time code (LTC) recorded in the longitudinal direction of a tape (not shown) obtained in the playback system of a digital video tape recorder with LTC recording. Playback L
It performs delay processing on the TC signal, and the above-mentioned playback LT
A C signal is supplied from a signal input terminal (1) to a memory circuit (2) and an edge detection circuit (3).

The edge detection circuit (3) performs a double edge detection operation of detecting a rising edge and a falling edge of the reproduced LTC signal. For example, as shown in FIG. An edge detection output pulse is formed at each timing of a falling edge. The edge detection output pulse obtained by the edge detection circuit (3) is supplied to the malfunction detection circuit (4) and is also sent to the reset terminal of the edge interval measurement counter (6) and the gate via the AND gate circuit (5). It is supplied to the load terminal of the control counter (7) and each latch terminal of the 1/4 arithmetic processing circuit (8) and the 3/4 arithmetic processing circuit (9).

The edge interval measurement counter (6) is the regenerated LTC.
A clock CK having a frequency that ensures acceptable accuracy for the time axis fluctuation component of the signal is supplied to the clock terminal, and the clock GK is added and counted.

This edge interval measurement counter (6) is reset at each timing of the rising edge and falling edge of the reproduced LTC signal by the edge detection output pulse supplied via the AND gate circuit (5).
By adding and counting the clock CK, the edge interval of the reproduced LTC signal is measured. The count output data from the edge interval measurement counter (6) is calculated by the 1/4 arithmetic processing circuit (8) and the 3/4 arithmetic processing circuit (8).
It is supplied to each data terminal of the four arithmetic processing circuits (9), and the first and second coincidence detection circuits (10), (
11).

The 1/4 arithmetic processing circuit (8) and the 3/4 arithmetic processing circuit (9) use the edge detection output pulse supplied via the AND gate circuit (5) to detect the rising edge and The count output data from the edge interval measurement counter (6) is latched at each falling edge timing, and 1/4 and 3/3 of the value is latched.
Calculate 4.

Here, the count output data obtained by the front edge-to-edge corner measurement counter (6) at each timing of the rising edges, 7 edges and falling edges of the reproduced LTC signal is as follows:
It shows the edge interval of the reproduced LTC signal.

1/4 of the above for each edge timing of the above reproduced LTC signal.
The calculation output data indicating a value of 1/4 of the edge interval of the reproduced LTC signal calculated by the calculation processing circuit (8) is supplied to the first coincidence detection circuit (10).

Further, the reproduction LT calculated by the 3/4 arithmetic processing circuit (9) at each edge timing of the reproduction LTC signal
Calculation output data indicating the value of 3/4 of the edge interval of the C signal is supplied to the second coincidence detection circuit (11), and is also supplied to the data terminal of the gate control counter (7). .

The gate control counter (7) has the same clock CK as the edge interval measurement counter (6) supplied to its clock terminal, and performs subtraction counting on the clock CK. This gate control counter (7) outputs calculation output data indicating a value of 374 of the edge interval of the regenerated TC signal calculated by the 3/4 arithmetic processing circuit (9) at every edge timing of the regenerated LTC signal. A counting operation is performed by subtracting the clock GK from this value, and the borrow output is applied as a gate control signal to the AND gate circuit (5) via the OR gate circuit (14).

The borrow output of the gate control counter (7) is
By using the gate control signal of the D gate circuit (5), during the normal operation period of the delay processing circuit of this embodiment, the rising edge and the falling edge of the reproduced LTC signal detected by the edge detection circuit (3) are controlled. For Etsuji,
As shown in FIG. 2, the edge pulse of 2T11iIM passes through the AND gate circuit (5).

Further, the first coincidence detection circuit (10) performs a coincidence detection operation between the count output data obtained by the edge interval measurement counter (6) and the calculation output data by the 1/4 calculation processing circuit (8). and use the edge spacing measurement counter (
A coincidence detection output pulse is output at every timing when the count output data obtained in step 6) coincides with a value of 1/4 of the edge interval of the reproduced LTC signal. Further, the first coincidence detection circuit (11) is configured to detect the edge interval measurement counter (6).
) and the calculation output data by the 3/4 calculation processing circuit (9), and the calculation output data obtained by the edge interval measurement counter (6) is used as the reproduction LTC. 3/4 of signal edge spacing
A match detection output pulse is output at each timing that matches the value of .

and the first and second coincidence detection circuits (10);
Each coincidence detection output pulse obtained in (11) is supplied to the clock terminal of the address counter (16) and the write/read control terminal of the memory circuit (2) via the OR gate circuit (15). , is supplied to the malfunction detection circuit (4).

The address counter (16) is preset with offset data corresponding to the playback speed of the tape, and the first and second coincidence detection circuits (to), (1) calculate the address value given by the offset data.
Address data is formed by counting each defeat detection output pulse supplied from 1) through the OR gate circuit (15) as a clock, and this address data is sent to the address terminal of the memory circuit (2). It is designed to be given to

The memory circuit (2) includes the first and second coincidence detection circuits (10) and (11) to the OR gate circuit (
The address indicated by the address data given by the address counter (16) is accessed using each loss detection output pulse supplied via the address counter (16) as a write/read control signal, and the address indicated by the address data given by the address counter (16) is accessed to read out the reproduction LTC signal. Writing and reading are performed.

A reproduction L that gives the reproduction LTC signal a delay amount corresponding to the reproduction speed for the tape indicated by the offset data preset in the address counter (16).
The TC signal is read from the memory circuit (2), and the delayed reproduced LTC signal is output from the signal output terminal (17).

Further, the malfunction detection circuit (4) is set by an edge detection pulse from the edge detection circuit (3), as shown in FIG. 3, for example, and the first and second coincidence detection circuits (10), (11) to the above OR gate circuit (1
The SR rough flip-flop circuit (4A) is reset by each loss detection output pulse supplied through the circuit 5), and the output of this SR79717071 circuit (4A) is converted into an edge detection pulse by the edge detection circuit (3). The latch circuit (4B) latches the latch circuit (4B).
The latch output from B) is sent to the AND gate circuit (5) as a gate control signal via the OR gate circuit (14).
).

This malfunction detection circuit (4) applies an edge pulse (P) to the reproduced LTC signal as shown by the broken line in FIG.
If an error occurs at position o), the third of the subsequent edge pulses is passed through the AND gate circuit (5), and the edge interval is measured using the third pulse (P, ). By resetting the counter (6) and loading the calculation output data from the 3/4 calculation processing circuit (9) into the gate control counter (7), the fourth pulse (P4) is added to the AND gate. A gate control signal is formed to pass through the circuit (5). In the delay processing circuit of this embodiment, the edge interval measurement counter (6) is reset by the fourth pulse (P4), and the calculation output data from the 3/4 calculation processing circuit (9) is transferred to the gate. By loading the control counter (7), normal delay processing operation is restored.

H8 Effects of the Invention In the time code signal delay processing circuit according to the present invention, the time code (LTC) recorded in the longitudinal direction of the tape is
) can be given a delay amount corresponding to the reproduction speed with respect to the tape by the memory means.

Therefore, by applying the present invention, in a digital video tape recorder that performs LTC recording, it is possible to specify editing points with high precision using the time code played back from the tape and perform editing work including variable speed playback mode. .

(16) Address counter (17)
・・・・・・Signal output terminal

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a time code signal delay processing circuit according to the present invention, FIG. 2 is a time chart for explaining the operation of the delay processing circuit, and FIG. 3 is a block diagram showing the configuration of a time code signal delay processing circuit according to the present invention. FIG. 4 is a block diagram showing the configuration of the malfunction detection circuit, and FIG. 4 is a time chart for explaining the operation of the malfunction detection circuit. (1)...Signal input terminal (2)...Memory circuit

Claims (1)

[Scope of Claims] A memory means to which a reproduced time code signal obtained by reproducing the time code recorded in the longitudinal direction of the tape is supplied; and an edge detection means for detecting rising edges and falling edges of the reproduced time code signal. , a measurement counter means for measuring the interval between each edge detected by the edge detection means; and 1/1/2 of the edge interval measured by the measurement counter means.
4 position timing and 3/4 position timing, and offset data corresponding to the playback speed for the tape are preset, and the output pulses detected by the timing detection means are counted and the address of the memory means is stored. A delay processing circuit for a time code signal, comprising: address generation counter means for forming data, and wherein the memory means gives the reproduced time code signal a delay amount corresponding to the reproduction speed with respect to the tape.