JPH02179680A - Self-test circuit for picture display device - Google Patents

Abstract

PURPOSE:To surely self-test a picture display device by providing a detecting circuit which detects whether an external input signal is present or not and a switch circuit which switches a horizontal deflecting flyback pulse signal of the picture display device as an artificial video signal at the time of detecting the absence of the input signal by the detecting circuit. CONSTITUTION:It is detected by a detecting circuit 9 whether the input signal from an external signal source is present or not. A switch circuit 11 is provided which outputs the horizontal deflecting flyback pulse signal of the picture display device as the artificial video signal only when the no-input state of the input signal is detected by the circuit 9. A clamp pulse generating circuit 27 is provided to which a synchronizing signal related to the input signal is inputted and from which a clamp pulse signal is outputted, and the circuit 11 stops the output of the artificial video signal when the circuit 9 detects the external input signal. When the circuit 9 detects the signal no-input state. The artificial clamp pulse signal synchronized with the horizontal deflecting flyback pulse signal is outputted from an artificial clamp pulse generating circuit 23, and the artificial video signal is subjected to clamp processing by the artificial clamp pulse signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a self-test circuit for an image display device.
A personal computer (hereinafter referred to as a personal computer)
The present invention relates to a self-test circuit suitable for an image display device connected to a main body via a signal cable and using a cathode ray tube (CRT) display as one image display element.

[Conventional technology]

This type of image display device l is used in combination with a personal computer body 3, for example as shown in Figure 2, and a video signal inputted from the personal computer body 3 via a signal cable (hidden and invisible) is amplified by a video amplification circuit. In addition to driving the cathode of the CRT display 5, a clamp pulse signal is also generated from the horizontal synchronizing pulse signal input through the signal cable, and the clamp circuit clamps the video signal applied to the CRT display 5 to adjust the DC level of the video signal. It has a configuration that aligns the

[Problem to be solved by the invention]

However, the above-described image display device 1 does not transmit the video signal to the CRT display 5 for some reason during operation.
If the display is no longer displayed, it is difficult to determine whether there is a failure on the personal computer 3 side, a disconnection or disconnection of the signal cable, or a failure on the image display device 1 side, which is inconvenient.

The present invention has been made to solve these conventional drawbacks, and an object of the present invention is to provide a self-test circuit that can independently and easily check the operation of an image display element on the side of an image display device.

[Means to solve the problem]

In order to solve such problems, the present invention provides a detection circuit that detects the presence or absence of an input signal from an external signal source, and a horizontal deflection of an image display device only when the detection circuit detects the absence of the input signal. It is configured by forming a switch circuit that switches and outputs the flyback pulse signal as a pseudo video signal.

In addition to such a configuration, the present invention also provides a clamp pulse generation circuit that inputs a synchronization signal related to the input signal and outputs a clamp pulse signal.

It may also be configured to include a pseudo clamp pulse generation circuit that generates and outputs a pseudo clamp pulse signal from the horizontal deflection flyback pulse signal only when the detection circuit detects no input.

Further, a waveform shaping circuit is provided for shaping the horizontal deflection flyback pulse signal and outputting a shaped pulse signal to the switch circuit and the pseudo-clamp pulse generation circuit, and the pseudo-clamp pulse generation circuit is configured to control the operation of the switch circuit. It is also possible to have a configuration in which the level of the shaped pulse signal that changes accordingly is compared, and when the level exceeds a predetermined level, the pseudo clamp pulse is output.

[For production]

In the present invention equipped with such means, when the detection circuit detects no input of a video signal from an external signal source, the switch circuit switches and outputs the horizontal deflection flyback pulse signal of the image display device as a pseudo video signal. The image is then displayed on five image display elements.

On the other hand, when the detection circuit detects an input signal from an external signal source, the switch circuit suppresses the output of the pseudo video signal.

In addition, in a configuration having a pseudo clamp pulse generation circuit and a clamp pulse generation circuit, when the detection circuit detects no signal input from an external signal source, the pseudo clamp pulse generation circuit generates a pseudo clamp synchronized with the horizontal deflection flyback pulse signal. The pulse signal is output, and the pseudo video signal can be clamped with the pseudo clamp pulse signal. On the other hand, in the state where the input signal is detected, the clamp pulse signal is output from the clamp pulse generation circuit instead of the pseudo clamp pulse generation circuit, It becomes possible to clamp the input video signal from an external signal source.

Furthermore, in a configuration in which the shaped pulse signal from the waveform shaping circuit is added to the pseudo clamp pulse generation circuit and the switch circuit, and the pseudo clamp pulse generation circuit is provided with a comparison function, the shaped pulse signal changes depending on the operation of the switch circuit. A pseudo clamp pulse generation circuit outputs a pseudo clamp pulse according to the level.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a self-test circuit according to the present invention.

A signal cable from an external signal source such as a personal computer (not shown) is connected to the first input terminal 7.

It is connected to the gate of an FET type transistor Q1 via a resistor R1. Symbol R1 is a bias resistor.

The drain of transistor Q1 is grounded and the source is connected to FE.
T-type transistor Q! It is connected to the gate of
It is connected to power supply B via resistor R3.

The drain of the transistor Q2 is grounded, and the source is connected to the voltage source 71B via a resistor R4.

These transistors Q1 and Q form a detection circuit 9 that detects the presence or absence of an input signal at the first input terminal 7.

The source of transistor Q2 is connected to capacitor C and resistor R.
Transistor Q through a series circuit of 5.

A resistor R8 is connected to the collector of the transistor Q3, and the emitter is connected to the power supply B. The transistor Q3 forms a switch circuit 11 for switching the output of a shaped pulse signal, which will be described later. Symbol R7 is a bias resistor.

Three backflow prevention diodes DI, D2, and D3 are forwardly connected to the resistor R6 connected to the collector of the transistor Q, and the first diodes DI, D2, and D3 are connected to the resistor R6 connected to the collector of the transistor Q, respectively. Second. Third output terminal 13,1
5.17 is connected.

Resistors R@, R9+ Rra are terminating resistors.

These first to third output terminals 13, 15.17 are connected to a video amplification circuit of an image display device (not shown).

A horizontal deflection flyback pulse signal is applied to the second input terminal 19 from the primary side or secondary side of the flyback transformer in the image display device.

A resistor R11 is connected to the second input terminal 19,
The cathode of a Zener diode D4 whose anode side is grounded is connected between the output side of this resistor R11 and the ground.
These resistor R11 and Zener diode D4 form a waveform shaping circuit 21 that clips the horizontal deflection flyback pulse signal and shapes it into a rectangular waveform.

The connection point P2 between the resistor R11 and the Zener diode D4 is
It is connected to the pseudo clamp pulse generation circuit 23 and also to the source of the transistor Q3, ie, the 21st point, via a resistor R12.

Therefore, the horizontal deflection flyback pulse signal applied to the second input terminal 19 is waveform-shaped by the waveform shaping circuit 21 and can be input to the base of the pseudo clamp pulse generation circuit 23 and the transistor Q.

The pseudo clamp pulse generation circuit 23 is made of 2, for example, C-MOS.
(Complementary Metal 0xi
It consists of an oscillation circuit such as a mono-multi circuit using a semi-cond-ductor type semiconductor, and outputs a pseudo-clamp pulse signal synchronized with the shaped pulse signal from the waveform shaping circuit 21 to the fourth output terminal 25.

It also has a function to output a pseudo clamp pulse signal when the shaping pulse signal level at 22 points is below a predetermined level, for example a threshold voltage, but not to output a pseudo clamp pulse signal when it is above a predetermined level. There is.

The clamp pulse generation circuit 27 inputs a horizontal synchronization signal transmitted through a signal cable from the personal computer main body, and generates a fourth clamp pulse signal synchronized with the horizontal synchronization signal.
It has a conventionally known configuration in which the clamp pulse signal is output to the output terminal 25 of the computer, and the clamp pulse signal is not output when the horizontal synchronization signal from the personal computer body is not input.

Note that the circuit configurations of the video amplification system, horizontal deflection system, vertical deflection system, and CRT display in the image display device (not shown) are the same as those of the conventional art.

Next, the operation of the self-test circuit of the present invention configured as described above will be explained.

For example, if the signal cable from the computer is not connected and the first input terminal 7 is set to rHJ by the image display device 9.
Assuming that it is at the level.

The transistor Ql of the detection circuit 9 is turned on, and the transistor Q2 is turned off.

On the other hand, the horizontal deflection flyback pulse signal applied to the second input terminal 19 is waveform-shaped by the waveform shaping circuit 21, and the shaped pulse signal is output to the pseudo clamp pulse generation circuit 23 and passed through the resistor R12 to P1.
added to the point.

Since transistor Q2 is in the OFF state, the shaped pulse signal is applied to the base of transistor Q through capacitor C and resistor R5.

A diode Dl connected to the collector via a resistor R.
, D, , the first to third output terminals 13.15 through D3.
．． 17 as an RGB pseudo video signal.

Therefore, the pseudo video signals from the first to third output terminals 13.15.degree. 17 are amplified by the video amplification circuit in the nine-image display device and drive, for example, the cathode of the CRT display.

On the other hand, the shaped pulse signal level at 22 points is as follows.

Transistor Q! Since the source is not at the ground potential, the level is higher than the predetermined level, so the pseudo clamp pulse generation circuit 23 oscillates a pseudo clamp pulse signal synchronized with the shaped pulse signal and outputs it to the fourth output terminal 25. .

At this time, the clamp pulse generating circuit 27 does not output a clamp pulse signal because no horizontal synchronizing signal is input from the personal computer main body side.

Therefore, the pseudo video signals output from the first to third output terminals 13, 15, 17 are clamped by a predetermined clamp circuit, and converted into video signals with uniform DC signal levels.
A single color image is displayed by driving the RT display, and the operating status of the CRT display can be confirmed even when the signal cable is not connected.

Note that by varying the levels of the pseudo video signals output from the first to third output terminals 13, 15, and 17, it is possible to display two different color single images.

Next, when the signal cable is connected to the image display device from the personal computer side and the first input terminal 7 becomes rLJ level, transistor Q1 becomes OFF state, transistor Q2 becomes ON state, and the source of transistor Q2 is grounded. Changes in potential.

Therefore, the shaped pulse signal from the waveform shaping circuit 21 is
Since it is not output to one point and is not output from the collector of the transistor Q3, the pseudo video signal is not output from the first to third output terminals 13, 15, and 17.

Note that the circuit configuration on the personal computer main body side must be configured so that the first input terminal 7 is at the rLJ level when the signal cable is connected.

On the other hand, in the pseudo clamp pulse generation circuit 23, +P
Since one point becomes the ground potential and the shaping pulse signal level at the +P2 point becomes a signal level determined mainly by the voltage division ratio of the resistors R11+R12 and decreases, no pseudo clamp pulse signal is output.

On the other hand, since the clamp pulse generation circuit 27 outputs an original clamp pulse signal from the second output terminal 25 based on the horizontal synchronization signal from the signal cable, the video signal from the signal cable is not transmitted from the clamp pulse generation circuit 27. It is separately clamped using a clamp pulse signal and drives a CRT display.

Second, the object of the present invention can be achieved even with a configuration in which the pseudo clamp pulse generation circuit 23 and the clamp pulse generation circuit 27 of the above-described embodiments are omitted.

However, by providing the pseudo clamp pulse generation circuit 23 and the clamp pulse generation circuit 27, the pseudo video signal and the external input video signal can be accurately clamped, and the video display quality can be maintained in good condition. The pseudo-clamp pulse generation circuit 23 is not limited to an example formed of a C-MOS type semiconductor circuit, but in a C-MOS type semiconductor circuit, the shift hold voltage tends to be located approximately in the middle of the applied power supply voltage. Therefore, if a C-MOS type semiconductor circuit is used for the pseudo clamp pulse generation circuit 23, the P! It becomes easy to accurately compare and detect changes in the level of the shaped pulse signal at a point, and the output of the pseudo clamp pulse signal becomes accurate.

Note that the present invention is not limited to displaying images of color video signals, but can also be implemented to displaying monochrome video signals.

〔Effect of the invention〕

As explained above, the present invention includes a detection circuit that detects the presence or absence of an input signal from an external signal source, and a detection circuit that switches the horizontal deflection flyback pulse signal of the image display device as a pseudo video signal only when the signal is not input. Since it is configured by forming a switch circuit for outputting, it can be used when the signal cable is disconnected from the two-image display device or when the computer main body etc. is in a malfunction state.

Since a pseudo video signal is generated to operate the CRT display, it is possible to easily check the operation of a single image display device.

Further, in a configuration that includes a clamp pulse generation circuit and a pseudo clamp pulse generation circuit in addition to such a configuration, it is possible to perform clamp processing of the pseudo video signal using the pseudo clamp pulse signal, and a good pseudo video display can be performed.

Furthermore, in a configuration that includes a waveform shaping circuit and in which the pseudo clamp pulse generating circuit outputs a pseudo clamp pulse by comparing the level of a shaped pulse signal that changes depending on the operation of the switch circuit, the signal cable becomes disconnected. In addition to the above-mentioned effects, the present invention has the advantage that automatic and more reliable self-testing can be ensured when the personal computer or the like is in a malfunctioning state.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a self-test circuit for an image display device according to the present invention, and FIG. 2 is a diagram illustrating an overview of the image display device. ■・・・・・・・・・・・・・・・・・・・・・ Image display device 3・・・・・・・・・・・・・・・・・・・・・
External signal source (computer main unit) 5...
......Image display element (CRT display) 7.19...1. Second input terminal 9......Detection circuit 11......・
Switch circuit 13.15.17.25...1st to 4th
Output terminal 21 of...
・・・Waveform shaping circuit 23・・・・・・・・・・・・・・・
...Pseudo clamp pulse generation circuit 27...
・・・・・・・・・・・・・・・・・・ Clamp pulse generation circuit C・・・・・・・・・・・・・・・・・・・・・
...Capacitor DI, D2. D-co...diode

Claims (3)

[Claims] (1) A detection circuit that detects the presence or absence of an input signal from an external signal source, and only when this detection circuit detects a non-input state of the input signal, uses the horizontal deflection flyback pulse signal of the image display device as a pseudo video signal. A self-test circuit for an image display device, comprising: a switch circuit for switching output; (2) a clamp pulse generation circuit that inputs a synchronization signal related to the input signal and outputs a clamp pulse signal, and generates a pseudo clamp pulse signal from the horizontal deflection flyback pulse signal only when the detection circuit detects a no-input state; The self-test circuit for an image display device according to claim 1, further comprising: a pseudo-clamp pulse generation circuit that generates and outputs a pseudo-clamp pulse. (3) a waveform shaping circuit that shapes the horizontal deflection flyback pulse signal and outputs a shaped pulse signal to the switch circuit and the pseudo-clamp pulse generation circuit; the pseudo-clamp pulse generation circuit is connected to the switch circuit; 2. A self-test circuit for an image display device according to claim 1, wherein the level of said shaped pulse signal that changes according to the operation of said shaped pulse signal is compared, and said pseudo clamp pulse is output when said shaped pulse signal level exceeds a predetermined level. .