JPH0217845U - - Google Patents

Info

Publication number
JPH0217845U
JPH0217845U JP9680588U JP9680588U JPH0217845U JP H0217845 U JPH0217845 U JP H0217845U JP 9680588 U JP9680588 U JP 9680588U JP 9680588 U JP9680588 U JP 9680588U JP H0217845 U JPH0217845 U JP H0217845U
Authority
JP
Japan
Prior art keywords
semiconductor package
semiconductor
specifications
housed
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9680588U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9680588U priority Critical patent/JPH0217845U/ja
Publication of JPH0217845U publication Critical patent/JPH0217845U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案に係る半導体パツケージの一
例を示す平面図、第2図はこの考案に係る半導体
パツケージの他の例を示す平面図、第3図はこの
考案に係る半導体パツケージを適用したICをプ
リント基板に実装した状態を示す斜視図、第4図
は従来の半導体パツケージを示す平面図、第5図
は従来の半導体パツケージを適用したICをプリ
ント基板に実装した斜視図である。 1,1A……半導体パツケージ、2……接続ピ
ン、3……凹部、10……IC、20……プリン
ト基板、G……グランド、Vcc……電源。
FIG. 1 is a plan view showing an example of a semiconductor package according to this invention, FIG. 2 is a plan view showing another example of a semiconductor package according to this invention, and FIG. 3 is an IC to which the semiconductor package according to this invention is applied. FIG. 4 is a plan view showing a conventional semiconductor package, and FIG. 5 is a perspective view showing an IC mounted on a printed circuit board using the conventional semiconductor package. 1, 1A... Semiconductor package, 2... Connection pin, 3... Recess, 10... IC, 20... Printed circuit board, G... Ground, Vcc... Power supply.

Claims (1)

【実用新案登録請求の範囲】 チツプなどの半導体素子等が収納された半導体
パツケージにおいて、 上記半導体パツケージの表面若しくは裏面に、
その内部機能、仕様などに関する表示がなされた
ことを特徴とする半導体パツケージ。
[Scope of claim for utility model registration] In a semiconductor package in which a semiconductor element such as a chip is housed, on the front or back surface of the semiconductor package,
A semiconductor package characterized by displaying information regarding its internal functions, specifications, etc.
JP9680588U 1988-07-21 1988-07-21 Pending JPH0217845U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9680588U JPH0217845U (en) 1988-07-21 1988-07-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9680588U JPH0217845U (en) 1988-07-21 1988-07-21

Publications (1)

Publication Number Publication Date
JPH0217845U true JPH0217845U (en) 1990-02-06

Family

ID=31321914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9680588U Pending JPH0217845U (en) 1988-07-21 1988-07-21

Country Status (1)

Country Link
JP (1) JPH0217845U (en)

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