JPH021782U - - Google Patents

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Publication number
JPH021782U
JPH021782U JP7860888U JP7860888U JPH021782U JP H021782 U JPH021782 U JP H021782U JP 7860888 U JP7860888 U JP 7860888U JP 7860888 U JP7860888 U JP 7860888U JP H021782 U JPH021782 U JP H021782U
Authority
JP
Japan
Prior art keywords
input
output
mode
signals
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7860888U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7860888U priority Critical patent/JPH021782U/ja
Publication of JPH021782U publication Critical patent/JPH021782U/ja
Pending legal-status Critical Current

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は第1の考案の一実施例を示す構成ブロ
ツク図、第2図は計器前面の構成図、第3図は動
作を説明するフローチヤートである。第4図は第
2の考案の一実施例を示す構成斜視図、第5図は
第4図の装置の構成ブロツク図、第6図はキーボ
ードを介して多点人出力装置の入力作業をする場
合の説明図である。第7図は従来装置の構成ブロ
ツク図、第8図は多点入出力装置の正面図である
。 10……接点スイツチ、24……発光ダイオー
ド、26……信号処理回路、41……判定回路、
42……モード判別回路、50……端子台、70
……CPUユニツト。
FIG. 1 is a block diagram showing an embodiment of the first invention, FIG. 2 is a front diagram of the instrument, and FIG. 3 is a flowchart explaining the operation. FIG. 4 is a perspective view of the configuration of an embodiment of the second invention, FIG. 5 is a block diagram of the configuration of the device shown in FIG. FIG. FIG. 7 is a block diagram of a conventional device, and FIG. 8 is a front view of a multi-point input/output device. 10... Contact switch, 24... Light emitting diode, 26... Signal processing circuit, 41... Judgment circuit,
42...Mode discrimination circuit, 50...Terminal block, 70
...CPU unit.

Claims (1)

【実用新案登録請求の範囲】 (1) 複数の入出力信号と一対一に設けられ当該
信号の導通状態を表示する発光素子と、 前記入出力信号が入力信号の場合は当該入力信
号を読込んで指示されたタイミングでバスに出力
し、出力信号の場合は指示されたタイミングでバ
スからデータを読込んで出力端に出力する信号処
理回路と、 当該信号処理回路と前記バスとの情報の授受を
仲介するタイミングの指示を行うバスインタフエ
イス回路と、 を備えた多点入出力装置の表示装置において、 前記発光素子のみ若しくはこれに他の発光素子
を追加して縦3列横5行以上のドツトマトリクス
状に配置した表示部と、 前記入出力信号が正常であるか異常であるか判
定する手段と、 この判定手段で異常と判定した場合、若しくは
前記バスインタフエイス回路を介して通常の表示
モードから正常/異常状態の切替えが指示された
ときは当該表示部に異常状態である旨の表示をす
るモードと、これ以外の場合は前記発光素子を用
いて入出力信号の導通状態を表示するモードとす
るモード判別回路と、 を具備することを特徴とする多点入出力装置の
表示装置。 (2) 請求項1記載の発光素子、信号処理回路、
バスインタフエイス回路、表示部及び外部からの
指示にしたがつて当該表示部の動作を切替えるモ
ード判別回路よりなる多点入出力装置を前記表示
部が一列となる状態で複数組合せた入出力システ
ムと、 これら多点入出力装置のバスインタフエイス回
路を介して、各モード判別回路に指示を送ると共
に、入出力にかかる制御を行う制御部と、 よりなり、当該制御部の指示により前記一列の
表示部を用いて文字列を表示することを特徴とす
る多点入出力装置の表示装置。
[Claims for Utility Model Registration] (1) A light-emitting element that is provided in one-to-one correspondence with a plurality of input/output signals and displays the conduction state of the signals, and if the input/output signals are input signals, reads the input signals. A signal processing circuit that outputs data to the bus at the specified timing, and in the case of an output signal, reads data from the bus at the specified timing and outputs it to the output terminal, and mediates the exchange of information between the signal processing circuit and the bus. A display device for a multi-point input/output device, comprising: a bus interface circuit that instructs the timing of the light emitting device; a display section arranged in a shape, a means for determining whether the input/output signal is normal or abnormal, and a means for determining whether the input/output signal is normal or abnormal; When switching between normal/abnormal state is instructed, there is a mode in which an abnormal state is displayed on the display section, and in other cases, a mode in which the conduction state of the input/output signal is displayed using the light emitting element. 1. A display device for a multi-point input/output device, comprising: a mode discriminating circuit for determining a mode; (2) the light emitting element and signal processing circuit according to claim 1;
An input/output system in which a multi-point input/output device consisting of a bus interface circuit, a display section, and a mode discrimination circuit that switches the operation of the display section according to instructions from the outside is combined with a plurality of the display sections arranged in a row. , a control unit that sends instructions to each mode discrimination circuit through the bus interface circuit of these multi-point input/output devices and controls input/output; 1. A display device for a multi-point input/output device, characterized in that a character string is displayed using parts.
JP7860888U 1988-06-14 1988-06-14 Pending JPH021782U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7860888U JPH021782U (en) 1988-06-14 1988-06-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7860888U JPH021782U (en) 1988-06-14 1988-06-14

Publications (1)

Publication Number Publication Date
JPH021782U true JPH021782U (en) 1990-01-08

Family

ID=31303521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7860888U Pending JPH021782U (en) 1988-06-14 1988-06-14

Country Status (1)

Country Link
JP (1) JPH021782U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59156356A (en) * 1983-02-25 1984-09-05 株式会社 笠井仏檀工芸 Working mask

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5816317A (en) * 1981-07-21 1983-01-31 Fuji Electric Co Ltd Input and output module
JPS5876097A (en) * 1981-10-29 1983-05-09 Iwata Kagaku Kogyo Kk Preparation of gluconic acid by immobilized fungus
JPS59125775A (en) * 1983-01-07 1984-07-20 富士電機株式会社 Display

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5816317A (en) * 1981-07-21 1983-01-31 Fuji Electric Co Ltd Input and output module
JPS5876097A (en) * 1981-10-29 1983-05-09 Iwata Kagaku Kogyo Kk Preparation of gluconic acid by immobilized fungus
JPS59125775A (en) * 1983-01-07 1984-07-20 富士電機株式会社 Display

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59156356A (en) * 1983-02-25 1984-09-05 株式会社 笠井仏檀工芸 Working mask

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