JPH02177718A - Dynamic latch bus driver - Google Patents

Abstract

PURPOSE:To evade erroneous data from being caused in the case of fetching the data by connecting an input of a CMOS inverter to a bus line, connecting its output to a gate of a P-channel enhancement MOS transistor(TR) and connecting its drain output to the bus line. CONSTITUTION:A precharge signal 7 is supplied to a MOS TR 2 to turn on the P-channel enhancement MOS TR 2. Then a voltage source VDD is applied to a load capacitor 9, which is charged up to the VDD level. Thus, a TR 5 is turned on and the level VDD is always supplied to the bus line 6. Even when the bus line is brought into a level VSS by a coupling capacitor in existence between wires such other bus line, since the bus line is boosted to the level VDD at a speed in response to the current capability of the P-channel enhancement MOS TR 5, no erroneous data is caused at the time of fetching data.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF CA APPLICATION] The present invention relates to a dynamic holding type bus driver, and particularly to a dynamic holding type bus driver for a CMOS semiconductor integrated circuit.

[Prior Art] FIG. 3 is a circuit diagram showing a conventional example of a dynamic holding type bus driver.

In this bus driver, a precharge signal 7, which is a gate bias voltage for turning on a P-channel enhancement MOS transistor 2, is applied in advance, and a voltage source VDD is applied to a load capacitor 9, so that the load capacitor 9 is set to the VDD potential. Charge up to. After that, the P-channel enhancement MOS transistor 2 is turned off, but the bus line 6 is set to VDD due to the amount of charge in the load capacitor 9.
held at a potential. After that, the data selection signal 8 is applied to the gate of the N-channel enhancement MOS transistor 3, and the N-channel enhancement MOS
When the transistor 3 is turned on, the bus line 6 is held at the vSS potential, and when the transistor 3 is turned off, the bus line 6 is held at the VDD potential.

The potential of this pie line 6 is received by a CMOS inverter 10 connected to the bus line 6 and transmitted as data.

Problems to be solved by the invention C] The above-mentioned conventional dynamic retention type bus driver has the following problems:
The bus line is held at the VDD potential in advance, and then no potential is supplied, and no potential is supplied when the bus line is treated as data at the VDD potential, so as shown in FIGS. 4 and 5. When multiple data lines are wired in parallel, the first bus line 11, the second
bus line 12 and third bus line 13 are at VDD potential, and at time t1, the first bus line 11 and the third bus line 13 are at VDD potential.
When the second bus line 13 changes to the vSS potential, the second bus line 12 originally holds the VDD potential and the receiving side CM
The OS inverter 10 that should output the VSS potential is
Coupling capacitance between bus line wiring 15 (in this case,
(considered as a lumped constant), the first bus line 11
and the third bus line 13 is VSS at time 1+.
Following the change in the potential, the potential of the second bus line 12 is also pulled in the direction of the vSS potential, so the CM on the receiving side
If the OS inverter 10 senses that the input is at the vSS potential, there is a drawback that the VDD potential, which is erroneous data, will be output as the output.

[Means for Solving the Problems] A dynamic holding type bus driver of the present invention includes a CMOS inverter whose input is connected to a bus line, and the CMOS inverter whose input is connected to a bus line.
It has a P-channel enhancement MOS in which the output of the MOS inverter is connected to the gate and the bus line is connected to the train.

[Operation] When the bus line holds the VDD potential, the output of the CMOS inverter becomes the SS potential, and the P-channel transistor is turned on, so that the bus line is always given the VDD potential.

Therefore, even if the bus line is pulled to ■SS potential due to coupling capacitance between wiring such as other bus lines,
Since the bus line is pulled up to the VDD potential at a speed corresponding to the current capacity of the P-channel enhancement MOS transistor, erroneous data will not be obtained when data is taken in.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of a dynamic holding type bus driver of the present invention, and FIG. 2 is an explanatory diagram of its operation.

The dynamic holding type bus driver of this embodiment has a third
In the conventional example shown in the figure, there is a CMOS inverter 4 whose input is connected to the bus line 6, a P-channel type in which the gate is connected to the output of the CMOS inverter 4, the source is connected to the power supply terminal 1, and the train is connected to the bus line 6. It has an enhancement MOS transistor 5.

Next, the operation of this embodiment will be explained.

By applying a precharge signal 7, which is a gate bias voltage for turning on the P-channel enhancement MOS transistor 2, to the MOS transistor 2, and applying a voltage source VDD to the load capacitor 9, the load capacitor 9 is
Charge to VDD potential. Therefore, bus line 6
becomes VDD potential, and the output of CMOS inverter 4 is v
Since it is at SS potential, P channel type enhancement M
The S transistor 5 is turned on, and the bus line 6 is always supplied with the VDD potential.

After that, a data selection signal 8 is applied to the gate of the P-channel enhancement MOS transistor 3, and if β of the N-channel enhancement MOS transistor 2 is β, then β8
>βP, the bus line 6 is pulled toward the vSS potential, the output of the CMOS inverter 4 is inverted, the P-channel enhancement MOS transistor 5 is turned off, and the bus line 6 is at the SS potential. Furthermore, if the N-channel enhancement MOS transistor 3 is turned off by the data selection signal 8, the bus line 6 is held at the VDD potential.

However, in order to suppress the through current when the N-channel enhancement MOS transistor 3 and the P-channel enhancement MOS transistor 2 are turned on, β8) βP or βN (β) is desirable, and the N-channel enhancement MOS transistor 3 is turned on. Considering the speed for pulling the bus line 6 to the VSS potential, βN)βP is desirable.

However, considering the effects of the present invention, βP is required to raise the bus line 6 to the VDD potential by the time the data on the bus line 6 is taken in (
The larger the value, the better), and after considering the above three points, β
It is most effective to set N=7·βP.

[Effects of the Invention] As explained above, the present invention connects the input of a CMOS inverter to the bus line, connects the output of the CMOS inverter to the gate of the P-channel enhancement MO3I-transistor, and connects the input of the CMOS inverter to the bus line. By connecting the drain output of the MOS transistor to the bus line, when the bus line holds the VDD potential, the VDD potential is always supplied from the voltage source VDD, so that other bus lines, etc. as shown in FIG. Even if the bus line is pulled to the VSS potential due to the coupling capacitance between the wiring lines, as shown in FIG. This has the effect of preventing incorrect data from being generated when data is imported.

Note that although the above has only touched upon the potential drop due to the coupling capacitance between the bus line wirings, it goes without saying that the same effect can be had on the potential drop due to various external noises.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of an embodiment of the dynamic retention type bus driver of the present invention, Figure 2 is an explanatory diagram of the operation of the dynamic retention type bus driver circuit of Figure 1, and Figure 3 is a conventional dynamic retention type bus driver. FIG. 4 is a circuit diagram showing an example of the use of a conventional dynamic holding type bus driver circuit, and FIG. 5 is an explanatory diagram of the operation of the conventional dynamic holding type bus driver circuit of FIG. DESCRIPTION OF SYMBOLS 1... Power supply terminal, 2... P channel type enhancement MOS transistor, 3... N channel type enhancement MOS transistor, 4... CMOS inverter, 5... P channel type enhancement MO, S transistor, 6 ...Bus line, 7.Precharge signal, 8.Data selection signal, 9.Load capacitance, 10.CMOS inverter, 11.First bus line, 12.. 2nd bus line, 13...Third bus line, 14...Bus driver 15...Coupling capacitance between bus line wiring. Figure 2

Claims (1)

[Claims] 1. A dynamic holding bus driver for a CMOS semiconductor integrated circuit, comprising: a CMOS inverter having an input connected to a bus line; an output of the CMOS inverter having a gate connected to the bus line; and a drain connected to the bus line; A dynamic holding type bus driver characterized by having a P-channel type enhancement MOS.