JPS6240531A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To realize a high voltage and a high speed of the titled circuit by superposing a clock signal voltage, and executing a boot-strap, when transferring a carry signal from the lower bit to the upper bit. CONSTITUTION:As for a half-adding circuit A, whenever source data (a), (b) are inputted a clock signal phi which becomes a high level VCC at least during a transfer period of a carry signal is delayed by a prescribed time T0 by a delaying circuit 10, and thereafter, brought to a capacity coupling to a gate of a carry signal transfer use MOS transistor 2 by a MOS capacity 11. In this way, when an output point C of an exclusive OR circuit 1 becomes VCC, a voltage which has subtracted a threshold voltage Vth of the transistor 2 from VCC appears in the gate (point (d)) of the transistor 2. On the other hand, the clock signal phi is delayed by the prescribed time T0 by the delaying circuit 10, and supplied through the MOS capacitor 11, therefore, the gate potential of the transistor 2 is brought to a bootstrap, and becomes a high voltage.

Description

[Detailed Description of the Invention] [Summary] A semiconductor integrated circuit according to the present invention transmits a carry signal from a lower bit to an upper bit via a carry signal transmission signal transistor, and also transmits a carry signal from a lower bit to an upper bit via a carry signal transmission signal transistor, The voltage applied to the gate of the carry signal transmission transistor is increased by a clock signal voltage that is at a high level during the carry signal transmission period, and the number of bits to be calculated is Even when the number of bits increases, the carry signal can be transmitted to the upper bits at high speed.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that transmits a carry signal from a lower bit to an upper bit and is equipped with a predetermined arithmetic circuit for input source bits, and is used as a counter or an adder. be done.

[Conventional technology]

FIG. 3 illustrates the circuit configuration of a full adder circuit A' as an example of a conventional semiconductor integrated circuit of this type.

In FIG. 3, 1 and 5 are exclusive logic circuits, 2 is a carry signal transmission MO3) transistor that transmits a carry signal from the lower bit to the upper bit, 3, 4, 7 and 8 are inverters, and 6 is an AND gate. , 9 is an MO for transmitting the carry signal generated in the full adder circuit A' to the upper bits.
It is an S transistor.

A and b are source data (operated data) and are supplied to each input terminal of the exclusive logic circuit.

Now, suppose only one of the source data a or b is "1"
(high level) and the other is "0" (low level), the output of the exclusive logic circuit 1 (that is, the potential at point C) becomes "1", and the MOS transistor for transmitting the carry signal from the lower bit , Gate 9th position of Star 2 will be at a high level. Therefore, the MO3) transistor 2 is turned on and the carry signal Carry In from the lower bit is transferred to the upper bit. That is, depending on whether the carry signal Carry In from the lower bit is at a low level or a high level, the carry signal 9- transferred to the upper bit also becomes a low level or a high level. Note that the signals Carry In and Car
ry Out has no carry when they are at high level, but produces a carry when they are at low level, and is an inverted signal with respect to the carry signal.

On the other hand, the source data a and b are input to the AND gate 6, and the output side of the AND gate 6 becomes a low level, and therefore the output side of the inverter 7 becomes a high level. Further, as described above, when the potential at point C becomes high level, the output side of inverter 8 becomes low level, and therefore transistor 9 is turned off.

Further, the potential at the point C becomes "0" (low level) through the inverter 3 and is inputted to one input terminal of the exclusive logic circuit 5, and the other input terminal of the exclusive logic circuit 5 is supplied with the lower bit bit. A carry signal Carry In from is inputted through an inverter 4, so that the result of the operation in the full adder circuit A' is produced as an inverted signal 10 on the output side of the exclusive logic circuit 5. (In the above example, the output side of inverter 3 is "0", and if there is no carry from the lower bit, Carry Ir+ is at high level, so the output side of inverter 4 is also "0".
Therefore, the output signals of the exclusive logic circuit 5 also become "0", and the inverted "1" becomes the result of addition of the source data a and b in this full adder circuit A'. ) If the source data a and b are both "1" or both "0", the output of the exclusive logic circuit 1 (potential at point C) becomes "0" and the MOS transistor 2 The carry signal Car from the lower bit is turned off.
ry In is no longer transmitted to the upper bits.

When the source data a and b are both "1", the output side of the inverter 7 is at a low level, while the output side of the inverter 8 is at a high level, and the transistor 9 is turned on. The low level signal on the output side of is outputted as a carry signal Carry Out to the upper bit from the full adder circuit A'. That is, in this case, a carry-up is performed to the higher focus side.

Further, when the source data a and b are both "0", the output side of the inverter 7 is at a high level, while the output side of the inverter 8 is at a low level, and the transistor 9
is turned off, and the level of the carry signal Carry Out is set to the high level potential precharged in the transistor 9, and no carry is carried out to the upper bit side.

In either case, on the output side of the exclusive logic circuit 5, the result of the operation of the source data a and b in the full adder circuit A' is generated as an inverted signal.

[Problem that the invention seeks to solve]

However, in the conventional technology as described above, as the number of bits in the adder as a whole increases, the carry signal is transmitted to the MO3) transistor in each half adder circuit when transmitting the carry signal from the lower bit to the upper bit. You will have to go through 2 many times.

By the way, it costs MO3! - When laying out a transistor in a semiconductor integrated circuit, the larger the β of the transistor, the larger the layout pattern, and the larger the capacitance. There is a limit to the ease with which it can flow. Therefore, as described above, when the carry signal from the lower bit passes through several stages of the transistors, a considerable transmission time is required, resulting in a problem that the carry signal transmission is delayed.

The present invention has been made to solve this problem, and uses a clock signal that changes the voltage applied to the gate of the transmission transistor for the carry signal to a high level during the transmission period of the carry signal. Based on the idea of increasing the voltage using so-called bootstrap technology, the carry signal can be transmitted at high speed without making the pattern of the carry signal transmission transistor particularly large. It is.

[Means for solving problems]

In order to solve the above problems, the present invention transmits a carry signal from the lower bit to the upper bit via a carry signal transmission transistor, and also includes a predetermined arithmetic circuit for the input source bit. A semiconductor integrated circuit is provided in which the voltage applied to the gate of a carry signal transmission transistor is increased by a clock signal voltage that is at a high level during the transmission period of the carry signal.

[For production]

According to the above configuration, the high level voltage applied to the gate of the carry signal transmission transistor (as described above, when one of the source data a and b is "1" and the other is "0" This is caused by transmitting the carry signal from the lower bit to the upper bit through the transistor), but by using the clock signal voltage that is high level during the transmission period of the carry signal, the voltage is further increased using bootstrap technology. be converted into

〔Example〕

FIG. 1 shows the circuit configuration of a half-adder circuit A as an embodiment of the semiconductor integrated circuit according to the present invention. Each time source data a and b are input, the level is high at least during the transmission period of the carry signal. The clock signal φ (see FIG. 2(A)), which becomes Vcc, is delayed for a predetermined time To by the delay circuit 10.
After being delayed by (see FIG. 2C), the MOS capacitor 11 capacitively couples the gate of the carry signal transmission MOS transistor 2 (indicated by point d).

Note that the clock signal φ delayed by a predetermined time by the delay circuit 10 is capacitively coupled to the gate of the carry signal transmission MOS transistor 2 provided in each half adder circuit. Further, 12 is a MOS transistor inserted between the gate of the FiMOS transistor 2 (point d) and the output side (point 0) of the exclusive logic circuit 1, and the high potential charged at the point d is the 0 point. This prevents it from dropping by discharging towards the side. In FIG. 1, parts common to the conventional circuit shown in FIG. 2 are given the same reference numerals.

Now, if one of the source data a and b input to the exclusive logic circuit 1 is "1" and the other is rOJ, then the output side (0 point) of the exclusive logic circuit 1 is: A high level voltage as shown in FIG. 2(B) is generated. In this case, the potential at the 0 point on the output side becomes a predetermined high level with a delay of a predetermined time TO after the source data a and b are input.

The potential at the 0 point (approximately Vcc) thus generated is applied to the gate of the transistor 2 (point d) through the transistor 12 to which Vcc is applied.

(See period T in FIG. 2(D)).

Note that during this period, the voltage applied to the point d varies from the Vcc to the threshold voltage vth of the transistor 12.
It is approximately equal to the value obtained by subtracting .

- The clock signal φ shown in FIG. After time t2, the signal φD (see FIG. 2 (C)) delayed by 0.00000000000000000000000000000, which is delayed by 0.0000000000000000000000000000000000000000000000000000000000000' is capacitively coupled to the gate (point d) of the transistor 2 through the MOS capacitor 11 after time t2, using the so-called bootstrap technique. As a result, the potential at point d increases after time t2. (See after time t! in FIG. 2(D)).

In this case, the value of the increased voltage is
1 and the ttid point (transistor 2 and inverter 3
It can reach up to about 2Vcc, depending on the ratio to nearby stray capacitance (including Then, this high voltage is applied to the core six points during the transmission period of the carry signal, and the transistor 2
Carry signal transmission through is sped up.

Note that when each of the source data a and b input to the cough exclusive logic circuit 1 is both "1" or both "0", the potential at the 0 point becomes a low level, and the d The potential at the point is also suppressed to a low level and does not rise.

Further, as described above, the transistor 12 inserted between the 0 point and the d point is connected to the d point during the carry signal transmission period.
This transistor 12 is provided to prevent the high potential charged at a point from flowing backward toward the 0 point and being discharged and lowering.
is required to prevent discharge through the logic gate, especially when a static logic gate is used as the logic gate.

〔Effect of the invention〕

According to the present invention, even when the number of bits to be operated on increases, it is possible to speed up the transmission of the carry signal without using a particularly large carry signal transmission transistor.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor integrated circuit according to the present invention, FIG. 2 is a timing diagram showing voltage changes at various parts to explain the operation of the circuit shown in FIG. 1, and FIG. 1 is a circuit diagram showing a conventional example of this type of semiconductor integrated circuit equipped with an arithmetic circuit. (Explanation of symbols) 1.5: exclusive logic circuit, 2: MOS transistor for transmitting carry signal, φ: clock signal, Carry In: carry signal from lower bit,
Carry Out: Carry signal to upper bit.

Claims (1)

[Claims] 1. A carry signal from the lower bit is transmitted to the upper bit via a carry signal transmission transistor, and a predetermined arithmetic circuit for the input source bit is provided, and a voltage is applied to the gate of the carry signal transmission transistor. is raised by a clock signal voltage that is at a high level during the transmission period of the carry signal.