JPH02177715A - Frequency doubling circuit - Google Patents

Abstract

PURPOSE:To obtain a frequency doubled clock signal whose duty factor is 50% with no adjustment with respect to an input clock signal of an optional frequency being a half the frequency of a reference clock signal or below by sampling the input clock signal with the reference clock signal. CONSTITUTION:A reference clock signal 101 outputted from an oscillator 1 is inputted to a counter circuit 2, which counts a pulse number of the reference clock signal 101 generated within a half period of the input clock signal. Then a counter output signal 103 is latched at the trailing of the input clock signal 102, the counter output signal 103 is held for one period of the input clock signal 102 and a latch circuit output signal 104 is obtained, The signal 104 is inputted to a subtracter 41 in a frequency divider circuit 4 and subtracted from a full count of a decayded counter 42. The decade counter 42 counts up number of the reference clock signal pulse while starting from the loaded initial value and sends an output signal 105 of the frequency divider circuit from a carry-out terminal when the counter 42 reaches its full count.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a doubler circuit, and particularly to a 2a doubler circuit used in a digital circuit requiring speed conversion.

[Conventional technology]

A conventional doubler circuit is shown in the circuit diagram of FIG. 8, and its timing diagram is shown in FIG. In FIGS. 8 and 9, this type of doubler circuit includes a resistor 81, a capacitor 82, a non-inverter with Schmitt circuit (NINV) 83, an EX-O
Consists of an R circuit 84, which integrates the input clock signal 102 with a resistor 81 and a capacitor 82, and generates the integrated waveform 80.
2 is shaped into a rectangular wave by a non-inverter with a Schmitt circuit 83 to generate a phase-delayed waveform 803. EX-OR the input clock signal 102 and the phase delay waveform 803 signal.
By using the circuit 840 as an input signal and using its output signal as the output clock signal 109, a double clock is generated.

[Problem a that the invention attempts to solve]

The conventional doubler circuit described above has a resistor 81 and a capacitor 8.
A phase delay is generated using a 2 and 1 integration circuit and a limit circuit. Secondly, the amount of phase delay is fixed, and depending on the frequency of the input clock signal 1020, there is a drawback that an output clock signal with a double duty factor of 50X cannot be obtained.

SUMMARY OF THE INVENTION An object of the present invention is to provide a 92 multiplier circuit which solves the above drawbacks and prevents the pulse deity from changing even if the frequency of the input clock signal changes.

[Means to solve the problem]

The configuration of the doubling circuit of the present invention includes an oscillator that outputs a reference clock signal with a frequency m times (a positive integer of m≧2) the frequency of an input clock signal, and a reference clock signal and an input clock signal. A counter circuit that inputs the counter output signal and the input clock signal, counts the number of reference clock pulses generated within 172 periods of the input clock signal, and outputs the count value as a counter output signal; A latch circuit that holds the value of the counter output signal during the period, a frequency divider circuit that outputs a pulse signal with twice the frequency of the input clock signal from the reference clock signal, and a pulse that delays and adds the frequency divider output signal. a shift register circuit which expands the width and further selectively outputs a signal with a desired pulse width using a latch circuit output signal as a control signal; an inverter circuit which inputs a reference clock signal and inverts the polarity of the input signal and outputs it; Either a flip-flop that shifts the input data by 172 pits using the output signal of the shift register circuit as the input data and the inverter circuit output signal as the clock, or a 7-lip 70-tub input/output signal using the LSB of the latch circuit output signal as the select control signal. A selector for selecting the signal is included.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a doubler circuit according to a first embodiment of the present invention. In FIG. 1, the frequency of the input clock signal 102 is multiplied by m (m
≧2 positive! ! Reference clock signal 101 with a frequency of
and an oscillator l that outputs "L" of the input clock signal 102.
” level to clear the internal state and input clock signal 10
A counter circuit 2 that counts the number of pulses of a reference clock signal 101 generated within 172 periods of 2 and outputs the count value as a counter output signal 103, this counter output signal 103, an input clock signal 102, and a reference clock signal 101. and the counter output signal 10
3 is held for one cycle of the input clock signal 102;
Latch circuit 3 outputting as latch circuit output signal 104
, a frequency dividing circuit 4 that generates a divided pulse of the reference clock signal every 172 cycles of the input clock signal 102, and a latch circuit output signal 110 excluding the LSB of the frequency dividing circuit output signal 105 and the latch circuit output signal 104. Input the frequency divider output signal 105 by n) (n is ("71 value -1)
(a positive integer, rounding down), and further expands the pulse width of the frequency divider output signal 105 to (n+1) pit width and outputs it. A shift register circuit 5 inputs the reference clock signal 101 and determines the polarity of the signal. The inverter circuit 6 that outputs the inverted signal 107, the output 71 of the shift register circuit 5, and the inverter signal 107 are inputted, and the output signal 106 is logically summed with the signal obtained by shifting the output signal 106 by 172 bits and the signal 106 before being shifted. The input signal 106 of the flip-flop 7 and the flip-flop output signal 108 are used as input data, and the LSB of the latch circuit output signal 104 is used as a select signal to output the input signal 106 of the flip-flop and the flip-flop. and a selector 8 that selects and outputs one of the output signals 108.

The third factor is a circuit diagram showing the configuration of the latch circuit 3 in FIG. 1. In FIG. 3, the latch circuit 3 includes an inverter circuit 31 that inputs a reference clock signal 101 and outputs a polarity inverted signal 301 of the signal, and an inverter circuit 31 that inputs the signal 301 and a counter output signal 103 and converts the counter output signal 103 to 1. /
A flip-flop 32 outputs a signal 302 shifted by 2 bits; an inverter circuit 33 inputs the λ cuff lock signal 102 and outputs a polarity inverted signal 303; 1 of the input clock signal 102 by latching the signal 302
The flip-flop 34 holds and outputs the latch circuit output signal 104 during the liii1 period.

FIG. 4 is a circuit diagram showing the configuration of the frequency divider circuit 4 of FIG. 1. In FIG. 4, this frequency divider circuit 4 inputs the latch circuit output signal 104, subtracts the value of the latch circuit output signal 104 from the full count value of the decade counter 42, and outputs the calculation result as a signal 401. a subtracter 41;
Reference clock signal 1 with signal 401 as initial value input data
A decade counter 42 counts up the number of pulses of 01 and outputs the pulse output from the carry-out terminal as a frequency divider output signal 105 when the count reaches full, and a decade counter 42 that inputs the frequency divider output signal 105 and calculates the polarity of its inversion. Inverter circuit 43 that uses the signal as load signal 402
It includes and consists of.

FIG. 5 is a circuit diagram showing the structure of the shift register circuit 5 of FIG. 1. In FIG. 5, the shift register circuit 5 includes an N-bit shift register 51 that uses the frequency divider output signal 105 as input data and uses the reference clock signal 101 as a clock signal to delay the frequency divider output signal 105 from 1 bit to N bits. , the frequency divider output signal 105 and Ql
to QN (QN is an N-bit delayed output signal), the delayed output signal 501 at t is converted to [signal 105+Ql], [(signal 10
5+Q1)+Qri, [(signal 105 +Qs0Ch)
+Qs ), . . . , an OR circuit 52 sequentially calculates the cumulative OR and outputs it as a signal 502, and a latch circuit output signal 104 which uses the frequency divider output signal 105 and the cumulative OR signal 502 up to QN as input signals. When the count value of the counter circuit 2 is [2] and [3], the latch circuit output signal 110 excluding the LSB is selected as a selector signal, and when the count value of the counter circuit 2 is [2] or [3], the frequency dividing circuit output signal 105 is selected and In this case, the value of N is [currant value x d-1] QN t
Select the cumulative OR signal 502 at
The selector 53 selects the cumulative OR signal 502 up to Qpi and outputs it as the signal 106.

Next, FIG. 2 is a timing diagram of FIG. @1, and the operations of FIGS. 1 to 5 will be explained using this diagram.

Next, FIG. 2 is a timing diagram of FIG. 1, and the operations of FIGS. 1 to 5 will be explained using this diagram.

The reference clock signal 101 output from the oscillator 1 is input to a counter circuit 21, which counts the number of pulses of the reference clock signal 101 generated within 172 cycles of the input clock signal. Next, by latching the counter output signal 103 at the falling edge of the input clock signal 102, the counter output signal 103 is held for one period of the input clock signal 102 and becomes the latch circuit output signal 104. signal 104
is input to the subtracter 41 in the frequency dividing circuit 4, and is subtracted from the full count value of the decade counter 42.

The calculation result becomes the initial value input data 401 of the decade counter 42. This manual data 401 is input to the decade counter 4 when the frequency dividing circuit output signal 105 is output from the carry-out terminal of the decade counter 42.
2 is loaded. The decade counter 42 counts up the number of pulses of the reference clock signal from the loaded initial value, and when the full count value 1 is reached, the frequency divider output signal 105 is sent out from the carry-out terminal.

In the examples shown in FIGS. 2 and 4, since the value of the counter output signal 103 is [6], the subtracter 41 in the frequency dividing circuit 4 outputs (9).
-6=3) and set the initial value input data 401 of the decade counter 42 to [3]. As a result of step 7, every 6 pulses of the reference clock signal 101, the carry-out terminal of the divided counter becomes @H", and the frequency divider output signal 105 becomes a clock signal with twice the frequency of the input clock signal 102. Next, the signal 105 is input to the shift register circuit 5, and the N-bit shift register 51 inputs the signal 105 to the shift register circuit 5.
bit to N bits. Further, the frequency dividing circuit output signal 105 and the delayed output signal 501 from Ql to QN are sequentially cumulatively ORed by N OR circuits 52. Therefore, this cumulative OR signal 502 becomes a signal obtained by extending the pulse width of the frequency dividing circuit output signal 105 by the 1-bit unit width of the reference clock signal 101 by CN+1E pits.

Next, the N+1 signals 502 are selected by the selector 53 using the latch circuit output signal 110 excluding the LSB among the latch circuit output signals 104 as a selector signal. At this time, the selection signal indicates that the count value of the counter circuit 2 is [2].
] and [3], the frequency divider circuit output signal 105 is selected, and in the case of an even number greater than or equal to [4], the value of N is the count value x L.
Select the cumulative OR signal 502 up to QN which is -1,
[5] In the case of an odd number greater than or equal to (count value - 1), the value of N is (count value - 1
) Select the cumulative OR signal 502 up to QN which becomes X-L-1. In the example shown in FIG. 2, since the count value is [6] (6X, -1=2), that is, the cumulative OR signal 5025- is selected up to Q2.

The fN number 106 becomes a double clock signal of duty 50X with @H'' level of 3 bits and @L'' level of 3 bits. In the case of an odd number of [5] or more, for example, the count value is [5] or more.
5], then ((5-1)X-1=1), that is, Qs
The cumulative OR signal 502 up to is selected. Output signal 10
6 has a "H" level of 2 bits and an L0 level of 3 bits.

Next, the signal 106 is input to the flip-flop 7 and is shifted by 1/2 bit by the polarity inversion signal 107 of the reference clock signal 101. Furthermore, the signal 106 is logically summed with the signal after the 172-bit shift and is output as a signal 108. As a result, the signal 10g output from the clip block 7 has a high level of 172 bits higher than the signal 106 output from the shift register circuit 5, and is “L”.
“It becomes a signal whose level has decreased by 172 bits. Therefore,
When the aforementioned count value is [5], the signal 108 is @H''
It becomes a 50% duty double clock signal with level 25 bits and ``LL-level 5 bits.Next lζ, the selector 8 detects that the LSB of the latch circuit output signal 104 is ``Ll''.
, that is, when the value of the counter output signal 103 is an even number, the signal 10 output from the shift register circuit 5
Select 6. Also, the LSB of the latch circuit output signal 104
1H", that is, when the value of the counter output signal 103 is an odd number, the signal 10g output from the flip-flop 7 is selected. Therefore, the output clock signal 109 output from the selector 8 is equal to the color/color output signal 103 The input clock signal is always 1, regardless of whether the value is odd or even.
This becomes the clock signal of the digital data 50X, which is obtained by multiplying 02 by 2.

Although this embodiment is constructed using one decade counter, it is clear that when the value of the output signal of the counter circuit 2 is [10] or more, similar results can be obtained by connecting decade counters in series. .

The doubling circuit of this embodiment counts the number of pulses of the reference clock generated within 172 periods of the input clock signal, and generates a pulse every 1/2 period of the input clock signal.

The generated pulse is expanded to the desired pulse width and output using the count value as a control signal, so no adjustment is required for input clock signals of any frequency as long as the frequency is 1/2 or less of the reference clock signal. Thus, a double clock signal with a data rate of 50% is obtained. By connecting the double multiplier circuits of this embodiment in a subordinate manner, a 2N multiplier circuit with a duty factor of 50X, such as 4 times, 8 times, etc., can be easily realized.

FIG. 6 is a circuit diagram showing a counter circuit of a doubler circuit according to a second embodiment of the present invention. The circuit blocks other than this counter circuit 2 have the circuit configuration of the first embodiment shown in FIG. In the doubler circuit of the second embodiment, the counter circuit 2
The counter 21 inputs the reference clock signal 101 and the load signal 202, and starts counting the reference clock signal 101 from 1 [1] every time the load signal 202 is input, and outputs the count value as the counter output signal 103.
and a comparator 22 which inputs an externally set set value 201 and a counter output signal 103 and outputs a load signal 202 only when the values of both signals match.

FIG. 7 is a timing diagram showing the operation of the second embodiment of the present invention. In FIG. 7, when obtaining a double clock signal using the double multiplier circuit of this embodiment, since the frequencies of the reference clock signal 101 and the input clock signal 1020 are known in advance, the comparator 22 in FIG. Setting value 2
01 is set to a value l obtained by dividing 172 cycles of the input clock signal 102 by 10101 cycles of the reference clock signal. ag
In FIG. 7, as an example, 1/2 of the input clock signal 102
A case where the period is five times the period of the reference clock signal 10101 is shown. As a result, when the value of the counter output signal 103 reaches [5]l, the load signal 20 is output from the comparator 22.
2 is output, and the counter output signal 103 of the counter 21
is initialized and the reference clock signal 101 is started again from [1].
Start counting.

Since the circuits after the latch circuit 3 are exactly the same as those in the first embodiment, the double clock signal 109 can be obtained by the same operation as in the first embodiment.

〔Effect of the invention〕

As explained above, the present invention enables the input clock signal of any frequency to be dedifferentiated without adjustment by sampling the input clock signal with the reference clock signal, as long as the frequency is 172 or less of the frequency of the reference clock signal. A 5ON double clock signal can be obtained, and a 2N multiplier circuit can be easily realized by cascading the clock signals.

However, when performing a dynamic burn-in test, high-speed pulses cannot be applied to integrated circuit (IC) devices due to the nature of the furnace. The present invention transmits pulses at a low frequency through this furnace, and in particular, by mounting the doubler circuit of the present invention connected in multiple stages inside an IC or on a BT board, it is possible to transmit pulses at a low frequency by 2n times the exact external frequency. CMO8 with accurate lock such as
@It has the effect of operating the inside of the IC and therefore consuming a certain amount of power more than in the normal case.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the double frequency circuit of the first embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of the first embodiment of FIG. 1, and FIG. 3 is the latch shown in FIG. 1. A circuit diagram showing the configuration of the circuit, FIG. 4 is a circuit diagram showing the configuration of the frequency dividing circuit in FIG. 1,
FIG. 5 is a circuit diagram showing the configuration of the shift register circuit in FIG. 1, FIG. FIG. 8 is a timing diagram showing the operation of the second embodiment of the figure, FIG. 8 is a circuit diagram of a conventional double multiplier circuit, and FIG. 9 is a timing diagram showing the operation of the double multiplier circuit shown in FIG. 1... Oscillator, 2... Counter circuit,
3... Latch circuit, 4... Frequency divider circuit,
5...Shift register circuit, 6...Inverter circuit, 7...Flip-flop, 8...
...Selector, 21 ...Counter, 22
... Comparator, 31.33 ... Inverter, 32.34 ... Aritube flop, 41.
...Subtractor, 42 ... Decade counter, 43 ... Inverter circuit, 51 ...
・N-bit shift register, 52...OR circuit, 53...Selector, 81...Resistor, 82...Capacitor, 83...・Non-inverter with Shemit circuit, 84...EX-
OR circuit, 101...Reference clock signal, 10
2... Input clock signal, 103...
Counter output signal, 104... Latch circuit output signal, 105... Frequency divider circuit output signal, 106,
107.108...Signal, 109...
Output clock signal, 110...Latch circuit output signal excluding LSB, 201...Setting value, 202
...Load signal, 301, 302.303...
...Signal, 401...Initial value input data,
402...Load signal, 501...Delayed output signal, 502...Cumulative OR signal, 80
2.803...Signal. Agent Patent Attorney Shinpaku Uchihara δ

Claims (1)

[Claims] an oscillator that outputs a reference clock signal with a frequency m times the frequency of the input clock signal (a positive integer of m≧2); a counter circuit that counts the number of reference clock pulses generated within /2 cycles and outputs the count value as a counter output signal; and a counter circuit that inputs the counter output signal and the input clock signal, and receives the counter output signal and the input clock signal for one cycle of the input clock signal. A latch circuit that holds the value of the counter output signal, a frequency divider circuit that outputs a pulse signal with twice the frequency of the input clock signal from the reference clock signal, and a delay and addition of the output signals of the frequency divider circuit. A shift register circuit that expands the pulse width and selectively outputs a signal with a desired pulse width using the latch circuit output signal as a control signal, and an inverter circuit that inputs the reference clock signal, inverts the polarity of the input signal, and outputs it. and,
Using the output signal of the shift register circuit as input data and the inverter circuit output signal as a clock, the input data is
1. A doubling circuit comprising: a flip-flop that shifts /2 bits; and a select that selects one of the input and output signals of the flip-flop using the LSB of the latch circuit output signal as a select control signal.