JPH06120815A - Pulse swallow system variable frequency divider - Google Patents

Abstract

PURPOSE:To provide a pulse swallow system variable frequency divider which can construct a PLL system that can work at a high speed and with high stability without falling into abnormal state at the time of application of a power supply. CONSTITUTION:A pulse input inhibiting circuit 701 is provided to inhibit the transmission of the carry output of a programmable or a pulse 710 obtained by expanding the carry output together with a pulse width expanding circuit 702 which generates a 1st pulse 707 by expanding the output pulse of the circuit 701 and a 2nd pulse 703 having the width larger than the pulse 707, an inhibition signal generating circuit 740a which produces an inhibition signal by inverting the output of a storage circuit 706 at the fall edge of the pulse 710, inverts a synchronously the output of the circuit 706 by means of the pulse 703 of the circuit 702 to cancel the inhibition signal, and therefore produces the signal that is applied to an inhibition signal input terminal of the circuit 701, and a logic circuit which uses the pulse 707 of the circuit 702 as an operating clock to produce the signal to be applied to the programmable counter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse swallow type variable frequency divider for dividing an input signal.

[0002]

2. Description of the Related Art FIG. 6 shows a block diagram of a typical PLL circuit including a conventional pulse swallow-type variable frequency divider. The prescaler 1 divides the signal input from the signal input terminal 11 according to the output of the mode control circuit 5. The division ratio is 1/6 when the control signal input terminal 13 is Low,
When the input terminal 13 is High, the frequency is divided into ⅕. The output of the prescaler 1 is given to the 6-bit counter 2 and the 3-bit counter 4. 6-bit counter and 3
The carry outputs 21 and 41 of the bit counter are given to the mode control circuit 5.

The pulse swallow type variable frequency divider 100 having such a structure operates as follows. First, in the initial state, the 6-bit counter 2 and the 3-bit counter 4 are loaded with the initial values from the logic circuit 6 via the terminals 20 and 40, and both carry outputs are Low.
At this time, the output of the mode control circuit 5 is Low, and the signal applied to the input terminal 12 of the prescaler 1 is divided into 1/6. Each of the counters 2 and 4 performs a counting operation by a signal given from the output terminal 14 of the prescaler 1. Then, as the counting operation proceeds, the carry output 41 of the 3-bit counter 4 is first generated, and the output of the mode control circuit 5 changes to High. After that, the prescaler 1 divides the frequency by a factor of 5, and the carry of the 6-bit counter 2 is eventually generated. This carry is used as the initial value load control signals 22 and 42 for the 6-bit counter 2 and the 3-bit counter 4, and is also given to the mode control circuit 5 to reduce the frequency division ratio of the prescaler 1 to 1/6.
It is used for returning to the frequency division and for generating the operation clock of the logic circuit 6.

[0004]

However, in such a variable frequency divider, the system may not operate normally depending on the initial value of the data given to the variable frequency divider when the power is turned on. Now, in order to simplify the operation of the counters, it is assumed that the output of the logic circuit 6 is loaded into each counter with the polarity inverted from all the bits. At this time, for example, if the output value of the logic circuit when the power is turned on is 000100 ₍₂₎ = 4 for the 6-bit counter and 011 ₍₂₎ = 3 for the 3-bit counter, the initial value of the 6-bit counter is the 000100 ₍₂₎ = the value obtained by reversing the 1,0 of all bits of 4 111011 ₍₂₎ = 59,3 initial value of the bit counter 011 ₍₂₎ = inversion 1,0 of all bits of the 3 The resulting value is 100 ₍₂₎ = 4. Since the frequency division number of the 2-modulus prescaler is switched between 6 and 5, the variable frequency divider performs 23 frequency division (3 + 5 × 4 = 23). The initial oscillation frequency of the voltage controlled oscillator (VCO) 8 is approximately 1 GHz.
A pulse for completion of frequency division is generated for every 23 ns. The width of the pulse generated by the variable frequency divider is now set to 10ns
And When this pulse is given to the pulse width expansion circuit 7 which expands the pulse width by 20 ns by taking the logical sum of the input pulses which are sequentially delayed, the pulse disappears. This state is shown in FIG. Therefore, no pulse is given to the logic circuit 6, the output of the logic circuit remains at the value at power-on, the variable frequency divider continues to divide by 23, and the logic circuit does not perform the desired operation.

Therefore, conventionally, immediately after the power is turned on, the control voltage of the voltage controlled oscillator 8 is controlled to sufficiently delay the clock supplied from the outside, and the pulse width is set to whatever the output of the logic circuit 6 is when the power is turned on. After allowing the expansion circuit 7 to generate a normal pulse and generating an appropriate frequency division ratio at the output of the logic circuit 6, the control voltage of the voltage controlled oscillator 8 is applied from the loop filter 92 to normally operate the PLL. I was dealing with it by moving to a state. However, a switch or the like must be provided at the input part of the voltage controlled oscillator 8 to perform control by a microcomputer or the like, which complicates the system and causes the impedance of the switch to make the operation of the PLL unstable. It was

The present invention has been made in view of the above problems, and an object of the present invention is to provide a frequency divider capable of forming a PLL system that operates at high speed and stably without causing an abnormal state when the power is turned on. To do.

[0007]

A pulse swallow-type variable frequency divider according to claim 1, wherein an input signal is input to a first input end, a control signal is input to a second input end, and the second
A prescaler for dividing the input signal by any one of the two division ratios according to the signal applied to the input terminal of the prescaler is provided, and the first and second prescalers that operate in synchronization with the output of the prescaler are provided. A programmable counter, a control circuit that receives the output of the prescaler and the carry of the first and second programmable counters as inputs, and gives a control signal to the prescaler, and a carry output of the first programmable counter or a pulse obtained by expanding the carry output. A pulse input prohibition circuit that prohibits input transmission based on the signal at the prohibition signal input end, a first pulse obtained by extending the output pulse of the pulse input prohibition circuit, and a second pulse longer than the first pulse. Pulse width expansion circuit for generating the pulse of the first programmable counter and the carry output of the first programmable counter or the carry output thereof. At the falling edge of the stretched pulse, the output of the storage circuit is inverted to generate an inhibit signal, and the output of the storage circuit is asynchronously inverted using the second pulse of the pulse width extension circuit to output the inhibit signal. A prohibition signal generation circuit that generates a signal to be applied to a prohibition signal input terminal of the pulse input prohibition circuit by canceling it, and a first output pulse of the pulse width expansion circuit as an operation clock, and the first and second counters A logic circuit that generates a signal to be supplied to

According to another aspect of the pulse swallow-type variable frequency divider, an input signal is input to the first input terminal, a control signal is input to the second input terminal, and the second input terminal is input. A prescaler for dividing an input signal by any one of two division ratios according to a given signal, and first and second programmable counters operating in synchronization with the output of the prescaler; The output of the prescaler and the carry of the first and second programmable counters are input, and a control circuit that gives a control signal to the prescaler, and a carry output of the first programmable counter or a pulse obtained by expanding the carry output are input. Inhibit signal The pulse input inhibit circuit that inhibits input transmission based on the signal at the input terminal, and the pulse output of the pulse input inhibit circuit is expanded. A pulse width expanding circuit for generating a first pulse, and long the second pulse from the first pulse, first at the first falling edge of the pulses carry output or stretching this programmable counter 1
The output of the first storage circuit is inverted by inverting the output of the second storage circuit to generate an inhibition signal, and inverting the output of the second storage circuit at the falling edge of the second pulse of the pulse width expansion circuit. A prohibition signal generation circuit that generates a signal to be applied to a prohibition signal input terminal of the pulse input prohibition circuit by asynchronously inverting and canceling the prohibition signal, and a first output pulse of the pulse width expansion circuit as an operation clock, The first
And a logic circuit for generating a signal to be supplied to the second counter.

[0009]

In the variable frequency dividers of claims 1 and 2, by devising the circuit configuration, it is not necessary to perform special switch control by a microcomputer as in the conventional case, so that the system can be simplified. It is possible to construct a more stable system than a complicated system using switches as in the past.

[0010]

(Embodiment 1) A first embodiment corresponding to the invention described in claim 1 will be described with reference to the drawings. FIG. 1 shows a block diagram of a PLL using the pulse swallow-type variable frequency divider of the first embodiment. In this example,
A difference from the conventional example shown in FIG. 6 is that a pulse shaping circuit 70 generates a signal to be supplied to the logic circuit 6 which was conventionally generated by the pulse width expansion circuit 7. FIG. 2 shows the details of the pulse shaping circuit 70, and FIG. 3 shows a waveform diagram for explaining the shaping process.

The pulse shaping circuit 70 includes a pulse input terminal 71.
The pulse output of the pulse swallow type variable frequency divider is input from 0. In the conventional example of FIG. 6, when a pulse having a width of 10 ns is input to the pulse width expansion circuit 7 at a cycle of 23 ns, the output of the pulse width expansion circuit 7 is always High.
The operation clock is not given to the logic circuit 6. On the other hand, if the pulse is shaped by the pulse shaping circuit 70 of FIG. 1 showing the first embodiment of the present invention, an appropriate pulse can be output by the function of widening the input pulse interval. The function is to prohibit the pulse input at the falling edge of the input pulse and release the prohibition at the Low level of the pulse width expansion circuit.

The pulse shaping circuit 70 will be described in detail below. In the pulse shaping circuit shown in FIG. 2, the initial states of the flip-flops 704 and 706 are both reset. Here, the pulse width expansion circuit 702
Is a pulse output from the input terminal 705 by extending the pulse width to the first output terminal 707 and the second output terminal 703, and the pulse width is the pulse output from the terminal 707 (for example, 30 ns). The pulse (for example, 40 ns) output from the terminal 703 is longer than the width by t ₀ . This state is shown by the symbol t ₀ in FIGS. 3 (A) and 3 (B). In this state, first the pulse input terminal 7
It is assumed that a pulse having a width of 10 to 10 ns is given with a period of 23 ns. The input signal is the pulse input inhibition circuit 70.
It is given to the pulse width expansion circuit 702 via 1, the second output terminal 703 of the pulse width expansion circuit becomes High, and the reset of the memory circuit 706 is released. Here, the output 70 is output by the time when the signal at the pulse input terminal 710 falls.
It makes the assumption that 3 will fall. Next, at the falling edge of the input pulse given from the pulse input terminal 710,
The output of the flip-flop 706, which is a memory circuit, is High.
Therefore, the pulse input prohibition circuit 701 has a pulse input terminal 710.
The input signal from will be prohibited. At this stage, the pulse width expansion circuit 702 has been given a pulse having a width of 10 ns, and this pulse has a width of 30 ns and 40 ns.
Performs an operation to extend to the width. At this point, the second output terminal 703 of the pulse width expansion circuit 702 is High, so the reset of the flip-flop 704 is released. Eventually, when the signal at the second output terminal 703 of the pulse width expansion circuit 702 falls, the flip-flop 704 captures the value at the pulse input terminal 710 at this falling edge. The role of the flip-flop 704 is that the value of the pulse input terminal 710 is High when the signal at the output terminal 703 of the pulse width expansion circuit 702 falls.
If so, the signal to the reset input terminal of the memory circuit 706 is kept until the signal of the pulse input terminal 710 becomes Low.
The reset signal to 06 is not generated. This state is shown in FIG. Further, FIG. 3A shows an operation waveform of the pulse shaping circuit when the value of the pulse input terminal 710 is Low at the time when the signal of the second output terminal 703 of the pulse width expansion circuit 702 falls. The signal at the second output terminal 703 of the pulse width expansion circuit 702 is Low.
Then, the flip-flop 704 is reset and the memory circuit 706 is reset.

In such a configuration, the pulses output from the two output terminals 707 and 703 of the pulse width expansion circuit 702 are used for different purposes. That is, the signal output from the second output terminal 703 is the input signal to the prohibition signal generation circuit 740a, and the signal output from the first output terminal 707 is the operation clock of the logic circuit 6 in FIG. Are used respectively. By doing so, it is guaranteed that the clock output to the output terminal 711 has a Low period of t _{0 at the} shortest.

It should be noted that the initial state of the pulse shaping circuit shown in FIG. 2 clearly has no problem from the following consideration. That is, in the initial state, the memory circuit 70
When the output of 6 is High, the output of the pulse width expansion circuit 702 becomes Low, the memory circuit 706 is automatically reset, and the prohibition of pulse input is released. In addition, in the initial state of the flip-flop 704, the output is High.
If it is h, reset is applied when the pulse input becomes Low, or if it is Low, the signal of the output terminal 703 of the pulse width expansion circuit 702 can be directly given to the reset input of the memory circuit 706, so there is no problem. .

(Embodiment 2) A second embodiment corresponding to the invention described in claim 2 will be described with reference to the drawings.
The block diagram of the PLL using the pulse swallow type variable frequency divider of the second embodiment is the same as that of the first embodiment. The difference is the internal configuration of the inhibit signal generation circuit of the pulse shaping circuit 70. FIG. 4 shows the details of the pulse shaping circuit 70, and FIG. 5 shows a waveform diagram for explaining the shaping process. The operation will be described below.

The pulse shaping circuit 70 receives the pulse output of the pulse swallow type variable frequency divider from the input terminal 710. In the conventional example, the pulse width expansion circuit has 10
When a pulse having a width of ns is input, the output of the pulse width expansion circuit is always High, and the operation clock is not given to the logic circuit 6. On the other hand, if the pulse shaping circuit 70 shapes the pulse, an appropriate pulse can be output by the function of widening the input pulse interval. As a function,
The pulse input is prohibited at the falling edge of the input pulse, and the prohibition is released at the falling edge of the output pulse of the pulse expansion circuit. The pulse shaping circuit 70 will be described in detail below.

In the pulse shaping circuit shown in FIG. 4, it is assumed that the initial state is that the reset of the flip-flop 706, which is the first storage circuit, is released and the output is Low. In this state, first 10 ns from the pulse input terminal 710.
Suppose a pulse of width is given with a period of 23 ns. The input signal is supplied to the pulse width expansion circuit 702 via the pulse input inhibition circuit 701, and the second output terminal 703 of the pulse width expansion circuit 702 becomes High. When the output falls, the flip-flop 704 captures the value at the pulse input terminal 710 at the falling edge. The role of this flip-flop 704 is that the pulse width expansion circuit 7
At the time of the falling edge of the output of 02, if the pulse input terminal 7
If the value of 10 is High, the clock signal to the second memory circuit 718 does not fall until the signal of the pulse input terminal 710 becomes Low. In this manner, when a clock is input to the flip-flop 718 which is the second memory circuit, its output becomes Low, and at that moment, the flip-flop 706 which is the first memory circuit is reset, and its output becomes Low, The pulse input inhibition circuit 701 releases the inhibition of the input from the pulse input terminal 710. After a little delay from this operation, the second memory circuit 718
To the first storage circuit 706, the output of the set signal becomes High, and the reset to the first memory circuit 706 is released. In this way, the initial state is restored.

In consideration of the operation of the flip-flop 704, the operation waveform of the pulse shaping circuit when the value of the input terminal 710 is Low at the falling time of the output of the pulse width expansion circuit 702 is shown in FIG. FIG. 5B shows an operation waveform of the pulse shaping circuit in the case of High.

Here, the minor loop detection circuit 717 in FIG. 4 will be supplementarily described. The purpose of this circuit is to fix the output of the first memory circuit 706 to High at all times and to prevent the pulse input inhibition state from continuing. Specifically, the flip-flop 706
Output from the input terminal 713 is continuously input a plurality of times by the clock supplied from the pulse input terminal 710, and if all of them are high, a high signal is generated from the output terminal 714 and the output of the logic gate 715 is forced. Then, the flip-flop 706 is reset to Low to release the inhibition of pulse input. The fact that High is continuously input by the above-described multiple captures means that the pulse input is prohibited for that number of times during operation. Therefore, the number of times of fetching should be able to determine the minor loop state and the state in which the pulse input is continuously prohibited in the normal state. That is, the data may be fetched from the input terminal 713 at least once more than the maximum number of times the input is continuously prohibited in the normal operation state.

[0020]

According to the pulse swallow type variable frequency divider of the present invention, P does not cause an abnormal operation when the power is turned on.
The LL system can be realized more stably with a simpler structure than the conventional one.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a PLL circuit using a pass-swallow-type variable frequency divider according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration of a pulse shaping circuit in the embodiment.

FIG. 3 is a waveform diagram showing the operation of the pulse shaping circuit in the embodiment.

FIG. 4 is a circuit diagram showing a detailed configuration of a pulse shaping circuit according to a second embodiment of the present invention.

FIG. 5 is a waveform diagram showing the operation of the pulse shaping circuit in the embodiment.

FIG. 6 is a block diagram showing a configuration of a PLL circuit using a conventional pass-swallow-type variable frequency divider.

FIG. 7 is a waveform diagram showing the operation of the pulse width expansion circuit in the conventional Pass-Swallow-system variable frequency divider.

[Explanation of symbols]

 1 Pre-scaler 2 6-bit counter-4 3 3-bit counter-5 Mode control circuit 6 Logic circuit 7 Conventional pulse width expansion circuit 8 Voltage controlled oscillator 70 Pulse shaping circuit 100 Variable frequency divider 701 Pulse input prohibition circuit 702 Pulse width expansion Circuit 704 Flip-flop 706 Storage circuit 717 Minor loop detection circuit 718 Second storage circuit

Claims (2)

[Claims] 1. An input signal is input to a first input end, and a second input signal is input.
A control signal is input to an input terminal of the prescaler for dividing the input signal by any one of two division ratios by the signal applied to the second input terminal, and an output of the prescaler First and second programmable counters that operate in synchronization; a control circuit that receives the outputs of the prescaler and the carry of the first and second programmable counters as inputs, and that provides a control signal to the prescaler; A carry input of a programmable counter or a pulse obtained by extending the carry input is used as an input, and a pulse input inhibition circuit that inhibits input transmission based on a signal at an inhibition signal input end; and a first pulse obtained by extending the output pulse of the pulse input inhibition circuit A pulse width expansion circuit for generating a pulse and a second pulse longer than the first pulse; and the first programmer Output of the memory circuit is inverted at the carry output of the pulse counter or the falling edge of the expanded pulse to generate an inhibit signal, and the output of the memory circuit is asynchronously generated by using the second pulse of the pulse width expansion circuit. An inversion signal generation circuit that inverts and releases the inhibition signal to generate a signal to be applied to the inhibition signal input terminal of the pulse input inhibition circuit, and a first output pulse of the pulse width expansion circuit as an operation clock, A pulse swallow-type variable frequency divider having a logic circuit for generating a signal to be supplied to the first and second counters. 2. An input signal is input to the first input terminal, and the input signal is input to the second input terminal.
A control signal is input to an input terminal of the prescaler for dividing the input signal by any one of two division ratios by the signal applied to the second input terminal, and an output of the prescaler First and second programmable counters that operate in synchronization; a control circuit that receives the outputs of the prescaler and the carry of the first and second programmable counters as inputs, and that provides a control signal to the prescaler; A carry input of a programmable counter or a pulse obtained by extending the carry input is used as an input, and a pulse input inhibition circuit that inhibits input transmission based on a signal at an inhibition signal input end; and a first pulse obtained by extending the output pulse of the pulse input inhibition circuit A pulse width expansion circuit for generating a pulse and a second pulse longer than the first pulse; and the first programmer The falling edge of the pulses carry output or stretching it in Rukaunta inverts the output of the first memory circuit to generate a prohibiting signal, the pulse width in the second falling edge of the pulse stretching circuit second
Inverting the output of the memory circuit and asynchronously inverting the output of the first memory circuit to release the inhibit signal, thereby generating a signal to be applied to the inhibit signal input terminal of the pulse input inhibit circuit. A pulse swallow-type variable frequency divider comprising: a circuit; and a logic circuit that generates a signal to be given to the first and second counters by using a first output pulse of the pulse width expansion circuit as an operation clock.