JPH0217721A - Logic circuit - Google Patents

Abstract

PURPOSE:To increase load driving capacity by attaching a source-follower field effect transistor not being provided in a Schottky diode FET logic(SDFL) on an output part. CONSTITUTION:When a signal of H level is inputted to either the input terminals 9a, 9b and 9c of the SDFL, a switching FET13 is turned on, and a drain voltage drops. And the source-follower FET15 is turned off, and an L level is outputted from an output terminal 14. In a diode logic generally, another switching diodes 8b and 8c function as load capacitance by remarking a switching diode 8a in a multiple input OR logic. In the title circuit, since a circuit equivalent to a buffer FET logic is constituted of the output driving parts of logic circuits A2, A3 and A4 at a preceding stage, and the input part of a logic circuit A1 at a succeeding stage, it is possible to prevent response speed from being lowered due to the load capacitance.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a logic circuit including a diode as a logic element.

Conventional technology A field effect transistor of a chemical α conductor represented by GεtAs (hereinafter referred to as r FET (Field Eff
Focusing on the superiority of yield in manufacturing as a logic circuit using ECT Transistor),
Various logic circuits using debuttion mode FETs have been proposed so far.

No. 4121 is a circuit diagram showing an example of such a conventional logic circuit. This circuit consists of a Schottky diode la,
A three-way NOR circuit is constructed using lb and lc as logic elements, and uses Schottky diode FET logic (S
el+otLky Diode FET Logic;
(hereinafter referred to as rSDFL).

In the figure, three Schottky diodes 1rt, l
The anodes of b and lc are respectively connected to three input terminals 2a, 2b and 2C corresponding to these, and a three-man OR logic is configured by these Schottky diodes 1a, 1b and lc.

The level shift diode 3 is a diode for lowering the logic level of the input signal, and its anode is connected to the above-mentioned three Schottky diodes la, lb, l.
It is commonly connected to each cathode of c.

Pulldown FE7.4 is level shift diode 3
This is a FET for biasing the voltage to a low potential, and an N-channel depression type FET is used. The drain of this pull-down FET is connected to the cathode of the level shift diode 3, and the gate and source are connected to the low potential power supply 1,. It is connected to the.

The load FET 5 is a FET constituting the load of the inverter section, and similarly an N-channel depression type FET is used. The drain of this load FET5 is a high potential power supply■. . , and the gate l- and source are connected to the output terminal 6.

The switching FET 7 is a FET that constitutes the switching element of the inverter section described above, and similarly an N-channel depression type FET is used. The drain of this switching FE77 is connected to the load FET5 mentioned above.
The gate is connected to the drain of the above-mentioned pull-down FET 4, and the source is connected to the second low potential power supply 2, .

In the circuit with the above configuration, when an H level signal is input to either of the input terminals 2a, 2b2c, the drain potential of the pull-down FE74 rises, this potential is given to the switching FET7 as a gate input signal, and the switching FET7 It is turned on and an L level signal is taken out from the output terminal 6. In addition, input terminals 2a, 2b, 2
When no H level signal is input to any of the FETs c, the drain potential of the pull-down FET 4 decreases, the switching FET 7 is turned off, and a signal of 1 level is taken out from the output terminal 6. That is, the inverter section composed of the load FET 5 and the switching FET 7 inverts the gate input signal of the switching FET 7 and drives the next stage circuit.

The above-mentioned 5DFL has a structure that allows the use of FE'r with a shallow threshold voltage, and is therefore characterized in that power consumption can be kept low. In addition, since a very small Schottky diode (for example, the size of the active region is about 1 μm x 2 μm) is used as a logic element, the required area can be kept small even when configuring a multi-input logic circuit. It has the characteristic of being able to

Because 5DPL has such characteristics, it is possible to increase the degree of integration by applying it to LSI, and 5DPL has already been developed.
LSIs such as single-gate scale multipliers and gate arrays have also been prototyped using FL.

Problems to be Solved by the Invention However, since the above-mentioned 5DFL is a logic circuit that uses a switching diode such as a Schottky diode as a logic element, in order to drive a logic circuit with the same configuration connected to the next stage, It is necessary to supply current from the load FET 5 to the switching diode of the next stage logic circuit.

However, the required current for this supply increases in proportion to the number of fan-outs, so when the number of fan-outs exceeds 4, as shown in Figure 5 (in Figure 5, FO increases the number of fan-outs). ) The logic level fluctuates, and if it is directly connected to the next stage logic circuit, the logic will not be transmitted correctly. That is, such a problem occurs because the driving ability of the 5DFL load is low.

Therefore, an object of the present invention is to provide a logic circuit that has advantages equivalent to 5DFL in terms of power consumption, required area, etc., and has sufficient load driving ability.

SUMMARY OF THE INVENTION The present invention provides an N-channel pull-down field effect I which has a plurality of diodes each having its anode connected to a plurality of corresponding input terminals, and a gate and a source connected to a first low potential power supply. - a level shifting diode inserted between the cathode of the diode and the pull-down field effect transistor; and a pull-down field effect I transistor whose source is connected to a second low potential power supply and whose gate is connected to the pull-down field effect transistor. an N-channel switching field-effect transistor whose drain is connected to the high-potential supply and whose source is connected to the drain of the switching field-effect transistor. effect transistor; and an N-channel source follower field effect transistor having a drain connected to the high potential power supply, a gate connected to the drain of the switching field effect transistor, and a source connected to the output terminal. This is a characteristic logic circuit.

According to the present invention for fY, it is better than 5D in terms of power consumption and required area.
While it exhibits the same capability as the FL, it has 11 source follower field effect transistors added to the output section, which the 5DFL does not have, so the presence of these source follower field effect I transistors increases the load driving capability.

Embodiment FIG. 1 is a circuit diagram showing an embodiment of the logic circuit of the present invention. This logic circuit is a logic circuit using monster conductor field effect transistors (hereinafter referred to as rFETs), and includes Schottky diodes 8a, 8L+, ! A three-way NOR circuit is constructed using 3c as a logic element.

In the figure, three diodes 1 to 8a, 8
The anodes of b and 8c are respectively connected to the three corresponding input terminals 9εL, 9b and 9c, and a three-man OR logic is constructed by these Schottky diodes 13a and 8b8C. Level shift diode 1
0 is a diode for lowering the logic level of the input signal inputted through the diodes 8a, 8b, and 8c, and its anode is connected to the three diodes mentioned above.
It is connected to the cathodes of Sotoki diodes 8a, 8b, 8C'.

Pull-down FET 11 is level shift diode 1
This is a FET for biasing 0 to a low potential, and an N-channel depression type PET is used. The drain of this pull-down FET 11 is connected to the cathode of the level shift diode 10, and the gate and source are connected to the low potential power supply V pn.

Load FET12 is a FET that constitutes the load of the inverter section.
, and the same N-channel depression type FE
T is used. The drain of this load FET 12 is connected to a high potential power supply V1)p.

The switching FE 13 is an FET constituting the switching element of the above-mentioned input unit, and also uses an N-type FET and a depression type FET.

The drain of this switching FET 13 is connected to the gate and source of the load FET 12 described above, the gate is connected to the drain of the pull-down FET II described above, and the source is connected to the second low potential power supply ■. ing.

That is, the configuration up to now is completely the same as the conventional 5DFL described above. This circuit further includes an N-channel depression type source follower FE715 whose drain is connected to the above-mentioned high potential power supply ■1llo, whose gate is connected to the drain of the switching FET13, and whose source is connected to the output terminal 14. Newly added.

In this logic circuit, when an H level signal is input to any of the input terminals 9a, 9b, and 9c, the pull-down FET
The drain potential of II increases, this potential is given to the switching FE 713 as a gate input signal, the switching FET 13 is turned on, and its drain potential drops. This potential is applied to the source follower FET 15 as a gate input signal, the source follower FET 15 is turned off, and an L level signal is taken out from the output terminal 14.

Furthermore, when no H level signal is input to any of the input terminals 9a, 9b, and 9c, the pull-down FET 11
The drain potential of FET 13 decreases, the switching FET 13 is turned off, and its drain potential increases. Since this potential is applied to the source follower FET 15 as a gate input signal, the source follower FET 15 is turned on and a signal of 1 level is taken out from the output terminal 14.

In other words, the inverter section composed of the load FET 12 and the switching FET 13 includes the switching FET 13
The source follower FE 715 amplifies the inverted signal to drive the next stage circuit.

As described above, the logic transmission in this logic circuit is the same as in the conventional 5DFL, but the load driving ability is significantly improved compared to the conventional 5DFL. Figure 2 shows how the logic level changes as the number of fan-outs (indicated by FO in 2I) increases in this logic circuit. It can be seen that the logic level does not change much, and the logic threshold also hardly changes. In other words, even if the number of fan-outs increases to 9, the variation in the logic level will be suppressed within the operating margin, and by using this logic port n in place of the conventional 5DFL, the 5DFL
This can fully compensate for the lack of driving capacity.

Furthermore, if the number of inputs is four or more, it is sufficient to connect the input terminals and the corresponding Schottky diodes in parallel with the above-mentioned Schottky diodes 8a, 8b, 8C, and add a plurality of logic circuits. As in the case of 5DFL, by combining them, it is possible to easily configure logic circuits such as OR and NAND in addition to NOR circuits.

FIG. 3 shows three logic circuits A2, A3, . A configuration example in which A4 output terminals are connected to each other is shown. In this connection configuration, the preceding stage logic circuit A2. A3. A4's respective source followers FE715, Schottky diodes 8a, 8b, 8c, level shift diode 10 and pull-down FET1 of the next stage logic circuit A1.
1 is the wired O of the well-known buffer art FET logic.
It can be seen that the same circuit as R is configured.

In the case of diode logic, it is possible to easily configure a multi-input OR3&M by simply increasing the number of switching diodes, such as the Schottky diodes 8a, 8b, and 8c described above. Now, when we focus on the signal input to a certain switching diode, the load capacity of other switching diodes is
However, in the logic circuit of this embodiment, as shown in FIG. 2, the response speed tends to decrease as the number of fan-ins increases. A3. Since the output drive section of A4 and the input section of the next stage logic circuit A1 constitute a circuit equivalent to a buffer art FET logic, it is possible to reduce the decrease in response speed due to load capacitance.

Further, since the logic circuit of this embodiment can be treated in the same way as a 5DFL in terms of logic configuration and connection between circuits, a circuit can be assembled in a mixed manner with a 5DFL. Therefore, by applying the logic circuit of this embodiment to a circuit part with a large fan-out number or a circuit part with a large fan-in number in the next stage, it is possible to take advantage of the excellent characteristics of 5DFL, such as low power consumption, and to It can also compensate for the lack of driving capacity.

Effects of the Invention As described above, the logic circuit of the present invention exhibits the same performance as the 5DFL in terms of power consumption and required circuit area, but it also has a source follower FET in the output section, which the 5DFL does not have. Since it is added, the load driving capacity is large, and when used in combination with the 5DFL, it can sufficiently compensate for the lack of the load driving capacity of the 5DFL.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a logic circuit that is an embodiment of the present invention, Fig. 2 is an input/output characteristic diagram of the logic circuit, and Fig. 3 is a circuit showing a connection configuration in which a plurality of such logic circuits are combined. 4 is a circuit diagram showing a conventional logic circuit, and 5I21 is an input/output characteristic diagram of the logic circuit. 8a, 8b, 8C... Schottky diode, 9a
, 9b, 9c...input terminal, 10...level shift diode, 11...pull-down FET, 12...
...Load FET, 13...Switching FET, 14
...Output terminal, 15...Source follower FET, V,
. ...First low potential Tkii, V ss... Second low potential power supply, V DD... High potential power supply agent, patent attorney, number of strokes, Kei Partial input! Pressure.

Claims (1)

[Scope of Claims] A plurality of diodes each having an anode connected to a plurality of corresponding input terminals, an N-channel pull-down field effect transistor having a gate and a source connected to a first low potential power supply; a level shifting diode interposed between a cathode and the pull-down field effect transistor; and an N-channel switching whose source is connected to a second low potential power supply and whose gate is connected to the drain of the pull-down field effect transistor. a field effect transistor; an N-channel load field effect transistor having a drain connected to a high potential power supply, a gate and a source connected to the drain of the switching field effect transistor; and a drain connected to the high potential power supply; and an N-channel source follower field effect transistor whose gate is connected to the drain of the switching field effect transistor and whose source is connected to the output terminal.