JPH02176473A - Voltage determination circuit - Google Patents

Abstract

PURPOSE:To determine successively a peak value of a periodic waveform and a voltage such as a DC voltage and to facilitate the determination of appropriateness by latching outputs of first and second comparators. CONSTITUTION:An input signal from a signal input terminal 1 being taken as a positive-side input, it is compared with a reference voltage as a negative- side input from a reference voltage input terminal 2 by a first comparator 4 of a voltage determination circuit, and the input signal form the terminal 1 taken as the negative-side input and a reference voltage as the positive-side input from a reference voltage input terminal 3 are compared with each other by a second comparator 5. An output of the result of comparison by the first comparator 4 is latched in first D-FF 8 by a clock DK1 from a clock input terminal 10, and the logic of an output of the FF 8 and an output of the comparator 5 is computed in an AND circuit 6. An output of this circuit 6 is latched in second D-FF 9 by a clock from a clock input terminal 11 and the result VO of determination is outputted from a signal output terminal 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a voltage determination circuit, and particularly to a voltage determination circuit that discretely determines whether an analog voltage is within a standard range.

BACKGROUND ART Conventionally, a circuit shown in FIG. 5 is known as a voltage determination circuit that determines whether the level of an analog voltage is within a standard range. In this circuit, the input signal ■
1 is input, the first reference voltage 11 is input to the first reference voltage input terminal 2, and the second reference voltage Vr2 is input to the second reference voltage input terminal 3.

The input signal Vl is input to the positive input of the comparator 4 and the negative input of the comparator 5. The reference voltage VB-1 is input to the negative side input of the comparator 4, and the reference voltages 2 and 2 are input to the positive side input of the comparator 5. The outputs of comparators 4 and 5 are AND
The signal is inputted to the circuit 6, where it is ANDed and outputted from the signal output terminal 7 as a judgment output (i).

In FIG. 5, the lower limit voltage of the input voltage range is given to the reference voltage ■rl, and the upper limit voltage of the input voltage range is given to the reference voltage Vr2.

According to this circuit, when the input voltage is lower than the standard voltage range, the output of comparator 4 becomes "L" level, and when the input voltage is higher than the standard voltage range, the output of comparator 5 becomes "L" level.
" level, and the output terminal 7 is output through the AND circuit 6.
is set to L” level to notify that the voltage is outside the standard voltage range.

Further, when the input voltage is within the standard voltage range, the outputs of comparators 4 and 5 both become "H" level, and the signal output terminal 7 is set to H" level through the AND circuit 6, so that the output voltage is within the standard voltage range. Let me know.

[Problems to be Solved by the Invention] However, in the conventional voltage determination circuit described above, when determining a periodically fluctuating level such as a sine wave peak value determination circuit, for example, the voltage determination circuit continuously performs voltage determination even at times other than the determination time. The disadvantage is that it is difficult to judge pass/fail because the judgment is made based on the following criteria.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a voltage determination circuit that can perform continuous determination at arbitrary timings even regarding periodic waveforms.

[Means for Solving the Problems] A voltage determination circuit according to the present invention includes a first comparator having an input signal as a positive input and a first reference voltage as a negative input, and a first comparator having an input signal as a negative input. a second comparator which receives a second reference voltage as its positive input; a first D-flip-flop circuit which latches the output of the first comparator with a first clock signal; an AND circuit that receives the output of the D-flip-flop circuit and the output of the second comparator and outputs the logical product; and a second D-flip-flop that latches the output of the AND circuit with a second clock signal. the first. It is characterized in that a second clock signal is input at a predetermined timing, and the output of the second D-flip-flow 71 circuit is used as a judgment output.

[Operation] According to the present invention, the first comparator compares the input signal with the first reference voltage, and the result is transmitted to the first reference voltage using the first clock signal.
The D-flip-flop circuit (hereinafter abbreviated as D-FF) of
and the reference voltage of the first D-FF.
The result of logical product with the latch output of is latched into the second D-FF using the second clock signal. Therefore, by applying the first and second clock signals alternately, for example, by matching the peak timing of the periodic waveform, it is possible to continuously determine the level of the peak value of the periodic waveform.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a voltage determination circuit according to an embodiment of the present invention. In this circuit, an input signal v1 is input to a signal input terminal 1, and a first reference voltage input terminal 2 receives an input signal v1.
The reference voltages v, , l are input to the second reference voltage input terminal 3, and a second reference voltage r2 is input to the second reference voltage input terminal 3. The input signal V is input to the positive input of the comparator 4 and the negative input of the comparator 5. Also, the reference voltage ■r1 is the comparator 4
The reference voltage Vr2 is input to the positive input of the comparator 5. The output of comparator 4 is D-FF8
and the output of D-FF8 and the output of comparator 5 are:
It is input to the AND circuit 6. The output of the AND circuit 6 is input to the D-FF 9, and the output of the D-FF 9 is output from the signal output terminal 7 as a judgment output. The clock signal CK of the D-FF8 is given via the clock input terminal 10, and the clock signal CK of the D-FF9
2 is applied via the clock input terminal 11.

In this circuit, the lower limit voltage of the input voltage range is given to the reference voltage vr1, and the upper limit voltage of the input voltage range is given to the reference voltage r2.

FIG. 2 is a time chart during the operation of the circuit of this embodiment. In FIG. 0, time 1. From t2 to t2, the reference voltage V y 1
A lower limit voltage is applied from , and the comparator 4 makes a comparison decision. Similarly, from time t3 to t4, the upper limit voltage is applied from the reference voltage Vr2, and at time 0, when the comparator 5 makes a comparison, the clock signal CK1 is applied to the D-FF8.
The determination result from the comparator 4 is latched into the D-FF8. Further, at time t6, clock signal CK2 is applied to D-FF9, and the AND result of the determination result of comparator 5 and the determination result at time t5 is latched to D-FF9. If the input voltage vI is within the standard voltage range, HI
I level is obtained.

According to this circuit, when the input voltage Vl has a periodic waveform such as a sine wave, the peak value etc. can be determined by inputting the clock signals CK, CK2 at the same period in accordance with the peak timing.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. In this circuit, reference voltage input terminals 2 and 3 in FIG. 1 are commonly used as one reference voltage input terminal 12.

In this embodiment, the reference voltage from the reference voltage input terminal 12 is determined by inverting the rectangular waveform reference voltage vr whose amplitude is the difference between the lower limit voltage and the upper limit voltage in synchronization with the clock signals CKl and CK2. The lower limit determination can be repeated alternately, and the determination result can be latched in the D-FF8.9.

[Effects of the Invention] As described above, the present invention has the advantage that by latching the output of the comparator, it is possible to continuously determine the peak value of a periodic waveform and voltages such as DC voltage.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a voltage determination circuit according to an embodiment of the present invention, FIG. 2 is a time chart diagram showing the operation of the circuit of FIG. 1, and FIG. 3 is a voltage determination circuit according to another embodiment of the present invention. FIG. 4 is a circuit diagram showing the determination circuit, FIG. 4 is a time chart showing the operation of FIG. 3, and FIG. 5 is a circuit diagram showing a conventional voltage determination circuit. 1; Signal input terminal, 2, 3, 12; Reference voltage input terminal,
4, 5; Comparator, 6: AND circuit, 7: Signal output terminal,
8.9; D-FF, 10, 11; Clock input terminal

Claims (1)

[Claims] (1) A first comparator having an input signal as a positive input and a first reference voltage as a negative input, and a second comparator having the input signal as a negative input and a second reference voltage as a positive input. a comparator; a first D-flip-flop circuit that latches the output of the first comparator with a first clock signal; This A
A second circuit that latches the output of the ND circuit with a second clock signal.
and a D-flip-flop circuit, the first and second clock signals are input at predetermined timings, and the output of the second D-flip-flop circuit is used as a determination output. Voltage judgment circuit.