JPH02171096A - Time synchronizing system for multi-processor exchange system - Google Patents

Abstract

PURPOSE:To decrease time deviation between a master and each processor considerably by providing a means outputting time information generated from a clock means being the hardware to a loop bus and a means fetching the information from the bus and outputting it to a processor. CONSTITUTION:When a processor CPi sets the time to a clock means, the time information from a master clock means A being the hardware is sent to a loop bus 6 at all times for a prescribed period by a time information supply device B. The processor CPi reads the time information propagated onto the loop bus 6 through an interface device E at a prescribed period by a time information reader C and stored in a memory. Since the processor can read the information at any time, the timewise deviation between the master clock means and the clock means of each processor is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock synchronization method for a multiprocessor switching system.

[Conventional technology]

Conventionally, in a multiprocessor exchange system configured by connecting a plurality of processors for controlling exchange operations via a loop bus, the clocks of each processor were synchronized as follows. That is, a certain processor is equipped with a hardware clock means serving as a mask, and software reads time information from this clock means at a constant cycle and sends it to each processor via a loop bus. When each processor receives this time information from the loop bus, it updates the time of its own software clock means based on the information, and establishes synchronization with the mask clock means.

[Problem to be solved by the invention]

In such conventional clock synchronization methods, as mentioned above, a specific processor sends out time information using software.
Each processor also receives and receives time information using software and updates the time of its own clock means, so it takes time to process the time information transmission and reception, and the time of the mask's clock means is updated.
There is a problem in that a time lag occurs between the clock means of each processor.

An object of the present invention is to provide a clock synchronization method for a multiprocessor exchange system that solves these problems and makes it possible to extremely minimize the time lag between the clock means of the mask and the clock means of each processor. It's about doing.

[Means to solve the problem]

The present invention is a multiprocessor exchange (^
In the clock synchronization method of the system, a hardware clock means, a time information supply device that outputs time information generated by the clock means to the loop bus, and a time information supply device that takes in the time information from the loop bus and supplies it to the processor. The present invention is characterized in that it is provided with a time information reading device for outputting the time information.

〔Example〕 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an example of a multiprocessor switching system implementing the clock synchronization method according to the present invention.

This system is an exchange device EX.

The exchange processor CP that controls the exchange bag ffEX, the exchange processor CP that controls the exchange bag ffEX, and the other loop bus 6
It is connected and configured by. The processor CP is connected to the loop bus 6 through the bus interface device gD, and a hardware clock means A and a time information supply device B are provided directly to the processor CP, and the clock means A is connected to the loop bus 6 through the bus interface device gD. Processor CP.

The clock means A and the time information supply device B are connected to a time reading interface 2, and the time information supply device B is connected to a bus interface device by a time insert interface 3. On the other hand, the processor CP is connected to the loop bus 6 through the bus interface device E, and the processor CPj is provided with a time information reading device C, which is connected to the bus interface device E through the time reading interface 4, and the time information reading device C is connected to the bus interface device E through the time reading interface 5. is connected to the processor CP by. Although the figure only shows the CP as the processor that receives and receives time information for simplicity, in reality, there are multiple processors that receive and receive time information.

Next, the operation will be explained. After the processor CPi sets the time in the clock means, the clock means A continues to update the time by itself. The time information supply device WB reads time information from the hardware clock means A at regular intervals and sends the time information to the loop bus 6 through the bus interface device. On the other hand, on the processor CP side, the time information reading device C reads the time information flowing on the loop bus 6 through the bus interface device E at regular intervals and stores it in its memory. Then, the processor CPj reads this stored time information from the time information reading device C at any time, and reads out the stored time information from the time information reading device C.
can obtain time information from the computer and update the time of its own software clock means based on this information. Also, on the side of another processor (not shown) that receives and receives time information, a time information reading device and a processor operate in the same manner as in the case of processor CPj, and processor CPj operates.

Establish synchronization with

As described above, according to the clock synchronization method of the present invention, the time information from the clock means of the hardware mask is constantly sent to the loop bus at a constant cycle by the time information supply device, and the processor side that receives it Since the time information reading device reads and stores the time information, and the processor can read it at any time, it is possible to make the time difference between the clock means of the mask and the clock means of each processor extremely small. Become.

〔Effect of the invention〕

As explained above, the present invention provides a clock synchronization method for a multiprocessor exchange system configured by connecting a plurality of processors that control exchange operations via a loop bus, and provides a hardware clock means and a clock generated by the clock means. A time information supply device that outputs information to the loop bus, and a time information reading device that takes in time information from the loop bus and outputs it to the processor are provided.

Therefore, according to the clock synchronization method of the present invention, the time information from the clock means of the hardware mask is constantly sent to the loop bus at a constant cycle by the time information supply device, and the processor side that receives and receives the time information Since the reading device reads and stores the time information, which can be read out by the processor at any time, it is possible to minimize the time lag between the clock means of the mask and the clock means of each processor.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a multiprocessor switching system implementing the clock synchronization method of the present invention. 1... Clock means control interface 2... Time reading interface 3... Time insert interface 4... Time reading interface 5.
...Time readout interface 6e...Loop bus CPi, cp,...Exchange processor EX5, EX,
... Exchange device A ... Clock means B ... Time information supply device C ... Time information reading device

Claims (1)

[Claims] (1) In a clock synchronization method for a multiprocessor exchange system configured by connecting a plurality of processors that control exchange operations via a loop bus, a hardware clock means and time information generated by this clock means are transmitted to the loop bus. A clock synchronization method for a multiprocessor exchange system, comprising: a time information supply device for outputting time information; and a time information reading device for taking in the time information from the loop bus and outputting it to the processor.