JPH02170718A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To speed up access and to prevent the degradation of reliability by charging and discharging a signal output terminal by means of a second output buffer circuit on the basis of current driving capacity, and thereafter charging and discharging the signal output terminal by means of a first output buffer circuit on the basis of larger current driving capacity. CONSTITUTION:When the output of an output terminal rises or falls, since the output is driven by a second output buffer 15 whose driving ability is small, a noise caused by the sudden flow of the large current to a power source is eliminated. When the output is made into a potential having a certain level, the output is driven by a first output buffer 14 having the large current driving ability. Thus, the speed up of the access at the time of reading and prevention of reliability degradation can be satisfied.

Description

DETAILED DESCRIPTION OF THE INVENTION OBJECTS OF THE INVENTION Field of Industrial Application This invention relates to a semiconductor memory device with an improved output buffer circuit.

(Prior Art) A semiconductor memory is provided with an output buffer circuit for outputting data to the outside of the memory.

FIG. 5 is a circuit diagram showing the configuration of a data read circuit in a conventional semiconductor memory device. Cell data CLD read from the memory cell is detected as data D1 by the sense amplifier 51 and supplied to the latch circuit 52. The output data D2 of the output circuit 52 is supplied to the output buffer circuit 53.

The output buffer circuit 53 has the latch data D2.
and a control signal S, a NAND gate circuit 55 which is supplied with the latch data D2 and the inverted control signal S, and a power supply voltage VCC and an output terminal 5.
A P-channel P14OS transistor 57 is inserted between the source and the drain and the gate is supplied with the inverted signal of the NOR gate circuit 54, and the source and the drain are inserted between the ground voltage VSS and the output terminal 56. An N-channel MOS transistor 58 is provided at its gate to which the inverted signal of the NAND gate circuit 55 is supplied.

The control signal S is the chip enable signal CE.

This is a logical sum signal of the output enable signal OE and the write enable signal WE, and these signals are all “0”.
”, this signal S becomes “0” and the output buffer circuit 53 becomes operable.

That is, when the latch data D2 becomes "1" when the signal S is "0", the outputs of the NOR gate circuit 54 and the NAND gate circuit 55 both become "0", and the P channel M
OS) transistor 57 is turned off and N-channel MOS transistor 58 is turned on.

At this time, the output terminal 56 is discharged via the N-channel MOS transistor 58 which is on, and data "0" is output. On the other hand, when the latch data D2 becomes "0", the NOR gate circuit 54 and the NAND gate circuit 5
Both outputs of 5 become "1", P-channel MOS) transistor 57 is turned on, and N-channel MOS) transistor 58 is turned on.
is turned off, and the output terminal 56 is charged via the P-channel MOS transistor 57 which is turned on, and data of "1" is output.

Note that when any one of the signal CE, the output enable signal OE, and the write enable signal WE is '1#', the control signal S also becomes "1". At this time, the output of the NOR gate circuit 54 becomes "40", and the output of the NAND gate circuit 55 becomes "1", both P-channel and N-channel MOS) transistors 57 and 58 are turned off, and the output buffer circuit 5
3 does not perform data output operation.

By the way, in the conventional memory device described above, in order to speed up the access operation during reading, the element size of the transistor 57.5g in the output buffer circuit 53 is used as large as possible, and the charging and discharging of the output terminal 50 is need to be done in a short period of time. But electric fi,? Since the wiring for lt voltage VCC or ground voltage VSS includes an inductance component, the output terminal 5
When B is charged and discharged with a large current, large voltage fluctuations occur in the voltage VCC or the voltage VSS when the output rises and falls, as shown in the waveform diagrams of FIGS. 6(a) and 6(b). Since this voltage fluctuation is transmitted as noise to other circuits in the memory, there is a risk that other circuits, particularly input buffers, may misdetect the input level and malfunction. Therefore, by reducing the current drive capability of the transistors 57 and 58 in the output buffer circuit 53 to some extent, the generation of power supply noise can be suppressed at the expense of some access speed, as shown in the waveform diagram of FIG. 6(C). This is done to prevent a decline in reliability.

(Problem 8 to be Solved by the Invention) As described above, the conventional semiconductor memory device has the drawback that it is not possible to both increase the access speed during reading and prevent reliability from decreasing due to noise.

This invention has been made in consideration of the above circumstances, and its purpose is to provide a semiconductor memory device that satisfies both the acceleration of access speed during reading and the prevention of reliability deterioration. be.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor memory device of the present invention includes a first output transistor, and a first output transistor that charges and discharges a signal output terminal based on a read signal from a memory cell. an output buffer circuit, and a second output transistor whose current driving capacity is set smaller than that of the first output transistor, and based on the read signal, the output buffer circuit The semiconductor memory device of the present invention further includes a second output buffer circuit that charges and discharges a signal output terminal, and a logic circuit that takes a logic between a read signal from a memory cell and the control signal, and this logic circuit. A first output buffer circuit includes a first output transistor whose conduction is controlled by the output of the signal output terminal, and which charges and discharges the signal output terminal; A second output transistor whose driving capacity is set to be small; a switch transistor inserted between this transistor and a power supply and whose conduction is controlled by a control signal; and a second output buffer circuit that charges and discharges the signal output terminal.

(Function) When a read signal from a memory cell is supplied, first,
The second output buffer circuit charges and discharges the signal output terminal with a relatively small current drive capability. After this, the first output buffer circuit charges and discharges the signal output terminal with a relatively large current driving capability.

(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a data read circuit in an apparatus according to an embodiment of the present invention. Cell data CLD read from a memory cell (not shown) is detected by the sense amplifier 11 as data D1, and the latch circuit 12
is supplied to Latch data D2 of this latch circuit 12
is supplied to the output buffer circuit 13.

The output buffer circuit 13 includes a first output buffer 14.
and a second output buffer 15 are provided, and the output ends of both output buffers are commonly connected to an output terminal 16.

The first output buffer 14 is supplied with an inverter 17 for inverting the control signal S, a NOR gate circuit 18 to which the latch data D2 and the control signal S are supplied, and the latch data D2 and the output of the inverter 17. NA
ND gate circuit 19, inverter 20 for inverting the output of the NOR gate circuit 1B, and NAND gate circuit 1
Inverter 21.9 inverts the output of 9. An output P is inserted between the source and the drain between the power supply voltage VCC and the output terminal 16, and the output of the inverter 20 is supplied to the gate.
Channel MO3) An output transistor 22 whose source and drain are inserted between the ground voltage Vss and the output terminal 16 and whose gate is supplied with the output of the inverter 21.
A channel MOS transistor 23 is provided.

The second output buffer 15 includes an inverter 24 that inverts the control signal S, and a power supply voltage V. C and output terminal 16
A P-channel MO transistor 25 for a switch and a P-channel MO transistor 2B for an output transistor 2B, whose source and drain are inserted in series between the transistors and the gates thereof, and each of the control signal S and the latch data D2 is supplied to the transistor 25.
An output N-channel MOS transistor 27 whose source and drain are inserted in series between the ground voltage VSS and the output terminal 16 and whose gate is supplied with the latch data D2 and the output of the inverter, and a switch N-channel MOS A transistor 2B is provided. In this second output buffer 15, at least the transistor 26 has an element size larger than that of the first output buffer 1.
It is set sufficiently smaller than the transistor 22 in 4,
The current driving ability is smaller than that of this transistor 22, and at least the element size of the transistor 27 is set to be sufficiently smaller than that of the transistor 23 in the first output buffer 14, and the current driving ability is smaller than that of this transistor 23. has been smaller than.

The control signal S is the OR signal of the chip enable signal CE, the output enable signal OE, and the write enable signal WE, as in the conventional case, and when these signals are all "0°, this signal S is "0". ", and the output buffer circuit 13 becomes operational.

Next, the operation of the circuit configured as above will be explained.

First, when the signal S is "0", the output buffer circuit 13 becomes operational. That is, the first output buffer 14
Now, NOR gate circuit 18 and NAND gate circuit 1
9 output is “1° or “” according to latch data D2.
0” can be set.

Further, in the second output buffer 15, both the switch P-channel MOS transistor 25 and the N-channel MOS transistor 28 are turned on.

When the latch data D2 becomes “1” in this state, first,
N-channel MOS transistor 27 in second output buffer 15 is turned on. The output terminal 16 is discharged via this transistor 27. At this time, since the current driving capability of the transistor 27 is reduced, the output terminal 16 is discharged to "0" relatively slowly. After a predetermined period of time has passed since the latch data D2 changes to "1", the outputs of the NOR gate circuit 18 and the NAND gate circuit 19 in the first output buffer 14 change to "0".

As a result, the P-channel MOS) transistor 22 is turned off, the N-channel MOS) transistor 23 is turned on, and the output terminal 16 is discharged via the turned-on N-channel MOS) transistor 23. Here, since the current driving capability of the transistor 23 is made larger than that of the N-channel MOS transistor 27 in the second output buffer 15, the current driving capability of the output terminal 16, which was previously performed relatively slowly by the transistor 27, is increased. Discharging to '0' occurs rapidly by turning on this transistor 23.

On the other hand, when the signal S is “O”, the latch data D2 is “0”.
'', the P-channel MOS transistor 26 in the second output buffer 15 is turned on, and the output terminal 16 is charged via this transistor 26.At this time,
Since the current driving capability of the transistor 26 is small, charging of the output terminal 1G to "1" is performed relatively slowly. After a predetermined period of time has passed since the latch data D2 changes to “0”, the NOR in the first output buffer 14
The outputs of the gate circuit 18 and the NAND gate circuit 19 are “
As a result, the P-channel MOS transistor 22 is turned on, and the N-channel MOS transistor 2 is turned on.
P-channel MOS transistor 2 turns off and turns on.
2, the output terminal 16 is charged. Also in this case,
Since the current driving capability of the transistor 22 is made larger than that of the P-channel MOS transistor 2B in the second output buffer 15, the current driving ability of the output terminal 16, which was previously performed relatively slowly by the transistor 26, is set to "1". The charging of the transistor 22 is rapidly performed by turning on the transistor 22.

Note that when any of the signal CE, output enable signal OE, and write enable signal WE is "1", the control signal S also becomes "1m". At this time, in the first output buffer 14, the NOR gate circuit 18 is Output is “0”
” The output of the NAND gate circuit 19 becomes “1°, and P
Channel and N-channel MOS transistors 22.23
Since both are turned off, the first output buffer 14 does not output data. In addition, the second output buffer 15
Since both the P-channel MOS transistor 25 and the N-channel MOS transistor 28 are turned off, the second output buffer 15 also does not output data.

FIG. 2 is a waveform diagram showing a potential change at the output terminal 16 when the output data from the output buffer circuit 13 changes from "0" to "1 degree" in the memory device of the above embodiment in comparison with a conventional case. It is.

In the case of the above embodiment, first, the output is charged by operating the second output buffer 15, which has a small current drive capacity. Therefore, as shown in waveform a, the slope of the waveform is It becomes gentle. Therefore, when the output rises, the voltage VC
C or voltage VSS will not undergo large voltage fluctuations, and noise generation can be prevented. Then, when the output potential rises to a certain extent, the first output buffer 14 having a large current drive capacity starts charging the output, and the waveform rapidly rises to "1". Therefore, high-speed access can also be achieved.

On the other hand, the waveform shown in FIG. 5 is obtained when the current drive capacity of the P-channel and N-channel MOS transistors 57 and 58 in the output balance circuit 53 is set sufficiently large in the conventional device shown in FIG. In order to perform high-speed access, the rise is rapid, and the above-mentioned noise is generated in the power supply wiring. Furthermore, waveform C is
In the conventional device shown in FIG. 5, the current drive capabilities of the P-channel and N-channel MOS transistors 57 and 58 in the output balance circuit 53 are set to be sufficiently small to prevent noise generation. The startup becomes slow and high-speed access cannot be performed.

FIG. 3 is a circuit diagram showing the configuration of a data read circuit of a semiconductor memory device according to another embodiment of the present invention. The memory device of this embodiment is configured to transmit complementary signals through a signal path from a sense amplifier to an output buffer circuit. That is, cell data CLD read from a memory cell (not shown) is detected by the sense amplifier 31 as complementary data DI, DI, and the latch circuit 3
2. Complementary data D2 latched by this latch circuit 32. D2 is supplied to the output buffer circuit 33.

The output buffer circuit 33 includes a first output buffer 34.
and a second output buffer 35 are provided, and the output ends of the 100 output buffers are commonly connected to an output terminal 36.

The first output buffer 34 includes an inverter 37 for inverting the control signal S, an inverter 38 for inverting the latch data D2, a NAND gate circuit 39 to which the output of the inverter 37 and the latch data D2 are supplied, and the control signal NOR to which S and the output of the inverter 38 are supplied.
A gate circuit 40 has a source and a drain inserted between the power supply voltage VCC and the output terminal 36, and the gate has the above NAND
An output P-channel MOS transistor 41 to which the output of the gate circuit 39 is supplied, a ground voltage VSS and an output terminal 3
An output N-channel MOS transistor 42 is inserted between the source and the drain between the NOR gate circuit 6 and the NOR gate circuit 40, and has a gate supplied with the output of the NOR gate circuit 40.

The second output buffer 35 includes an inverter 43 for inverting the control signal S, a power supply voltage VCC and an output terminal 36.
A P-channel MOS (P channel MOS) transistor 44 for a switch and an N transistor 44 for an output whose source and drain are inserted in series between the switch and the gate to which the control signal S and the output data D1 of one of the sense amplifiers 31 are respectively supplied. Channel M
OS transistor 45, ground voltage VSS and output terminal 3B
an N-channel MOS transistor 46 for output and a switch N-channel MOS transistor 46 whose source and drain are connected in series and whose gates are supplied with the other output data D1 of the sense amplifier 31 and the output of the inverter 43;
OS transistor 47, an output P-channel MOS whose source and drain are inserted between the series connection point of the transistors 44 and 45 and the output terminal 3G, and whose gate is supplied with the output data D1 of the sense amplifier 31) transistor 48, an output P-channel MOS transistor whose source and drain are inserted between the series connection point of the transistors 47 and 46 and the output terminal 36, and whose gate is supplied with the output data D1 of the sense amplifier 31. 49 are set and marked. This second output buffer 35
At least the transistors 45 and 48 are set to have a sufficiently smaller element size than the transistor 41 in the first output buffer 34, have a current drive capacity smaller than that of the transistor 41, and have a small (
Both of the transistors 46 and 49 are set to have element sizes sufficiently smaller than the transistor 42 in the first output buffer 34, and have a current drive capability smaller than that of the transistor 42.

Further, the control signal S is the OR signal of the chip enable signal CE, the output enable signal OE, and the write enable signal WE, as in the embodiment shown in FIG. 1, and these signals are all "0". When this signal S
becomes "0", and the output buffer circuit 33 becomes operational.

In a circuit having such a configuration, when the signal S is "0", the output buffer circuit 33 is in an operable state. That is, in the first output buffer 34, the outputs of the NAND gate circuit 39 and the NOR gate circuit 40 are the latch data D.
2. A state can be set to "1" or "0" depending on D2. In the second output buffer 35, both the P-channel MOS transistor 44 and the N-channel MOS transistor 47 for switching are turned on.

In this state, if data is read from a memory cell (not shown) and even a slight potential difference occurs between the output data D2 and D2 of the sense amplifier 31, in the second output buffer 35, the N-channel MOS transistor 45 and the P-channel MOS
3) The transistor 48 or N-channel MO8) The transistor 4B and the P-channel MOS transistor 49 are each turned on more strongly, and the output terminal 36 is charged or discharged. At this time, each of the above transistors 4
Since the current drive capability of 5.4g and 46°49 is small, the output terminal 3θ is discharged to “0” or
Charging to 1" is performed relatively slowly. Next, after a predetermined period of time has passed after the latch data D2.D2 of the latch circuit 32 is determined, the NAND gate circuit 39 and the NOR gate circuit in the first output buffer 34 are charged. As a result, one of the P-channel and N-channel MOS transistors 41..42 is turned on, and the output terminal 3B is rapidly charged or discharged via the turned-on transistor.

In the case of this embodiment device as well, when the output from the output terminal 36 rises and falls, the output is driven by the second output buffer 35, which has a small current driving capacity, so that a sudden large current flows through the power supply. Generation of noise can be prevented.

Then, when the output reaches a certain level of potential, the output is driven by the first output buffer 34 having a large current drive capability, so that high-speed ACMOS can be realized.

FIG. 4 is a circuit diagram showing the configuration of a data read circuit of a semiconductor memory device according to still another embodiment of the present invention. In the memory device of this embodiment, instead of the complementary outputs DI, DI of the sense amplifier 31 as inputs to the second output buffer 35 in the embodiment device of FIG. Complementary data D2. It is designed to supply D2. Latch data D2 of this latch circuit 32. Since the potential difference of D2 is sufficiently expanded compared to the complementary outputs Di and D1 of the sense amplifier 31, the current consumption in the second output buffer 35 is reduced compared to the case of the embodiment device of FIG. be able to.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor memory device that satisfies both the increased access speed during reading and the prevention of reliability deterioration.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a data read circuit in an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the embodiment described above, and FIG. 3 is a circuit diagram of another embodiment of the present invention. FIG. 4 is a circuit diagram showing the configuration of a data read system circuit of a semiconductor memory device according to another embodiment of the present invention; FIG. The figure is a circuit diagram of a conventional device, and FIG. 6 is a waveform diagram for explaining the conventional device. 11...Sense amplifier, 12...Latch circuit, 13
... Output huff circuit, 14... First output buffer, 15... Second output buffer, 16... Output terminal, 17, 20.21.24... Inverter, 18.
...NOR gate circuit, 19...NAND gate circuit, 22.25.26...P channel MOS transistor, 23.27.28...N channel MO3) transistor. Applicant's agent Patent attorney Takehiko Suzue

Claims (2)

[Claims] (1) A first output buffer circuit that includes a first output transistor and charges and discharges a signal output terminal based on a read signal from a memory cell; and a second output buffer circuit that includes a second output transistor set to be small and charges and discharges the signal output terminal before the first output buffer circuit based on the read signal. A semiconductor memory device characterized by: (2) A logic circuit that takes logic between a read signal from a memory cell and a control signal, a first output transistor whose conduction is controlled by the output of this logic circuit, and a first transistor that charges and discharges a signal output terminal. an output buffer circuit; and a second output transistor whose conduction is controlled by the read signal and whose current drive capability is set smaller than that of the first output transistor.
an output transistor, a switch transistor inserted between this transistor and a power source and whose conduction is controlled by a control signal, and a first output transistor that charges and discharges the signal output terminal before the first output buffer circuit. 1. A semiconductor memory device comprising: two output buffer circuits.