JPH02170665A - Picture processor - Google Patents

Abstract

PURPOSE:To quickly execute a picture processing to form a moving picture by arbitrarily setting the address initial value of at least one of a writing address generating means and a reading address generating means. CONSTITUTION:Each of RAMs 401 and 402 has the 8k-byte capacity, and picture data by one-line components (8000 picture elements) in a main scanning direction can be stored there. A picture memory is constituted with, what is called, a double buffer constitution, and buffers 408 and 410 or buffers 409 and 411 perform the latch operation synchronously with the access to the RAM 401 or 402. A writing address counter 403 is incremented (counted up) from a fixed counting initial value (address initial value) one by one in accordance with a signal WCK, but the address generating operation of a reading address counter 404 can be controlled by various edition processing signals.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device for forming an edited image that is a wholly or partially transformed original image.

[Conventional technology]

In recent years, image forming devices equipped with image processing devices that perform digital signal processing on image signals, such as digital copiers, facsimile machines, and printers, have improved gradation and color reproducibility on the one hand, while on the other hand In recent years, image editing functions have been diversified.

The image editing function is a function to create an image by intentionally transforming the original image. Edited images created using this function include moving images that change the arrangement of images,
There are so-called mirror images (mirror images) in which the original image is symmetrically reversed, italic images suitable for stylizing characters and the like by tilting the original image, and repeated images formed by repeating a part of the original image.

Forming a moving image is performed, for example, when forming an image on a sheet of paper that is larger than the original image, and when you want to match the center of the image with the center of the sheet, and a mirror image is used, for example, to create a block copy. can. Additionally, italic images are useful for lettering, and repeated images are useful when creating multiple labels.

When forming these edited images, generally a predetermined amount of image data is stored in an image memory, and the data in the image memory is replaced based on arithmetic processing by an arithmetic unit such as a microprocessor.

[Problem to be solved by the invention]

However, if the image processing to form the edited image is performed using software using a microprocessor etc., the degree of freedom in editing can be increased, but in reality, a certain amount of processing time is required, which is limited by the calculation processing speed. Therefore, there was a problem in that real-time image formation could not be performed.

Further, in order to simplify the configuration, if one image memory is used in common to perform multiple types of image editing processing, the software becomes complicated and there is a problem in that the processing speed further decreases.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide an image processing device that can perform image processing for forming a moving image at high speed.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention provides a clock generation circuit that simultaneously outputs a write clock signal and a read clock signal, and a clock generation circuit that alternately writes a predetermined amount of sequentially manually inputted image data for each line. The other includes first and second image memories that read out written image data when performing an operation, and write address generation means that specifies addresses for writing to the first and second image memories in accordance with a write clock signal. , readout address generation means for specifying readout addresses of the first and second image memories according to the readout clock signal,
The present invention is characterized in that the initial count value of at least one of the write address generation means and the read address generation means can be arbitrarily set.

(Operation) The clock generation circuit simultaneously outputs a write clock signal and a read clock signal.

The first and second image memories alternately write a predetermined amount of sequentially input image data for each line, and when one performs a writing operation, the other reads the written image data.

The write address generation means updates (increments or decrements) the address according to the write clock signal.
and designate the writing addresses of the first and second image memories.

The read address generation means updates the address in accordance with the read clock signal, and specifies the read address of the first and second image memories.

The initial address value of at least one of the write address generation means and the read address generation means is set to an arbitrary value.

This generates a moving image data signal that shifts the image forming position.

〔Example] Embodiments of the present invention will be described below with reference to the drawings.

7 is a perspective view showing the image reader unit 14 of the image processing device B incorporated in a digital copying machine, FIG. 8 is a plan view of the image sensor 11, and FIG. 9 is a CCD shown in FIG. 8.
FIG. 3 is an enlarged view showing the sensor chip lla.

A digital copying machine consists of an image processing device B (see Figure 5), which performs various signal processing on pixel signals read by scanning an image of a document, and outputs them as image signals;
The printer includes a laser printer unit (not shown) that forms a color image using a well-known electrophotographic method based on image signals sent from the printer.

The image reader unit 14 equipped with the image sensor 11 is placed on the document table glass 18! ! The placed document is scanned in line in the sub-scanning direction.

As shown in FIG. 8, the image sensor 11 includes five contact type CCD sensor chimps lla, 11a...
are arranged in a staggered manner so as to be continuous in the horizontal direction (main scanning direction) and alternately with a certain pinch in the vertical direction (sub scanning direction). Since there is a constant pitch in the sub-scanning direction, the rear CCD sensor chip Ila in the sub-scanning direction
There is a delay in the output signal from the front CC.
This is corrected by delaying the output signal from the D sensor chip lla.

Each CCD sensor chip lla has a size of 62.5. um
(d=1/''16m5) A large number of square elements are arranged in one row.

Each element is divided into three parts, one divided area is R (red),
A filter is provided to receive light of one of the three primary colors of G (green) and B (blue).

FIG. 5 is a block diagram of the electric circuit of image processing device B. FIG.

The photoelectric conversion signals output in parallel from the CCD sensor unit 11 are processed by a digitization processing circuit 1 including an AD converter.
After being quantized by 01 and converted to 8-bit (256th floor v4) image data, the 5-channel synthesis circuit 1
At step 02, the signal is converted into a serial signal corresponding to the pixel arrangement.

Next, a white balance correction circuit 103 performs white balance correction to compensate for the difference in spectral sensitivity of the CCD sensor chip for each RGB color, and a shading correction circuit 104 performs a white balance correction to compensate for the difference in spectral sensitivity of the CCD sensor chip for each RGB color. ) and each CCD sensor chip, and the data signal that was proportional to the intensity of reflected light is converted according to the reading range of the original and becomes proportional to the density of the original. is converted into a concentration data signal.

The color correction circuit 105 calculates the three primary colors YSM of printing toner from the image data corresponding to the density of each RGB color as described above.
, masking processing to generate image data corresponding to C and UC to generate image data corresponding to Bk (black).
R processing and the like are performed, and a gamma correction circuit 106 performs gamma correction based on the background color and density gradient of the original.

The color editing circuit 107 performs three types of color image editing processing: negative/positive inversion, color change, and paint (filling).

Image data signals 077~ that have undergone these various signal processes
Reference numeral 70 denotes a scaling/editing processing circuit 108, which performs scaling processing using a thinning method or interpolation method, and editing processing for forming edited images such as moving, mirroring, italics, and repeating, including the output timing and output order of image data. Alternatively, processing is performed to change the scanning speed in the sub-scanning direction.

After that, the MTF correction circuit 109 performs smoothing to prevent the occurrence of moire fringes and edge enhancement to eliminate edge loss, and the gradation reproduction circuit 110 performs binarization processing using the area gradation method and sends it to the laser printer section. Sent. In the laser printer section, image formation is performed by controlling the beam deflection corresponding to the scanning of the document in the main scanning direction and the rotation of the photosensitive drum corresponding to the scanning in the sub-scanning direction.

Note that 111 is a line memory that stores image data at a specific processing stage, and 112 is a line memory that stores image data at a specific processing stage, and 112 is a line memory that stores image data at a specific processing stage. CP that controls the circuit
U (central processing unit) 113 is a ROM in which control programs and various data are stored.

FIG. 1 is a block diagram of the scaling/editing processing circuit 10B.

The scaling/editing processing circuit 108 is the color editing circuit 1 at the previous stage.
Image data signals D77-70 (8-bit parallel signal) inputted from 07 are subjected to scaling processing and editing processing, and outputted as image data signals D87-80 (8-bit parallel signal) to the subsequent MTF correction circuit IO9. Input and output are performed via launch circuits 412 and 413 that perform a launch operation in accordance with the image clock signal 5YNCK, which serves as a reference for the transmission timing of image data between the image processing circuits described above.

Such a scaling/&lii processing circuit 108 includes a clock generation circuit 400 that outputs a write clock signal WCK and a read clock signal RCK simultaneously, that is, in parallel;
A set of RAMs in which a predetermined amount of sequentially input image data is written alternately every line period, and when one performs a writing operation, the other reads out the written image data.
401.402, R according to write clock signal WCK
Write address counter 403\read clock signal R that specifies the address when writing AM401.402
A read address counter 404 specifies the address when reading from the RAM 401, 402 according to CK, a write address WA from the write address counter 403, and a read address RA from the read address counter 404.
Address selectors 405 and 406 to select RAM
It has a line parity counter 407 for selecting write operation or read operation of 401 and 402.

RAM 401 and 402 each have a capacity of 8 bytes and can store image data for one line (8000 pixels) in the main scanning direction, but data writing and reading are done through a common input/output port. Therefore, in order to avoid input/output data collisions, buffers 408 and 410 consisting of D-FFs are provided for RAM 401, and buffers 408 and 410 are provided for RAM 402.
9.411 is provided. Therefore, the image memory configuration is a so-called double buffer configuration, and the buffers 408, 410 and 409, 411 perform a latch operation in synchronization with access to the RAM 401 or RAM 402, respectively.

The write address counter 403 of this embodiment increments by rl from a fixed count initial value (address initial value) for each line in accordance with the signal WCK, that is, performs an amplifier count operation.
04, its address generation operation can be controlled by various editing processing signals, as will be described later.

The line parity counter 407 performs rl-, rl-,
and rH, are alternately exchanged to select the write or read operation of the RAMs 401 and 402.

Based on the signals 0DD-LINE and EVEN-LINE
RAM401.402, address selector 405.4
06, Buffer 4 The switching operations of 08 to 411 are summarized in Table 1.

(The following is a blank space) FIG. 2 is a block diagram of the clock generation circuit 400.

The clock generation circuit 400 uses the image clock signal 5YNCK, which serves as a reference for the transmission timing of image data between each of the image processing circuits described above, as a standard clock signal SCK,
This standard clock signal SCK is used to generate a clock signal TCK by thinning out the standard clock signal SCK using an adder 451.

The CPU 112 gives the adder 451 magnification data (MAG-DATA) determined according to the magnification ratio,
Adder 451 connects MAG-DATA to launch circuit 452
The arithmetic sum data is added to the latch circuit 45.
It is latched at 2. This addition operation is repeated every pulse of the signal 5YNCK, and the carry signal CK-E at the time of addition is
N is a gate circuit 4 whose one input is the signal 5YNCK.
When the arithmetic sum data incremented by 10 MAG-DATA, which is added as the other input to the adder 453, does not exceed the maximum value of the adder 451, the signal CK is output.
-EN becomes "L", and the output of the gate circuit 453 also becomes "L".
”. As a result, the pulses of the signal 5YNCK disappear every predetermined number, and the clock signal TCK is generated by thinning out the signal 5YNCK. Naturally, when l is specified as the magnification ratio, that is, when forming a same-sized image, the signal 5YNCK is not thinned out, and the clock signal TC
The pulse timings of K and the standard clock signal SCK are equal.

The clock signal TCK generated in this manner is applied to the selector 454 together with the signal 5YNCK as the standard clock signal SCK.

The selector 454 writes either the standard clock signal SCK or the clock signal TCK into the write clock signal WC.
K and read the other clock signal RC at the same time.
Select and output as K.

The selection operation of selector 454 is controlled by scaling control enable signal REDUCE.

That is, when forming a reduced image, the signal REDU
CE is "L", and at this time the selector 454 selects the clock signal TCK as the write clock signal WCK and at the same time selects the standard clock signal SCK as the read clock signal RCK.

When forming an enlarged image, the signal REDUCE is "H", and at this time the selector 454 selects the clock signal SCK as the write clock signal WCK and the clock signal TCK as the read clock signal RCK.

These signals WCK have different numbers of pulses per unit time,
Image data signals DB7 to DB80 subjected to scaling processing by accessing RAM401.402 with signal RCK
is generated.

FIG. 3 is a time chart of the scaling process in the case of reduction, and FIG. 4 is a time chart in the case of enlargement.

In these figures, the write operation and read operation of image data corresponding to one line are shown aligned with the edge of one horizontal synchronization enable signal TG.
Actually, as shown in Table 1, write operations and read operations corresponding to one line are performed alternately every line period.

Referring also to FIG. 1, for example, when forming a reduced image with a scaling factor of 2/3, the clock generation circuit 400
Based on MAG·DATA obtained by the calculation by 12°2, a clock signal TCK obtained by thinning out one pulse every three pulses from the signal S Y N CK is output as a write clock signal WCK.

When the vertical synchronization enable signal VD for preventing transmission of the image data signals D77-70 outside the effective image forming range becomes inactive, the latch circuit 412 becomes active and the image data signals D77-70 are inputted from the previous stage as the image data signals D77-70. Image data (■, ■, ■...) as signal 5YNC
Latch according to K.

When processing odd lines, as shown in Table 1, the signal 0DD
-LINE is "L", and the output of the latch circuit 412 is sent to the RAM 401 via the buffer 408.

At this time, the write address WA of the RAM 401 is incremented by one address from the start address A1 in accordance with the double clock signal TCK as the signal WCK in the write address counter 403, and one pixel worth of image is stored at one address by access synchronized with address specification. Since the data is written, the RAM 401 stores a reduced image data group (■, ■, ■, . . . ) in which one pixel out of three pixels of the image data is thinned out.

At the time of reading, the RAM 401 is accessed according to the clock signal SCK having the same pulse period as the signal 5YNCK, and the latch circuit 401 is accessed via the buffer 410.
Image data signals DB'7 to 80 subjected to reduction processing from 3
sent out as.

Furthermore, when forming an enlarged image, for example, if the magnification ratio is set to 3/2, the clock generation circuit 400 generates the clock signal TCK by thinning out one pulse every three pulses from the signal 5YNCK as described above. , which is output as a read clock signal °RCK.

Since the write clock signal WCK is equivalent to the signal 5YNCK, one line of image data (■, ■,
) are written to the RAM 401 in the order of input without being omitted. However, RAM4 in read operation
Since the access to 01 follows the clock signal TCK, the specified period of the even-numbered address corresponds to two periods of the signal 5YNCK, and the latch circuit 413 outputs the even-numbered image data (■, ■, ...). A series of enlarged image data signals D87 to D80 are output.

In this way, the image data signal D generated by differentiating the timing of access during the write operation and read operation of each of the RAMs 401 and 402.
If image formation is performed based on 87 to 80, an image with variable magnification in the main scanning direction can be formed.

Note that the scaling of the image in the sub-scanning direction is performed by changing the scanning speed of the image league unit 14 in the sub-scanning direction. In other words, the scanning speed at the same magnification is V
(mm7 seconds) and the magnification ratio in the sub-scanning direction is a.
The scanning speed during zooming is set to V/a (mm 7 seconds).

Returning to FIG. 1, the initial address value in the read address counter 404 is the load added from the repeating circuit 470 based on the load data LOAD-DATA from the adder circuit 461 to which the movement data MOV・DATA is applied from CPtJ l 12. Set according to signal LOAD.

By appropriately changing this initial address value, it becomes possible to form a moving image in which the image formation position is shifted.

That is, as mentioned above, the capacity of RAM 401 and 402 is 8 bytes (8192 x 8 bits), and "OH" to rl
It is possible to allocate an address (13 bits) of FFFH. On the other hand, the read address counter 404 is 1
It is a 5-bit counter and can generate addresses from "OH" to "r7FFFH". Therefore, as shown in Figure 6, the addresses and large areas of RAM401 and 402 are
00HJ to r5FFFHJ, and the initial count value of the read address counter 404 is used as the load data LOA.
r4000H by D-DATA.

By increasing/decreasing settings around the RAM401
．． The readout position from 402 can be shifted left and right in the main scanning direction. The area in which image data is actually written is determined depending on the pixel density and document size. For example, when an A3 size document is read with 161ii pixels/■, the amount of data for one line is approximately 5 bytes. In this embodiment, the data clear enable signal DATA-CLR is input from the read address counter 404 to the clear terminal of the latch circuit 413 so that the data written in this range is output.

The initial count value of the write address counter 403 is rQ, and when writing, the RAM 401 or R
Image data is written to the AM 402 in order from address (physical address) 0.

Therefore, for example, if the load data LOAD-DATA is
4000H", address (logical address) '40
Reading is performed from 00HJ, that is, physical address "0", and an image is formed at the same position as the original image. For example, if the load data LOAD-DATA is set to "r3000H", the read address counter 40
The increment of 4 is repeated and RAM401.4
The image data is read out from when it reaches "r4000H" to which 02 is assigned. As a result, a moving image shifted to the right is formed.

These shift amounts and shift directions are determined by the movement data MOV.
It can be set appropriately by changing DATA.0 For example, when forming a reduced image in the center of copy paper,
The CPU 112 performs calculations to determine the optimum values of the movement data MO2 and DATA based on the magnification ratio and copy paper size detection signals.

In addition, in the sub-scanning direction, by advancing or delaying the timing of activating the vertical synchronization enable signal VD mentioned above in units of line periods, 1 / l 6 t
Movement can be performed in m increments.

The repetition circuit 470 is for forming a repetition image, and includes a comparator 4711 that compares the output of the read address counter 404 and the repetition data REP-DATA.
Output of comparator 471 and repetition control enable signal R
It consists of a gate circuit 472 to which EP/ON is manually input, and a gate circuit 473 to which the output of the gate circuit 472 and the horizontal synchronization enable signal TG are input.

When the signal REP-ON is inactive (active low), that is, when not forming a repetitive image, the output of the gate circuit 472 is always inactive, and the output of the gate circuit 473, the signal LOAD, is the same as the signal TG. follow. Therefore, in this case, like the write address counter 403, the initial count value is set for each line.

When the signal REP-ON is active, when the count value reaches the repetitive data REP-DATA, the output of the comparator 471 becomes "L" (active). Accordingly, the signal LOAD becomes active, and the read address counter 404 Load data to LOAD -DATA
Initial settings to load the RAM 401 or
Even in the middle of reading one line of M402, the read address counter 404 increments again from the initial count value.
A zero-repetition image in which image data stored in two specific address areas is repeatedly read out to generate a repeat image data signal is useful, for example, when creating a large number of labels.

The variable initial setting circuit 460 is for forming an italic image, and includes the above-mentioned adder 461 and line counter 46.
It is composed of 2. When forming an italic image,
The variable initial setting circuit 460 changes the count initial value of the read address counter 404 at predetermined intervals.

The line counter 462 receives the italic enable signal ANGL.
When E-OFF is "L", the count is increased by the signal TG, and the adder 461 outputs load data LOAD-DATA, which is the sum of the output DOUT of the line counter 462 and the movement data MOV-DATA. Therefore, the initial count value of the read address counter 404 increases every line.

As a result, the formed image becomes an italic image shifted to the left by one pixel for each line.

Note that if the signal TG is thinned out and applied to the line counter 462, it is possible to shift by one pixel for each plurality of lines, and the tilt angle can also be controlled by changing the count step of the line counter 462. . Also, if the line counter 462 is made to perform a down-count operation or the adder 461 is changed to a subtracter,
The direction of the tilt can be reversed.

Further, the read address counter 404 can be switched between an up-count operation and a down-count operation by a mirror enable signal MIRROR.

When signal MIRROR is inactive, read address counter 404 receives load data LOA as described above.
An up-count operation is performed according to the signal RCK from the initial count value set based on D-DATA, but when the signal MIRROR is active, the operation is switched to a down-count operation.

When the read address counter 404 is switched to down-count operation, the image data written in the RAM 401 or the RAM 402 will be read out in order from the one that was written last.

For example, if r5000H is set as the initial count value by load data LOAD-DATA,
Read address counter 404 is logical address r500
Decrement from 0H, RAM401.402
So, the logical address "5o.

From the physical address corresponding to OH, to the physical address “0”
The image data stored within the address range M up to is read out.

The image data signals DB7 to DB8 generated by the down-counting operation of the read address counter 404 in this way
The image formed based on 0 is a so-called mirror image (I image) obtained by symmetrically inverting the original image. This mirror image is used, for example, to create a block copy.

The image processing described above, that is, the scaling processing and the processing for forming each edited image, can be performed individually or in combination as appropriate.

For example, it is possible to repeatedly form reduced and horizontally reversed images in the main scanning direction of a sheet of copy paper.

According to the embodiment described above, the Wj&image data signal is generated by changing the initial count value of the address counter that specifies the address of the image memory or by switching the counting operation, so that multiple types of images i! Even when processing i collections, complicated arithmetic processing is not required, and the processing can be performed at the same speed as a single editing process.

In the above-described embodiment, the clock generation circuit 400 uses the adder 451 to generate the clock signal TCK, but this is generated by dividing the standard clock signal SCK using several stages of frequency dividers. Standard clock signal SC
A clock signal TCK for scaling K may be generated.

That is, the scaled clock signal TCK obtained by thinning out the standard clock signal SCK in the present invention is not limited to a pulse signal with an irregular period, but also includes a signal obtained by frequency-dividing the standard clock signal SCK.

In the embodiment described above, write address counter 40
3 has a fixed initial count value and performs only up-count operation, and has been described as being capable of changing the initial count value and switching the count operation only for the read address counter 404, but conversely, when the write address counter 404 The counter 403 may change the initial count value and switch the counting operation, and edit processing may be performed at the stage of writing image data to the RAM 401 or 4.2. Even if the value is made changeable and the other counting operation is switched, it is possible to form an edited image similar to this embodiment.

[Effects of the Invention] According to the present invention, image processing for forming a moving image can be executed at high speed, so it is possible to form a moving image in real time.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention, and FIG. 1 is a block diagram of a scaling/editing processing circuit, FIG. 2 is a block diagram of a clock generation circuit, and FIG. 3 is a time chart of scaling processing in the case of reduction. Figure 4 is a time chart of scaling processing in the case of enlargement, Figure 5 is a block diagram of the electric circuit of the image processing device, Figure 6 is a diagram showing the address area of RAM, and Figure 7 is a diagram showing the image league unit. 8 is a plan view of the image sensor, and FIG. 9 is an enlarged view showing the CCD sensor chip of FIG. 8. 400... Clock generation circuit, 401... RAM (
1st image memo January, 402... (second image memory), 403... write address counter (write address generation means), 404... read address counter (read address generation means), B. ...Image processing device,
RCK: Read clock signal, WCK: Write clock signal. Applicant Minolta Camera Co., Ltd. Agent Patent Attorney Yukio Kubo To Laser Printer Department

Claims (1)

[Claims] (1) A clock generation circuit that simultaneously outputs a write clock signal and a read clock signal, and a clock generation circuit that alternately writes a predetermined amount of sequentially input image data for each line, and when one performs a write operation, the other outputs the written image. The first and second ones perform the data read operation.
a double-image memory; a write address generating means for specifying addresses for writing into the first and second image memories according to a write clock signal; and a write address generating means for specifying addresses for reading from the first and second image memories in accordance with a read clock signal. 1. An image processing apparatus comprising: a designated read address generating means, and configured such that an initial address value of at least one of the write address generating means and the read address generating means can be arbitrarily set.