JPH02170667A - Picture processor - Google Patents

Abstract

PURPOSE:To quickly execute a picture processing to form an oblique picture by providing a variable initializing means which increases or reduces the address initial value of at least one of a writing address generating means and a reading address generating means at every prescribed period. CONSTITUTION:The address initial value of a reading address counter 404 is set in accordance with a load signal LOAD applied from a repeating circuit 470 based on load data LOAD.DATA from an adding circuit 461 to which movement data MOV.DATA is given from a CPU. This address initial value is properly changed to form a moving picture where the forming position of the picture is shifted. The counted initial value of the reading address counter 404 is increased or reduced by load data LOAD.DATA and set to shift the read position of RAMs 701 and 402 right or left in the main scanning direction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device for forming an edited image in which an original image is wholly or partially transformed.

[Conventional technology]

In recent years, image forming devices equipped with image processing devices that perform digital signal processing on image signals, such as digital copiers, facsimile machines, and printers, have improved gradation and color reproducibility on the one hand, while on the other hand In recent years, image editing functions have been diversified.

The image editing function is a function to create an image by intentionally transforming the original image. Edited images created using this function include moving images that change the arrangement of images,
There are so-called mirror images (mirror images) in which the original image is symmetrically reversed, italic images suitable for stylizing characters and the like by tilting the original image, and repeated images formed by repeating a part of the original image.

Forming a moving image is performed, for example, when forming an image on paper that is larger than the original image, and when you want to match the center of the image with the center of the paper, and mirror images are used, for example, to create a block copy. can. Additionally, italic images are useful for lettering, and repeated images are useful when creating multiple labels.

When forming these edited images, generally, a predetermined amount of image data is temporarily stored in an image memory, and the data in the image memory is replaced based on arithmetic processing by an arithmetic unit such as a microprocessor.

[Problem to be solved by the invention]

However, if the image processing to form the edited image is performed using software using a microprocessor etc., the degree of freedom in editing can be increased, but in reality, a certain amount of processing time is required, which is limited by the calculation processing speed. Therefore, there was a problem in that real-time image formation could not be performed.

Also, in order to simplify the configuration, if you try to process multiple types of image kfA collections by sharing one image memory, the software will not work properly. JtGt, which caused the problem that the processing speed further decreased.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide an image processing device that can perform image processing for forming an italic image at high speed.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention provides a clock generation circuit that simultaneously outputs a write clock signal and a read clock signal, and a clock generation circuit that alternately writes a predetermined amount of sequentially input image data for each line. The other includes first and second image memories that read out written image data when performing an operation, and write address generation means that specifies addresses for writing to the first and second image memories in accordance with a write clock signal. , a read address generating means for specifying the read address of the first and second image memories in accordance with a read clock signal; and increasing or increasing an initial address value of at least one of the write address generating means and the read address generating means at predetermined intervals. and variable initial setting means for decreasing the number of initial settings.

[Effect]

The clock generation circuit simultaneously outputs a write clock signal and a read clock signal.

The first and second image memories alternately write a predetermined amount of sequentially input image data for each line, and when one performs a writing operation, the other reads the written image data.

The write address generation means updates (increments or decrements) the address according to the write clock signal.
, and specify the writing addresses of the first and second image memories.

The read address generation means updates the address in accordance with the read clock signal, and specifies the read address of the first and second image memories.

The variable initial setting means increases or decreases the initial address value of at least one of the write address generation means and the read address generation means at predetermined intervals.

This generates an oblique image data signal that tilts the original image.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 7 is a perspective view showing the image league unit 14 of the image processing device B incorporated in a digital copying machine, FIG. 8 is a plan view of the image sensor 11, and FIG. 9 is a CCD shown in FIG.
FIG. 3 is an enlarged view showing the sensor tube lla.

A digital copying machine consists of an image processing device B (see Figure 5), which performs various signal processing on pixel signals read by scanning an image of a document, and outputs them as image signals;
The printer includes a laser printer unit (not shown) that forms a color image using a well-known electrophotographic method based on image signals sent from the printer.

An image league unit 14 equipped with an image sensor 11 performs a line scan in the sub-scanning direction on a document placed on a document table glass I8.

As shown in FIG. 8, the image sensor 11 includes five contact type COD sensor chips lla, 11a...
are arranged in a staggered manner so as to be continuous in the horizontal direction (main scanning direction) and alternately at a constant pitch in the vertical direction (sub-scanning direction). Since there is a constant pitch in the sub-scanning direction, the rear CCD sensor chimble in the sub-scanning direction
There is a delay in the output signal from the front CC.
This is corrected by delaying the output signal from the D sensor chip lla.

Each CCD sensor chip lla has a size of 62.5 am as shown in FIG.
A large number of (d=1/16+m) square elements are arranged in one row.

Each element is divided into three parts, one divided area is R (red),
A filter is provided to receive light of one of the three primary colors of G (green) and B (blue).

FIG. 5 is a block diagram of the electric circuit of image processing device B. FIG.

The photoelectric conversion signals output in parallel from the COD sensor chip lla are sent to a digitization processing circuit 1 including an AD converter.
After being quantized by 01 and converted to 8-bit (256 levels) image data, the 5-channel synthesis circuit 10
2, it is converted into a serial signal corresponding to the pixel arrangement.

Next, a white balance correction circuit 103 performs white balance correction to compensate for the difference in spectral sensitivity of the CCD sensor chip for each RGB color, and a shading correction circuit 104 performs a white balance correction to compensate for the difference in spectral sensitivity of the CCD sensor chip for each RGB color. ) and each CCD sensor chip, and the data signal that was proportional to the intensity of reflected light is converted according to the reading range of the original and becomes proportional to the density of the original. is converted into a concentration data signal.

The color correction circuit 105 calculates the three primary colors Y and M of printing toner from the image data corresponding to the density of each RGB color as described above.
, masking processing to generate image data corresponding to C and UC to generate image data corresponding to Bk (black).
R processing and the like are performed, and a gamma correction circuit 106 performs gamma correction based on the background color and density gradient of the original.

The color editing circuit 107 performs three types of color image editing processing: negative/positive inversion, color change, and painting (!!smashing).

Image data signals D77 through these various signal processes
Reference numeral 70 denotes a scaling/editing processing circuit 10B, which performs scaling processing using a thinning method or interpolation method, and editing processing for forming an edited image such as moving, mirroring, italic, repeating, etc., and the output timing and output order of image data. Alternatively, processing is performed to change the scanning speed in the sub-scanning direction.

After that, the MTF correction circuit 109 performs smoothing to prevent the occurrence of moire fringes and edge enhancement to eliminate edge loss, and the gradation reproduction circuit 110 performs binarization processing using the area gradation method and sends it to the laser printer section. Sent. In the laser printer section, image formation is performed by controlling the beam deflection corresponding to the scanning of the document in the main scanning direction and the rotation of the photosensitive drum corresponding to the scanning in the sub-scanning direction.

Note that 111 is a line memory that stores image data at a specific processing stage, and 112 is a line memory that stores image data at a specific processing stage, and 112 is a line memory that stores image data at a specific processing stage. CP that controls the circuit
U (central processing unit) 113 is a ROM in which control programs and various data are stored.

FIG. 1 is a block diagram of the scaling/editing processing circuit 108.

The scaling/editing processing circuit 108 is the color editing circuit 1 at the previous stage.
The image data signals D77-70 (8-bit parallel signal) input from 07 are subjected to scaling processing and editing processing, and outputted as image data signals D87-8o (8-bit parallel signal) to the subsequent MTF correction circuit 109. Input and output are performed via latch circuits 412 and 413 that perform a latch operation in accordance with the image clock signal 5YNCK, which serves as a reference for the transmission timing of image data between the image processing circuits described above.

Such a scaling/editing processing circuit 10B simultaneously outputs the input clock signal WCK and the read clock signal RCK.
That is, a clock generating circuit 400 outputs data in parallel, and a set of clock generating circuits 400 writes a predetermined amount of sequentially inputted image data alternately every line period, and when one performs a writing operation, the other reads out the written image data. RAM401
．． 402, RAM4 according to write clock signal WCK
A write address counter 403 that specifies the address when writing 01.402, a read address counter 404 that specifies the address when reading from the RAM 401.402 according to the read clock signal RCK, a write address WA from the write address counter 403, and a read address counter Address selectors 405 and 406 for selecting read address RA from 404 and RAM 401
It has a line parity counter 407 for selecting a write operation or a read operation.

RAM 401 and 402 each have a capacity of 8 and can store image data for one line (8000 pixels) in the main scanning direction, but data writing and reading require a common human output board. Therefore, in order to avoid input/output data collision, buffers 408 and 410 consisting of D-flimp flops (D-FF) are connected to the RAM 401, and buffers 408 and 410 are connected to the RAM 402.
9.411 is provided. Therefore, the image memory configuration is a so-called double buffer configuration, and the buffers 40B and 410 or buffers 409 and 411 perform a latch operation in synchronization with access to the RAM 401 or RAM 402, respectively.

The write address counter 403 of this embodiment increments by "1" from a fixed count initial value (address initial value) for each line in accordance with the signal WCK, that is, performs an amplifier count operation.
04, its address generation operation can be controlled by various editing processing signals, as will be described later.

The line parity counter 407 outputs an odd-numbered value that alternates "L" and rH every time it counts the horizontal synchronizing signal TG that defines one line period, and performs a write operation or a read operation of the RAM 401, 402. Select an action.

Signals ODD-L I NE and EVEN-L I
Table 1 summarizes the switching operations of the RAMs 401 and 402, address selectors 405 and 406, and buffers 408 to 411 based on the NE.

(The following is a blank space) FIG. 2 is a block diagram of the clock generation circuit 400.

The clock generation circuit 400 uses the image clock signal 5YNCK, which serves as a reference for the transmission timing of image data between the image processing circuits described above, as a standard clock signal SCK, and uses the adder 451 to generate the yA quasi-clock signal SCK. The clock signal TC is obtained by thinning out the standard clock signal SCK.
The 6CPtJ112 that generates K sends scaling data (MAG-DAT) determined according to the scaling factor to the adder 451.
A) is given, the adder 451 adds the output data of the launch circuit 452 to MAG-DATA, and the arithmetic sum data is latched by the latch circuit 452. This addition operation is
This is repeated every pulse of the signal 5YNCK, and the carry signal CK-EN during addition is applied as the other input to the data 1-circuit 453, which receives the signal 5YNCK as one input.

Signal CK when the arithmetic sum data incremented by MAG-DATA does not exceed the maximum value of adder 451.
-4N becomes “L” and the output of the gate circuit 453 is also rL.
As a result, the pulses of the signal 5YNCK disappear every predetermined number of pulses, and the clock signal TCK obtained by thinning out the signal 5YNCK is generated. Naturally, when l is set as 1 as the magnification ratio, that is, when forming a same-sized image, the signal 5YNCK is not thinned out, and the clock signal T
The pulse timings of CK and standard clock signal SCK are equal.

The clock signal TCK generated in this manner is applied to the ζ selector 454 together with the signal 5YNCK as the standard clock signal SCK.

The selector 454 writes either the standard clock signal SCK or the clock signal TCK into the write clock signal WC.
K and read the other clock signal RC at the same time.
Select and output as K.

The selection operation of selector 454 is controlled by scaling control enable signal REDUCE.

That is, when forming a reduced image, the signal REDU
CE is "L", and at this time the selector 454 selects the clock signal TCK as the write clock signal WCK and at the same time selects the standard clock signal SCK as the read clock signal RCK.

When forming an enlarged image, the signal REDUCE is "H", and at this time the selector 454 selects the clock signal SCK as the write clock signal WCK and the clock signal TCK as the read clock signal RCK.

These signals WCK have different numbers of pulses per unit time,
Image data signals 087 to 80 subjected to scaling processing by accessing RAM 401 and 402 with signal RCK
is generated.

FIG. 3 is a time chart of the scaling process in the case of reduction, and FIG. 4 is a time chart in the case of enlargement.

In these figures, the write operation and read operation of image data corresponding to one line are shown aligned with the edge of one horizontal synchronization enable signal TG.
Actually, as shown in Table 1, write operations and read operations corresponding to one line are performed alternately every line period.

Referring also to FIG. 1, for example, when forming a reduced image with a magnification of 2/3, the clock generation circuit 400
Based on MAG-DA and TA obtained by the calculation by 112, the clock signal TCK obtained by thinning out one pulse every three pulses from the signal 5YNCK is output as the write clock signal WCK.

When the vertical synchronization enable signal VD for preventing the transmission of image data signals D77-70 outside the effective image forming range becomes inactive, the launch circuit 412 becomes active, and the image data signals D77-70 are inputted from the previous stage as image data signals 077-70. ii! ii Image data (■, ■, ■...) are latched according to signal 5YNCK.

When processing odd lines, as shown in Table 1, the signal 0DD
-LINE is [LJ, and the output of the latch circuit 412 is sent to the RAM 401 via the buffer 408.

At this time, the write address WA of the RAM 401 is incremented by one address from the start address A1 in accordance with the double clock signal TCK as the signal WCK in the write address counter 403, and one pixel worth of image is stored at one address by access synchronized with address specification. As the data is written, the RAM 401 contains three pixels worth of image data. A reduced image data group (■, ■, ■...) in which the ii elements have been thinned out will be stored.

At the time of reading, the RAM 401 is accessed according to the clock signal SCK having the same pulse period as the signal 5YNCK, and the RAM 401 is accessed via the buffer 410 to the launch circuit 41.
The image data signals DB 7 to DB 80 are sent out after being subjected to reduction processing.

Furthermore, when forming an enlarged image, for example, if the magnification ratio is set to 3/2, the clock generation circuit 400 generates the clock signal TCK by thinning out one pulse every three pulses from the signal 5YNCK as described above. , and outputs this as a read clock signal RCK.

Since the write clock signal WCK is equivalent to the signal 5YNCK, one line of image data (■, ■,
) are written to the RAM 401 in the order of input without being omitted. However, RAM4 in read operation
Since the access to 01 follows the clock signal TCK, the specified period of the even-numbered address corresponds to two periods of the signal 5YNCK, and the latch circuit 413 outputs the even-numbered image data (■, ■, ...). A series of enlarged image data signals 087 to 80 are output.

As described above, if image formation is performed based on the image data signals D87 to D80 generated by differentiating the access timings during write and read operations of the RAMs 401 and 402 of the IMi, changes in the main scanning direction can be realized. A multiplied image can be formed.

Note that the scaling of the image in the sub-scanning direction is performed by changing the scanning speed of the image league unit 14 in the sub-scanning direction. In other words, the scanning speed at the same magnification is V
(mm7 seconds) and the magnification ratio in the sub-scanning direction is a.
The scanning speed during zooming is set to V/a (mm 7 seconds).

Returning to FIG. 1, the initial address value in the read address counter 404 is determined by the movement data MO from the CPU 112.
Based on the load data LOAD-DATA from the adder circuit 461 to which V DATA is given, the iterative circuit 47
It is set according to the load signal LOAD applied from 0.

By appropriately changing this initial address value, it becomes possible to form a moving image in which the image formation position is shifted.

That is, as mentioned above, the capacity of RAM401.402 is 8 bytes (8192 x 8 bits), and rOHJ~rl
It is possible to assign an address (13 pintos) of FFFH. On the other hand, the read address counter 404 is 1
It is a 5-bit counter and can generate addresses from "OH" to r7FFFHJ. Therefore, as shown in FIG. 6, the address area of RAM401.402 is
0)(''~r5FFFH, and the initial count value of the read address counter 404 is assigned to the load data 9LOA.
By increasing or decreasing the value around "4oooH" using D-DATA, the reading position from the RAM 401, 402 can be shifted to the left or right in the king scanning direction. The area where image data is actually written is determined depending on the pixel density and document size. For example, when an A3 size document is read at 16 pixels/flIIl, the amount of data for one line is approximately 5 bytes. In this embodiment, a data clear enable signal DATA-CLR is input from the read address counter 404 to the clear terminal of the launch circuit 413 so that the data written in this range is output.

Further, the initial count value of the write address counter 403 is "0", and at the time of writing, image data is written to the RAM 2 O 3 or the RAM 402 in order from address (physical address) 0.

Therefore, for example, if the load data LOAD-DATA is
4000H, address (logical address) r40
Reading is performed from 00HJ, that is, physical address "0", and an image is formed at the same position as the original image. Also, for example, the load data LOAD-DATA is r3000H.

Then, the read address counter 404 is repeatedly incremented, and image data is read out from when it reaches r4000HJ, which is allocated to the RAMs 401 and 402. As a result, a moving image shifted to the right is formed.

These shift) 13 and shift direction are the movement data MOV
- Can be set appropriately by changing DATA. For example, when forming a reduced image in the center of copy paper, the CPU 112 performs calculations to find the optimum value of the movement data MO2.DATA based on the magnification ratio and the detection signal of the copy paper size.

Furthermore, in the sub-scanning direction, movement can be performed in steps of 1/16 aa by advancing or delaying the timing of activating the vertical synchronization enable signal VD described above in units of line periods.

The repetition circuit 470 is for forming a repetition image, and includes a comparator 471 that compares the output of the read address counter 404 and repetition data REP-DATA;
Output of comparator 471 and repetition control enable signal R
It consists of a gate circuit 472 to which EP-ON is input, and a gate circuit 473 to which the output of the gate circuit 472 and the horizontal synchronization enable signal TG are input.

When the signal REP・ON is inactive (active low), that is, when a repetitive image is not formed, the output of the gate circuit 472 is always inactive, and the signal LOAD, which is the output of the gate circuit 473, is the signal TG. follow. Therefore, in this case, like the write address counter 403, the initial count value is set for each line.

When the signal REP・ON is active, when the count value reaches the repetition data REP-DATA, the output of the comparator 471 becomes "L" (active). Accordingly, the signal LOAD becomes active, and the read address counter 404 Load data to LOAD -DAT
Initial settings to load A are performed, and RAM 401 or R
Even in the middle of reading one line of AM 402, the read address counter 404 increments again from the initial count value. As a result, RAM401.4
The 6-repetition image in which the image data stored in the specific address area of 02 is repeatedly read out and a repeated image data signal is generated is convenient, for example, when creating a large number of labels.

The variable initial setting circuit 460 is for forming an italic image, and includes the above-mentioned adder 461 and line counter 46.
It is composed of 2. When forming an italic image,
The variable initial setting circuit 460 changes the count initial value of the read address counter 404 at predetermined intervals.

The line counter 462 has an italic enable signal ANC;
When LE-OFF is "L", the count is increased by the signal TG, and the adder 461 outputs load data LOAD-DATA, which is the sum of the output DOUT of the line counter 462 and the movement data MOV.DATA. Therefore, the initial count value of the read address counter 404 increases every l line.

As a result, the formed image becomes an italic image shifted to the left by one pixel for each line.

Note that if the signal TG is thinned out and applied to the line counter 462, it is possible to shift by one pixel every multiple lines, and the tilt angle can also be controlled by changing the current step of the line counter 462. can. Also, if the line counter 462 is made to perform a down-count operation or the adder 461 is changed to a subtracter,
The direction of the tilt can be reversed.

Further, the read address counter 404 can be switched between an up-count operation and a down-count operation by a mirror enable signal MIRROR.

When signal MIRROR is inactive, read address counter 404 receives load data LOA as described above.
An amplifier counting operation is performed according to the signal RCK from the count initial value set based on D-DATA, but when the signal MI RROR is active, the operation is switched to a down-counting operation.

When the read address counter 404 is switched to down-count operation, the image data written in the RAM 401 or the RAM 402 will be read out in order from the one that was written last.

For example, if r 5000 H is set as the initial count value by load data LOAD-DATA,
Read address counter 404 is logical address r500
Decrement from 0H, RAM401.40
In step 2, image data stored within the address range M from the physical address corresponding to the logical address "5000H" to the physical address "0" is read out.

The image data signal D8''l~ generated by the down-counting operation of the read address counter 404 in this way
The image formed based on 80 is a so-called mirror image obtained by symmetrically inverting the original image. This mirror image is used, for example, to create a block copy.

The image processing described above, that is, the scaling processing and the processing for forming each W collection image, can be performed individually or in combination as appropriate.

For example, it is possible to repeatedly form reduced and horizontally reversed images in the main scanning direction of a sheet of copy paper.

According to the above-described embodiment, the edited image data signal is generated by changing the initial count value of the address counter that specifies the address of the image memory or by switching the counting operation. Even though
'ai No complicated arithmetic processing is required, and the processing can be performed at the same speed as a single editing process.

In the embodiment described above, the clock generation circuit 400 uses the adder 451 to generate the clock signal TCK, but it is also possible to divide the frequency of the standard clock signal SCK using a several-stage frequency divider. Standard clock signal S
CK may be used to generate a clock signal TCK for scaling.

That is, the scaled clock signal TCK obtained by thinning out the standard clock signal SCK in the present invention is not limited to a pulse signal with an irregular period, but also includes a signal obtained by frequency-dividing the standard clock signal SCK.

In the embodiment described above, write address counter 40
3 has a fixed initial count value and performs only up-count operation, and has been described as being capable of changing the initial count value and switching the count operation only for the read address counter 404, but conversely, when the write address counter 404 In the counter 403, the initial value of the count is changed and the operation is changed to run 1, and the RAM 401 or 4
Editing processing may be performed at the stage of writing image data to 02. Furthermore, it is possible to form an edited image similar to this embodiment by making it possible to change the initial count value of one of the address generating means and switching the counting operation of the other.

(Effects of the Invention) According to the present invention, image processing for forming an italic image can be executed at high speed, so it is possible to form an italic image in real time.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention, and FIG. 1 is a block diagram of a scaling/editing processing circuit, FIG. 2 is a block diagram of a clock generation circuit, and FIG. 3 is a time chart of scaling processing in the case of reduction. Figure 4 is a time chart of scaling processing in the case of enlargement, and Figure 5
The figure is a block diagram of the electric circuit of the image processing device, and Figure 6 is R
7 is a perspective view showing the image reader unit, FIG. 8 is a plan view of the image sensor, and FIG. 9 is an enlarged view showing the CCD sensor chip of FIG. 8. 400... Clock generation circuit, 401... RAM (
(first image memory), 402... (second image memory), 403... write address counter (write address generation means), 404... read address counter (read address generation means), 460... - Variable initial setting means (variable initial setting means), B... image processing device,
SCK: standard clock signal, TCK: clock signal obtained by thinning out the I-compliant lock signal, RCK: read clock signal, WCK: write clock signal. Applicant Minolta Camera Co., Ltd. Agent Patent Attorney Yukio Kubo To Laser Printer Department

Claims (1)

[Claims] (1) A clock generation circuit that simultaneously outputs a write clock signal and a read clock signal, and a clock generation circuit that alternately writes a predetermined amount of sequentially input image data for each line, and when one performs a write operation, the other outputs the written image. The first and second ones perform the data read operation.
an image memory; write address generation means for specifying addresses for writing into the first and second image memories according to a write clock signal; and specifying addresses for reading from the first and second image memories in accordance with a read clock signal. What is claimed is: 1. An image processing apparatus comprising: a read address generating means for generating a read address; and a variable initial setting means for increasing or decreasing an initial address value of at least one of the write address generating means and the read address generating means at predetermined intervals.