JPH02170538A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an element having a higher efficiency and a higher yield in a simple process by a method wherein a polycrystalline silicon film or an amorphous silicon film is deposited and after an impurity is introduced in the film, the film is heat-treated in an oxidizing atmosphere of 950 deg.C or lower. CONSTITUTION:A single crystal silicon film 3 containing arsenic doped to it is deposited on a boron layer 2 obtained by introducing boron in a (100) single crystal silicon substrate 1 in a thickness of 2500Angstrom or thicker and an opening 4 is formed in part of the silicon film 3. Moreover, this silicon film is annealed in a wet and O2-containing atmosphere at 950 deg.C or lower. Accordingly, if the polycrystalline silicon deposition part 3 is assumed to be an emitter and an intrinsic base and the opening 4 is assumed to be an external base, the external base only results in being diffused deeply. Moreover, if boron ions are implanted, a peripheral tunneling between the external base and the emitter is suppressed. Thereby, a process is simple, the formation of an element is facilitated and the efficiency and yield of the element are also improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a bipolar semiconductor device, and particularly to a method for manufacturing a semiconductor device in which an emitter and a base are formed in a self-aligned manner.

(Prior Art) In order to achieve high speed in bipolar devices, it is important to reduce the parasitic capacitance and resistance component of the junction. In particular, collector-base junction capacitance and base resistance are major factors that affect the operating speed of devices, and many attempts have been made to reduce these.

To achieve high speed bipolar devices, it is necessary to miniaturize the emitter, reduce the distance between the emitter and the external base, and reduce the parasitic capacitance of the device.

Base resistance needs to be reduced. For this purpose, fine pattern formation technology and lithography technology capable of highly accurate positioning are required, but this is difficult with the current lithography technology. For this reason, a method has been proposed in which the position of each region is self-aligned (self-alignment) without relying on lithography technology. However, all of these methods have the problem that the process is extremely complicated.

Here, we will introduce two examples of current self-alignment processes.

The first example is the 1988 Institute of Electronics, Information and Communication Engineers study group notes ED.
-88-54p, 35. Fourth
This will be explained using figures.

FIG. 4 shows the conventional self-alignment process in order, and FIG. 4(A) shows that a buried collector 21 and a channel stopper 22 are formed on a P-type CZ (111) substrate 20,
For example, 0.85. A thick epitaxial layer 22 is grown at low temperature and low pressure to perform element isolation, which is characterized by no bird's beak and extremely small dimensional conversion difference, and then a first poly-SL film 23, a bad SiO□ film 24, Layer Si, N, film 25, SL, N, film 2
5 is patterned by photolithography to fix the base electrode, collector electrode, and resistor regions. Here, the opening width of the Si, N, and film on the region that becomes the emitter is, for example, 1-.

In FIG. 4 CB), the first poly-3i is selectively oxidized by high-pressure oxidation to form a base electrode, a collector electrode, and a poly-Si pattern serving as a resistor.

Next, by implanting boron ions over the entire surface using the selective oxide film 26 as a mask, each poly of the base electrode and resistor is
- Introducing boron into the Si pattern in a self-aligned manner.

The selective oxide film 26 on the emitter is removed as shown in FIG.
The silicon surface of W8jl is thinly oxidized while leaving it on. Thereafter, by implanting boron ions into the entire surface and performing heat treatment, seven anneals of the intrinsic base and diffusion formation of the extrinsic base are simultaneously performed.

Next, using low pressure CVD, the Sin film 27 and poly-5illi2g, which will become sidewall spacers, are laminated as shown in FIG. 4(D).

Then, as shown in FIG. 4(E), the poly-5illi2g, Sun, and film 27 are etched and packed to open the emitter 29 by anisotropic etching. The emitter opening width at this time is determined by the total film thickness of Si3N, Sin covering the bottom of the film 25, IPJ27, and poly-3i[28. In this process, SL,
By setting the total film thickness of the sidewall spacer 31 to 0.3 .mu.s for the aperture width of N, for example 1p, a finished emitter aperture width of up to 0.5-.mu.s is achieved.

Furthermore, as shown in FIG. 4(F), the second poly
-5i film 30 is generated by low pressure CVD, arsenic is ion-implanted, and an emitter is diffused and formed by heat treatment.
An emitter electrode pattern is formed by photolithography.

Finally, a contact hole is formed and the exposed poly
After forming a Pt-Si barrier on the -5i surface, Af
Form i-wiring.

By the way, when miniaturizing bipolar devices to increase their speed, the positional relationship between the emitter and the base becomes extremely important. For example, if the distance between the emitter contact and the base contact is reduced too much, the emitter and the external base will come into contact with each other, which will increase the junction leakage current due to the high impurity concentration at the emitter-base junction.Furthermore, the collector current will increase. depends on the emitter area, so in order to manufacture devices with little variation, the key is how to suppress the variation in the emitter area.

Let's review the above-mentioned process example from this perspective. Fourth
As can be seen from Figure (E), the emitter-base spacing or emitter area is determined by the sidewall spacer process by anisotropic etching of polysilicon. Furthermore, the width of this sidewall spacer is shown in Figure 4 (D
It is determined by the polysilicon film thickness in the process of ), and the thickness of the Si3 film formed in the LD/CO8 process of FIGS. 4(B) and (C)
It can be seen that it depends on the shape of the N4 membrane. Due to the problem of controllability of each film formation, it is difficult to suppress variations in such a process. Also, since it is a complex process, I was hoping for a high yield.

Next, a second example (mentioned study group note p, 41) will be shown.

A conventional process flow is shown in FIGS. 5(a) to 5(a).

Figure 5(a) shows that after element isolation is formed, a nitrogen film and P+ polysilicon are grown, and the polysilicon is etched away, leaving a portion that will become the base electrode, and then zero-order polysilicon is grown to form four parts of polysilicon. After that, grow a nitrided pancreas. Furthermore, a CVD oxide film is grown, and an oxide sidewall is formed on the inner wall of the recess by anisotropic etching.

In FIG. 5(b), the nitride film is etched using the oxide film sidewall as a mask, leaving the nitride film only on the inner wall of the recess.
Further, after removing this oxide film sidewall, the polysilicon is selectively oxidized using the nitride film on the inner wall portion as a mask.

In FIG. 5(c), after removing the nitride film in the recess, the polysilicon and nitride film are etched using the oxide film as a mask to open a base contact. The part of the central nitride film that is damaged becomes the emitter region.

In FIG. 5(d), a polysilicon sidewall is formed and a base contact is established. P using the central nitride film as a mask
+Oxidize the surface of polysilicon to form an oxide film between base-emitter polysilicon electrodes.

During oxidation, boron is diffused from the polysilicon through the base opening into the silicon substrate to form an extrinsic base layer.

In FIG. 5(e), after removing the central nitride film and forming an emitter contact opening, polysilicon that will become the emitter electrode is grown, and boron and arsenic ions are implanted. Boron and arsenic are diffused into the silicon substrate through the emitter opening to form an active base layer and an emitter layer.6 The emitter region, external base region, emitter contact section, and base contact section are all formed in a self-aligned manner;
For example, in 1.5-photolithography, 0.6μ
An emitter having a width of s is formed.

In this example, although the problems in the first example have been resolved, the problem that the process is extremely complicated remains.

(Problems to be Solved by the Invention) Conventional semiconductor device manufacturing methods require complicated steps to form an emitter and a base in a self-aligned manner.

The present invention was developed in view of this problem, and it is possible to form an emitter and a base simultaneously in a self-aligned manner through an extremely simple process, and also to realize peripheral tunneling, which is one of the bottlenecks in creating high-speed bipolar devices.
An object of the present invention is to provide a method for manufacturing a semiconductor device that can form a structure that is resistant to (peripheral tunnel effect).

[Structure of the invention]

(Means for solving problems) The main points of the manufacturing method proposed by the present invention are as follows.

A step of introducing impurities such as boron or arsenic into a single crystal silicon substrate, a step of depositing a polycrystalline silicon film or an amorphous silicon film of 2500 Å or more on the impurity introduced layer after cleaning the substrate surface, and a step of introducing impurities into a silicon film or an amorphous silicon film, and providing a substrate opening in a part of the deposited film;
Heat treatment is performed in an oxidizing atmosphere at 50°C or lower.

(Function) The manufacturing process proposed by the present invention attempts to form an emitter and a base simultaneously in a self-aligned manner by skillfully applying the characteristics of polycrystalline silicon or amorphous silicon. FIG. 1 shows a detailed explanatory diagram of the present invention based on experiments.

FIG. 1(a) shows a (100) single crystal silicon substrate 1,
Single crystal silicon 3 doped with arsenic is placed on the boron layer 2 into which boron is introduced so that Xi is 3100.
A portion of it with an opening 4 has been opened to accommodate approximately 0 people. This is annealed at 900° C. in a Wet O□ atmosphere as shown in FIG. 1(b). While the boron expansion RAM under the polycrystalline silicon has hardly increased, Xj of the opening 4 has decreased to about 6000 due to the OED effect. That is, if the polycrystalline silicon deposited portion 3 is used as an emitter and an intrinsic base, and the opening 4 is used as an extrinsic base, only the extrinsic base will be deeply diffused. Furthermore, as shown in FIG. 1(c), it can be seen from the figure that when boron ions are implanted, veriheral tunneling between the external base and the emitter can be suppressed. Note that the first layer 32 is a single crystallized portion.

When annealing in an oxidizing atmosphere, as shown in Figure 1(b), only the polycrystalline silicon openings are deeply diffused, and the polycrystalline silicon parts are hardly diffused, but this is due to silicon interstitial atoms and polycrystalline silicon generated during oxidation. This is because the silicon grain boundaries cause some kind of interaction, and the oxidation-enhanced diffusion effect (polycrystalline silicon openings) that is normally seen when annealing in an oxidizing atmosphere does not appear in polycrystalline silicon parts. It is believed that there is. It should be noted that impurities in the polycrystalline silicon portion are expected to be considerably redistributed due to normal thermal diffusion at a high temperature of 950° C. or higher, which is not preferable.

Furthermore, polycrystalline silicon has a fast oxidation rate, so
During annealing in an oxidizing atmosphere, a thick oxide film is also formed on the polycrystalline silicon sidewalls. If this oxide film is left and boron is ion-implanted again, an external base will be formed in a self-aligned manner. Furthermore, as is clear from the figure, there is no direct contact between the high concentration emitter and the high concentration external base.
Excellent resistance to peripheral tunneling.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

As shown in Figure 2(a), a P-type wheel crystal silicon substrate IO
An n+ buried layer 11 was formed therein using antimony, for example. This will later become the collector. Also, for example, LOCO
Element separation was performed using the 8 method. 161 is a thermal oxide film formed thereby.

Boron 12 is ion-implanted onto this as shown in FIG.
Polycrystalline silicon film containing 30 x 10”/cxl
Approximately 00 people will accumulate. Further, this polycrystalline silicon was patterned as shown in FIG. 2(c) to form a polyemitter 14. In addition, when the grain size of the polycrystalline silicon at this time was examined using an electron microscope w4D, it was found to be 200 to 800. Next, when annealing was performed at 950° C. in a Wet 02 atmosphere, oxidation and diffusion occurred as shown in FIG. 2(d).

In this way, by annealing in l/at O2 atmosphere, the external base 15 is formed and the spacer oxide film 16 is formed.
□ could be formed at the same time. At this time, the junction depth xj of the intrinsic base region 17 remained almost unchanged, but in the external base region, xj increased by about 3000A. The thickness of the oxide film on the polycrystalline silicon and on the side walls was about 450, but on the silicon substrate (opening) it was about 300. After this, in order to remove the ohmic of the external base, boron 18 is applied to the accelerating voltage 20 as shown in Fig. 2(e).
I x 10''/d ions were implanted at keV.
At this time, since a 450-layer oxide film is formed on the polycrystalline silicon 14, the upper part of the emitter is implanted using a 6th order planarization process and an etch-back method in which almost no boron is implanted into the emitter part and its surroundings. The part of the silicon oxide film that contains some boron was cut. (Figure 2 (
f)) Finally, CVD oxide film is deposited to form contact hole 19.
Holes were drilled and wiring was done. (Fig. 2 (g)) When the characteristics of the element thus produced were evaluated, the emitter-base wear resistance was L4V. For comparison, the emitter-base breakdown voltage of a device fabricated using the conventional process with the same processing dimensions was 1°V. Further, when the current gain bandwidth product fT of the device according to the process of the present invention was investigated, it was found to be 33 GHz.

This was better than the conventional 28 GHz. Furthermore, when we examined the relationship between the base-emitter forward voltage (VBll) and the base current (In), we found that, as shown in Figure 3, in the conventional device, the IQ increases especially in the low injection region, which is due to peripheral tunneling. was shown to be effective, but no increase in 1. was observed in the element fabricated by this process.

It has been found that the process of the present invention takes about half the number of days required to fabricate the device compared to the conventional process, and the process is simple and easy to fabricate, as well as good performance and yield.

The present invention is not limited to the embodiments described above, and the element isolation method and impurity dilute oxidation method may be changed, and amorphous silicon may be used instead of polycrystalline silicon.

〔Effect of the invention〕

As described above, in the present invention, when manufacturing a high-speed bipolar device, a device with higher performance and higher yield can be realized through a simple process.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of the process explaining the present invention in detail, Fig. 2 is a cross-sectional view of the process explaining the present invention in detail, and Fig. 3 is a characteristic diagram comparing the method of the present invention and the conventional method. , FIG. 4, and FIG. 5 are process cross-sectional views showing conventional examples. 1... Single crystal silicon substrate 2... Boron layer 3.
...Arsenic-doped polycrystalline silicon layer 4...opening

Claims (1)

[Claims] A step of introducing donor or acceptor impurities into a silicon semiconductor single crystal substrate and cleaning the semiconductor surface, and then depositing a polycrystalline silicon film or an amorphous silicon film with a thickness of 2500 Å or more; A step of introducing impurities into the amorphous silicon film,
A method for manufacturing a semiconductor device, comprising the step of providing a substrate opening in a part of the deposited film, and further heat-treating the substrate formed by the above step in an oxidizing atmosphere at a temperature of 950° C. or less.