JPH02170423A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To avoid an increase in a contact resistance due to an Si deposit on the interface between an Al film and an Si film by a method wherein a high-melting point metal or high-melting point metal silicide film is formed on the surface of a conductive region, where conductive support pillars are provided, in an Si semiconductor element. CONSTITUTION:An interelement isolation insulating film 22 consisting of an Si oxide is formed on a P-type Si substrate 21, a gate insulating film 23 is formed on the surface of an element formation region, and a gate electrode 24 is formed on a desired region. The, after N-type high-concentration impurity diffused layers 26, which are used as source and drain regions, are formed, Al is deposited on a titanium silicide film 27 and other Al is etched away in such a way that Al support pillars are left on the source and drain regions and the gate electrode. Then, an organic resin film 29 is applied as a temporary interlayer film, and after a heat treatment is performed, the film 29 is etched using oxidation plasma until all the Al support pillars 28 are exposed and an Al film 30 which is used as a wiring is deposited. Lastly, when the temporary interlayer film 29 is selectively removed by plasma etching using oxygen gas, a gap is generated between elements and between wirings.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a silicon semiconductor device, and particularly to an electrode wiring between silicon semiconductor elements and a manufacturing method thereof. [Background Art] In recent years, there has been a remarkable increase in the integration and speed of semiconductor devices, and this is due to the miniaturization of elements due to advances in processing technology. However, when an element is IR-reduced using a proportional shrinking agent, the high-speed performance of the element itself is improved, but the resistance and capacitance of the wiring connecting each element increases, and the wiring is a factor that determines the speed of semiconductor devices. The proportion of delay time has also increased. Particularly, when the wiring spacing (pitch) becomes narrower, the wiring capacitance increases significantly, which becomes a problem. The wiring capacitance is determined by the cross-sectional area of the wiring, the horizontal wiring spacing, the wiring-to-substrate spacing, and the dielectric constant of the insulating film filling between the wirings. Conventionally, silicon oxide films or phosphorus-doped silicon oxide liquid (PSG) deposited by CVD have been used as these insulating films.
etc., and its dielectric constant was around 4. To reduce the wiring capacitance, it is necessary to use an insulating filler with a lower dielectric constant, but in principle there is no such thing! r
! k (vacuum) has the smallest dielectric constant, and almost the same effect is expected even if a gas such as air is used. For this purpose, conductive pillars are formed on the area to be connected to the upper wiring in the semiconductor element formed on the substrate,
A method of connecting conductive columns by wiring without contacting other solid substances was proposed by Nakahiro Endo et al.
-No. 066497

[Problem to be solved by the invention]

In the above structure, when a conductive pillar mainly composed of aluminum is formed on the region to be connected to the upper wiring in the silicon semiconductor element, aluminum called an alloy spike grows into needles in the silicon substrate during subsequent heat treatment. This phenomenon causes a phenomenon called nodule, where silicon is deposited at the aluminum-silicon interface, making it difficult to connect the conductive region within the silicon semiconductor element and the conductive pillars mainly composed of aluminum. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that solve the above-mentioned problems. [Means for Solving the Problems] In order to achieve the above object, the semiconductor device of the present invention includes a silicon semiconductor element on a silicon substrate and at least a part of the wiring connecting each of the silicon semiconductor elements to another solid substance. In a silicon semiconductor device in which conductive pillars mainly made of aluminum are connected to each other without contact between conductive pillars provided on conductive regions in the silicon semiconductor element, the conductive pillars in the silicon semiconductor element should be provided with the conductive pillars. It has a high melting point metal or a high melting point metal silicide film on the surface of the region. The semiconductor device of the present invention includes a step of forming a silicon semiconductor element on a silicon substrate, then covering the surface of a conductive region within the silicon semiconductor element with a high melting point metal or a high melting point metal silicide, and forming an upper wiring within the silicon semiconductor element. A step of forming conductive pillars mainly composed of aluminum on the area to be connected, a step of exposing the conductive pillars mainly composed of aluminum after filling with a polymeric organic film, and a step of patterning the upper wiring. It is obtained by a method for manufacturing a semiconductor device including a step of forming the film and a step of removing the filled organic polymer film. [Function] By covering the surface of the conductive region of the silicon semiconductor element with a high-melting point metal or a high-melting point metal silicide, the conductive region within the silicon semiconductor element and the conductive pillars mainly composed of aluminum are prevented from coming into contact with each other. It has the advantage of improving condyle as there are no spikes or nodules. [Actual Cone Example] Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor device of the present invention. In the figure, an n-channel MOS consists of an element isolation insulating film 4 for isolating silicon semiconductor elements and a high concentration impurity diffusion layer 5 on a P-type silicon substrate 1.
A transistor is provided, high melting point metal silicide v6 is formed on the surface of the high concentration impurity diffusion layer, and upper wiring (second wiring) 8 is formed.
A conductive column 7 mainly made of aluminum is formed to connect with the conductive column 7. Reference numeral 9 denotes a gap formed between the semiconductor element and the upper wiring 8 and made of gas. FIGS. 3(a) and 3(b) are schematic diagrams showing the method for manufacturing a semiconductor device of the present invention in the order of steps. Figure 3 (a
), an inter-element isolation insulating film 22 made of a silicon oxide film is formed on a ρ-type silicon substrate 21, and then a gate insulating film 23 is formed on the surface of the element formation region, and then a first wiring is formed in a desired region. A gate electrode 24 is formed. Next, a silicon oxide film is deposited by CVD method, and CF4R
After performing IE and forming side spacers 25 on the side walls of the gate electrode, arsenic is diffused into the p-type silicon substrate 21 by ion implantation to form an n-type high concentration impurity diffusion layer that will become the source/drain region of the n-channel MO3 field effect transistor. Next, titanium, which is a high melting point metal, is deposited by sputtering, and titanium silicide M27 is formed on the surface of the n-type high concentration impurity diffusion layer using a silicide reaction. Subsequently, aluminum is deposited to a thickness of about 1.5 .mu.m, and other aluminum is etched away so as to leave aluminum pillars 27 in regions to be connected to the upper wiring, such as the source/drain region and the gate electrode. Next, Figure 3(b)
, an organic resin G29 such as a positive resist is spin-coated as an interlayer film, melted by heat treatment and flattened, and then an organic resin film is applied using oxygen plasma until the surfaces of all aluminum pillars 28 are exposed. 29 is etched, and aluminum 30 is deposited as an upper wiring. The illustrated structure is obtained by patterning the upper wiring using conventional photolithography and etching techniques. Finally, plasma etching using oxygen gas is performed to improve the Rv of the interlayer film. 4. When the fat film 29 is selectively removed, a gap is created between the element surface and the upper wiring, and the structure shown in FIG. 1 is obtained. In the above embodiments, a titanium silicide film was used on the conductive region within the silicon semiconductor element, but other metal materials may also be used, including tungsten, molybdenum, tantalum,
Materials such as titanium, alloy materials, or their silicides are promising. [Effects of the Invention] As described above, according to the present invention, p due to alloy spikes caused by diffusion of silicon into aluminum
This has the effect of improving reliability by avoiding the problems of n-junction breakdown and increased contact resistance due to nodules, which are silicon precipitation at the aluminum-silicon interface that occur when aluminum-silicon is used as a conductive support. .

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view showing the structure of the semiconductor device of the present invention, FIG. 2 is a schematic cross-sectional view showing a conventional example, and FIG. 3 fa)
, (b) are schematic diagrams illustrating the method for manufacturing a semiconductor device according to the present invention in order of steps. 1.21... P-type silicon substrate 2.22... Element isolation insulating film 3.23... Gate insulating film 4.24... Gate electrode (first wiring) 25... Side spacer 5. 26...N-type high concentration impurity diffusion layer 6.27...
High melting point metal silicide film 29...Organic resin film 8.30...Upper wiring (second wiring) Patent applicant NEC Corporation Representative Patent attorney Hara Uchi
Shinkaku 1? -p-type silicon substrate 3--gate leg 5--n-type high-concentration impurity FE diffusion layer 7--conductive branch 9--grooving gap Figure 2-Plan-f separation insulating layer 4-1-Gate electrical supply (1st wiring) 6--High 1st charge 3 Sillpoid membrane 8---Upper holder (2nd stroke 6 lines) Crane 3 figure (b)

Claims (2)

[Claims] (1) At least a part of the wiring connecting the silicon semiconductor element on the silicon substrate and each of the silicon semiconductor elements is mainly made of aluminum provided on the conductive region within the silicon semiconductor element without contacting other solid substances. A silicon semiconductor device that is connected between conductive pillars as components, characterized in that a high melting point metal or a high melting point metal silicide film is provided on the surface of the conductive region within the silicon semiconductor element where the conductive pillars are to be provided. Semiconductor equipment. (2) After forming a silicon semiconductor element on a silicon substrate, a step of covering the surface of a conductive region within the silicon semiconductor element with a high melting point metal or a high melting point metal silicide, and connecting with an upper wiring within the silicon semiconductor element. A step of forming conductive pillars mainly composed of aluminum on the region, a step of exposing the conductive pillars mainly composed of aluminum after filling with a polymeric organic film, and a step of patterning the upper wiring. and a step of removing the filled organic polymer film.