JPH01238146A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To float wirings flatly with a low stress by isolating them from the face of a semiconductor element in the air, to reduce its parasitic wiring capacity and to improve the operating speed of a semiconductor device by providing a conductive post brought into ohmic contact with the conductive region of the element. CONSTITUTION:After an interelement isolating insulating film 12 is formed on a P-type silicon substrate 11 and a gate insulating film 13 is then formed on the surface of an element forming region, a gate electrode 14 is formed. Then, arsenic is diffused in the substrate, an N-type high concentration impuritydiffused layer 15 is formed, aluminum is then deposited, and other aluminum is so removed by etching as to allow an aluminium post 16 to remain on a region to be connected to the upper interconnection. Then, it is spin coated with an organic resin film 17, flattened by heat treating, etched until the surface is exposed, and aluminum 18 is then deposited. Subsequently, when the film 17 of the temporarily interlayer film is removed by plasma etching, a gap is generated between the face of the element and the upper interconnection. Since this gap is filled with air and has small specific permittivity, its wiring capacity is reduced to approx. 1/4 of the conventional one.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to an electrode wiring between semiconductor elements and a manufacturing method thereof.

(Prior Art) In recent years, there have been significant improvements in the integration and speed of semiconductor devices, and this is due to the miniaturization of elements achieved through advances in processing technology. However, when elements are miniaturized by proportional reduction, the speed of the elements themselves improves, but the resistance and capacitance of the wiring between each element increases, and the delay caused by wiring is a factor that determines the speed of semiconductor devices. The proportion of my time has also increased. Particularly, when the wiring spacing (pitch) becomes narrower, the wiring capacitance increases significantly, which becomes a problem. What determines the wiring capacitance is the cross-sectional area of the wiring, the vertical and horizontal wiring spacing, the wiring-to-substrate spacing, and the dielectric constant of the insulating film filling between the wirings.

Conventionally, silicon oxide films and phosphorus-doped silicon oxide films (PSG) deposited by CVD have been used as these insulating films.
etc., and the dielectric constant was about 4.

To reduce the wiring capacitance, it is necessary to use an insulating filler with a lower dielectric constant, but in principle the dielectric constant is the lowest when there is nothing (vacuum). Almost the same effect is expected.

An example of forming a part of the wiring in the form of a suspension bridge connecting between pillars for this purpose is the work of G.D. McCormack (G.
D., McCormack) et al., 1982, Technical Proceedings of the Gallium Arsenide IC Symposium, 25-
It is reported on page 28. In this paper, as shown in FIG. 2, a contact hole is formed in an insulating film in an n+ region 33 on a gallium arsenide substrate 31, and then a wiring 37 is formed by plating titanium and gold.

(Problems to be Solved by the Invention) Since the metal is deposited using the metal technique, the wiring material is limited to gold or chromium, and it is difficult to use other metal materials.

(Means for Solving the Problems) The present invention provides a semiconductor device comprising a semiconductor element on a substrate and wiring connecting each of the semiconductor elements.
Provided is a semiconductor device characterized in that at least a part of the wiring is connected between conductive pillars provided on the conductive region within the semiconductor element without contacting any other solid substance.

Further, according to the present invention, after forming a semiconductor element on a substrate, forming a metal support on a region of the semiconductor element to be connected to an upper wiring; A method for manufacturing a semiconductor device is obtained, which includes the steps of exposing the pillars, patterning the upper wiring, and removing the filled organic polymer film.

(Function) By providing conductive pillars that make ohmic contact with the conductive region of the semiconductor element, the wiring can be formed flat with low stress and suspended in the air away from the semiconductor element surface, reducing parasitic wiring capacitance. The operating speed of the semiconductor device is improved. Furthermore, since it is not in contact with the insulating film, it has the advantage that stress migration is less likely to occur and the reliability of the wiring is improved.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings. FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor device of the present invention. An n-channel MO transistor (8) consisting of an interelement isolation insulating film 2 for isolating semiconductor elements, a gate oxide film 3, a gate electrode 4, and a high concentration impurity diffusion layer 5 is provided on a silicon substrate 1, and is connected to an upper wiring 7. A semiconductor device in which metal pillars 6 are formed will be described.

FIGS. 3(a) and 3(b) are schematic diagrams sequentially showing the method for manufacturing a semiconductor device of the present invention. An element isolation insulating film 12 made of a silicon oxide film is formed on a p-type silicon substrate 11.
Then, a gate insulating film 13 is formed on the surface of the element formation region.
After forming, a gate electrode 14 as a first wiring is formed in a desired region. Next, arsenic is diffused into the p-type silicon substrate by ion implantation to form an n-type high concentration impurity diffusion layer 15 that will become the source/drain region of the n-channel MIS"K field effect transistor, and then aluminum is
If the remaining aluminum is deposited to a depth of about .mu.m and then removed by etching so as to leave aluminum pillars 16 in regions to be connected to upper wirings, such as source/drain regions and gate electrodes, the result shown in FIG. 3(a) is obtained. Next, an organic resin film 17 such as a positive resist is spin-coated as an interlayer film,
After being melted and flattened by heat treatment, the aluminum and the organic resin film are etched using plasma etching under conditions where the etching rate is constant until at least the surface of all the aluminum pillars is exposed. Deposit aluminum 18. The pattern shown in FIG. 3(b) is obtained by patterning the upper wiring using ordinary photolithography and etching techniques.

Subsequently, when the organic resin film 17 serving as the interlayer film is selectively removed by plasma etching using oxygen gas, a gap is created between the element surface and the upper wiring.

Finally, the structure shown in FIG. 1 is obtained by promoting an alloy reaction between silicon and aluminum by low-temperature heat treatment to form ohmic contact between the interconnection parts.

Normally, the gap 8 in FIG. 1 is filled with air, and since the dielectric constant is as small as about 1, the wiring capacitance can be reduced to a quarter of the conventional level. Moreover, if the element is fixed in a package, bonded, and then sealed in dry nitrogen or vacuum, the stability and reliability of the element can be significantly improved.

In the example, aluminum was used for the metal support and the upper wiring, but different metal materials may be used for each. Among these, materials such as tungsten, molybdenum, titanium, tantalum, and gold, and alloy materials are promising, but It is also possible to use resistive semiconductors.

Furthermore, in the embodiment, one layer of upper wiring was explained, but
After obtaining the structure shown in FIG. 3(b), a second metal support is formed, and the steps of applying the second interlayer film and forming the upper wiring of the second layer are repeated in the same manner. Many of the layer wiring or multilayer wiring can be formed without contacting with an insulator.

Further, in the embodiment of the present invention, the metal support is formed only on the wiring portion of the element, but it may be formed on the insulating film in order to reinforce the bending of the upper wiring.

(Effects of the Invention) By using the present invention, since the interconnects are separated by gas or vacuum, the interconnect capacitance is reduced to a fraction of that of the conventional method, and this has a significant effect on high-speed operation of semiconductor devices. able to demonstrate. Further, when the wiring width is made finer, it is possible to avoid the problem of deterioration in reliability such as wire breakage due to stress migration, which is advantageous in manufacturing a high-density semiconductor device with finer wiring.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor device in an embodiment of the present invention. FIG. 2 is a schematic diagram showing a conventional example, and FIGS. 3(a) and 3(b) are schematic diagrams illustrating the manufacturing process of the present invention. The numbers in the figure indicate the following. 1.11...p-type silicon substrate 2,12...element isolation insulating film 3.13...gate insulating film 4,1
4... Gate electrode 5.15... N-type high concentration impurity diffusion region 6.16... Metal pillar, 7.18.
... Upper wiring 8 ... Gap made of gas 170.・
Interlayer film 31...Gallium arsenide substrate 32...Low concentration n-type layer 33-9. High concentration n-type layer 34...
Au-Ge-Ni alloy 35...Ti-Pb-Au alloy 36...Silicon nitride film 37/Ti-Au wiring Figure 1 1P type silicon substrate 2 Element isolation insulating layer 3 Gate insulating film 4 Gate electrode (No. 1 wiring) 5nn type high impurity diffusion layer 6 metal pillar 7 upper wiring (second wiring) 8 gap made of gas Figure 2 31 Gallium arsenide substrate 32n to layer 33 n+ layer 34 Au-Ge-Ni alloy 3
5 Ti-Pd-Au alloy 36SiN film 37Ti-A
U wiring Figure 3 11 P-type silicon substrate 12 Element isolation insulating layer 13 Gate insulating film 14 Gate electrode 15 N-type high concentration impurity diffusion layer 16 Metal pillar 17 Temporary interlayer film 18 Upper wiring

Claims (2)

[Claims] (1) In a semiconductor device constituted by a semiconductor element on a substrate and wiring connecting each of the semiconductor elements, conductivity within the semiconductor element can be achieved without at least a part of the wiring coming into contact with other solid substances. A semiconductor device characterized in that a wire is connected between conductive pillars provided on a region. (2) After forming a semiconductor element on a substrate, forming a metal support on a region to be connected to an upper wiring in the semiconductor element, and exposing the metal support after filling with a polymeric organic film. 1. A method of manufacturing a semiconductor device, comprising: a step of patterning an upper wiring; and a step of removing the filled organic polymer film.