JPH02168786A - Chrominance signal processing circuit - Google Patents

Abstract

PURPOSE:To decrease the number of high speed multipliers necessary for chrominance signal processing by effectively utilizing a horizontal blanking period, containing the information of an ACC signal in a second matrix coefficient, multiplying this coefficient with the chrominance signal of a picture pattern, and obtaining a corrected chrominance signal. CONSTITUTION:A multiplification processing between an ACC signal A0 and the first matrix coefficiencies RQ1-BI1 is executed during a horizontal blanking period T0 and new matrix coefficiencies RQ2-BI2 are formed. The multification processing between the ACC signal A0 and a color burst is executed during a next period T1 and the new ACC signal A0 is formed. The multification between the previously calculated new matrix coefficiencies RQ2-BI2 and the picture pattern is executed during a period T2 and the corrected chrominance signal is outputted. Consequently, multification processings respectively necessary during the horizontal blanking period T0, the gain adjustment period T1 and the image period Ts can be executed through one multiplier.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a digital television device that performs signal processing after digitizing a video signal, and particularly relates to a color signal processing circuit thereof.

(Prior Art) Significant advances in digital IC technology have made it possible to perform baseband signal processing in television receivers digitally, which was conventionally performed analog. In terms of performance, the advantages of digitizing the signal processing circuit are that high precision and distortion-free processing unique to digital are now possible, as well as improved resistance to temperature changes, changes over time, and noise resistance. In terms of functionality, it can be combined with memory and computers, and can be used for multi-screen televisions, scanning speed conversion,
Still images, special effects processing, etc. can be easily processed, and connections with various new media signals, which are digital signals, can also be made easier.

FIG. 4 shows a general configuration of a digital video processing section.

The analog video signal AV is sampled and digitized by an analog-to-digital converter 102 and converted into a digital video signal DV. The sampling is
This is performed at the timing of a summing pulse (+) S output from a voltage controlled crystal oscillator (hereinafter referred to as VCXO) 103.

The frequency of the sampling pulse ΦS is four times the color subcarrier frequency fsc, and the phase is synchronized with the demodulation axis of the color signal.

The following explanation will take I,Q demodulation as an example. Therefore, the sample phase in this case becomes the upper {circle around (2)}, ±Q phase. Control of the sample phase is performed by a phase-locked Dorp (PLL) circuit 106. The PLL circuit 106 calculates the sample phase in the color burst section of the input digital video signal DV, and calculates the sample phase and 1. A phase error signal S] corresponding to the difference from the Q phase is output. The phase error signal S1 is v c
Control the oscillation frequency of X O1, 03, thereby synchronizing the phase of the Zumble pulse ΦS with the I and Q phases.)
Closed-loop control is performed. In addition, sample gurus Φ
S is supplied to each circuit as a reference clock 7 in digital processing.

The digital video signal DV has a luminance/chromaticity separation circuit < y
The luminance signal Y] and the chrominance signal C are separated at 108 (referred to as F Y /c',>pre-circuit). The brightness signal Y] is subjected to contour, contrast, and brightness adjustments in the brightness processing circuit 1]2, and then output as a new brightness signal Y2. The color signal C is subjected to automatic saturation control (ACC), color saturation adjustment, hue adjustment, color demodulation, and matrix calculation processing in the color signal processing circuit]]3, and is processed into three color difference signals (RY), ((, - Y) and (B-Y) and output.The timing signal S2 necessary for this processing is input from the PLL circuit]06.The color difference signals (R-Y), (B-Y) are G-Y), (BY) are adder 1
2], ]22.123, it is added to the luminance signal Y2 and output as color signals R, G, and B. After these signals are digital-to-analog converted, they drive a color cathode ray tube through an output circuit. Also, controller 2
4 includes an image quality adjustment signal 125 controlled by the viewer and a controller 2 necessary for various automatic controls from the digital processing section.
4]26 is input. The controller 24 processes input signals 125 and 126 based on a predetermined program and outputs them as signal processing parameters 127 to each circuit of the digital processing section.

The above is an outline of the entire digital processing section. Next, the color signal processing circuit 113 will be explained.

FIG. 5 shows a conventional color signal processing circuit 113. As shown in FIG.

The color signal C from the Y/C separation circuit 108 is sent to the multiplier 201.
and is multiplied by the ACC signal A2. The output signal C1 of the multiplier 201 is input to the ACC circuit 203. here,
The amplitude of the color burst is detected, and the magnitude of the ACC signal A2 is controlled so that the amplitude approaches a predetermined target value. As a result, amplitude changes in the color signal C caused by characteristics of the transmission path from the transmitting station to the receiver are corrected.

A burst flag pulse (BFP) indicating the color burst position is input to the ACC circuit 203, and the AC
C operation timing is set.

The output of the multiplier 201 is sent to the data latch circuit 205.20.
6 is input. The data latch circuit 205 extracts one phase data from the input signal C1, and outputs the ■signal (I, D
) is demodulated. The timing of data extraction is pulse Φ
given by I. Similarly, data latch circuit 206
Then, Q phase data is extracted by pulse ΦQ, and Q
The signal (DQ) is demodulated. Pulse Φ11ΦQ is generated by timing circuit 207 based on color demodulation pulse ΦC.

The color demodulation pulse ΦC is output from the PLL circuit 1.06 together with the burst flag pulse BPF, and is a pulse that always provides constant phase timing (for example, Q phase).

The demodulated digital signal (ID) and Q signal (QD) are input to the color adjustment circuit 17. This iron uses a sine signal (Alsin θ) input from the controller 24,
Color saturation adjustment and hue adjustment are performed using cosine signals (A], , cos θ). signal (Alsinθ),
(Alcos θ) is calculated by the controller] 24 based on the color saturation signal A1 and hue signal θ, which are controlled by the viewer, and (Alsin θ) and (Alc
osθ). The color adjustment circuit 217 performs gain adjustment and coordinate rotation calculations as shown in the following equation on the input I and Q signals to obtain a multiplication signal (I'D) and a Q' multiplied signal (Q'D).
I am getting .

That is, compared to the input, the color density of the output will be A1 times greater, and the hue will change by θ.

The signal M D and the signal Q' D are transmitted to the multipliers 221 to 2
26. In the adders 227 to 229, the color difference signals (R-Y), (G-Y),
(B-Y).

Matrix coefficients (R1, RQ, GISGQ.

Bl, BQ) are provided by the controller 124.

This value is not always a fixed value according to theory, but must be changed depending on the characteristics of the color cathode ray tube used.

(Problems to be Solved by the Invention) In the conventional color signal processing method described above, ACC processing,
At least 9 multipliers are required for color saturation/hue adjustment and 7-trix operations. As is well known, the circuit scale of a multiplier is large; for example, an (8×8) bit multiplier has about 1000 gates. This becomes a serious problem when converting the system to an IC. Matrix operations in particular require a large number of circuits. However, if this is digitized, the external input digital R
Not only does it facilitate connection with GB signals, but it also reduces the number of external parts required for analog matrix circuits, which has great benefits.

Therefore, there has been a strong desire to reduce the amount of circuitry in matrix circuits.

SUMMARY OF THE INVENTION An object of the present invention is to provide a color signal processing circuit that can significantly reduce the number of high-speed multipliers required for color signal processing (ACC, color saturation/hue adjustment, matrix calculation).

[Structure of the Invention] (Means for Solving the Problems) This invention creates a new ACC signal from a new color burst obtained by multiplying a color burst and an ACC signal during a color burst period of a digital color signal. ACC generating means; and means for preparing a second matrix coefficient by multiplying the new ACC signal by a first 7-trix coefficient determined from system characteristics and user adjustment information during a horizontal blanking period; a means for multiplying the digital color signal by the second matrix coefficient during the picture period to obtain a corrected digital color signal; and a sum of the corrected digital color signal and a signal obtained by delaying the corrected digital color signal by one sample. and means for obtaining a color difference signal from the color difference signal.

(Operation) By the above means, different types of calculations are performed in a time-sharing manner. The second matrix coefficients are prepared during the horizontal blanking period and include the color saturation signal or hue signal and ACC information in advance. Therefore, the corrected color signal can be directly demodulated and separated into hue components, simplifying the system configuration.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The color signal C from the Y/C separation circuit is input to the signal conversion circuit 401, where the -○ phase data is converted to +Q, the -■ phase data is converted to +■, respectively...Q, I, QS I, It is converted into a color signal CIO having a data format of QS I.... This is an operation to facilitate subsequent processing.

The color signal CIO is an AC signal output from the ACC circuit 405.
It is input to multiplexer 402 together with C signal AO.

The output of multiplexer 402 is input to multiplier 403.

In the ACC circuit 405, the amplitude of the color burst is detected, and the ACC circuit 405 detects the amplitude of the color burst.
The magnitude of signal AO is controlled.

In the multiplexer 402, the ACCCC signal 0
and the color signal CIO, and the output signal C
1l becomes as shown in FIG. 2 (2b). Period (T
O), A, the ACC signal from the CC circuit 405 (A
O) is selected, and input color signals (burst and picture color signals) are selectively derived in periods (T1) and (T2).

The output signals C1, I are input to the multiplier 403, and subjected to multiplication processing by the output signal from the multiplexer 427 by 10 (matrix coefficient, ACC signal).

In the period (TO), multiplication processing of the ACC signal (AO) and the first matrix coefficients (RQI to BII) is performed,
New matrix coefficients (RQ2-BI2) are created. In the next period (T1), a multiplication process of the ACC signal (AO) and the color burst]1 is performed, and the amplitude of the resulting color burst I is detected by the ACC circuit 405, and a new ACC signal (AO
) is created. Then, in period (T2), the new matrix coefficients (RQ2 to BI2) calculated previously are multiplied by the picture color signal, and the corrected color signal is output.

The output signal C12 of the multiplier 403 has been subjected to ACC control, color saturation adjustment, and hue adjustment, and is sent to the delay circuit 43.
0, adder 431, registers 432 to 434, etc. perform matrix operations, (RY), (G-Y), (B-
Y) is demodulated into color difference signals, and each color difference signal is separated.

Next, multiplexers 402.427.421-426
, the registers 411 to 416 will be explained with reference to FIGS. 2 and 3.

First, the controller 440 controls the matrix RQI~B
II can be output. These matrix coefficient coefficients RQI to Bll are matrix coefficients RQO, RIO, and GQ according to preprogrammed cathode ray tube characteristics.
O, GIO1]2 BQO, BIO and color saturation signal AI adjusted by the user
and hue (θ).

The arithmetic processing for this is as follows. Therefore, the 7 trix coefficients RQI~Bll are the saturation level,
It will include hue adjustment information. 7 Trix coefficient RQ
I to BI] are the corresponding multiplexers 42
1 to 426, is time-divisionally derived during the required period (TO), and is input to the multiplier 403 via the multiplexer 427.

This period (TO) is before the color burst period,
This is a horizontal blanking period (no signal period).

Processing during the period (TO) will be explained.

During this period (To), the multiplexer 402
The ACC signal (AO) from the C circuit 405 is selected. As a result, the multiplier 403 performs arithmetic processing on the ACC signal (AO) and matrix coefficients RQI to Bll, and generates new matrix coefficients RQ2 to BI.
Create 2. The second matrix coefficients RQ2 to BI2 obtained in this way are stored in the corresponding registers 41.
1 to 416.

This means that new matrix coefficients RQ2 to BI2 have been prepared.

Next, processing of the period (TI) will be explained. During this period (TI), the multiplexer 402 outputs the color signal CIO
Select. Multiplexer 427 also selects the ACC signal from ACC circuit 405. This result multiplier 4
In step 03, the ACC signal (AO) and the color burst are multiplied, and the multiplier 403 obtains a color burst that has been subjected to amplitude control. Here, the ACC circuit 405 is
It is determined whether the color burst has a predetermined amplitude or not, and the value of the ACC signal (AO) is adjusted according to the deviation from the predetermined value, thereby controlling the color burst to a constant value.

Therefore, a new ACC signal (AO) is stored in this ACC circuit 405.

This ACC signal (AO) is used to create the second matrix coefficients in the next horizontal blanking period, as described in the processing of time periods (TO). As a result, the second matrix coefficients RQ2 to BI2 correspond to the ACC signal (
AO) information will also be included.

Processing during period (T2) will be explained.

During this period (T2), the second matrix coefficients RQ2 to BI2 prepared earlier are stored in the registers 411 to 416.
are output as signals K] to KG, pass through multiplexers 421 to 426, and further output to multiplexer 4.
27 to the multiplier 403. On the other hand, the multiplexers 4 and 02 select the input color signal CIO and supply it to the multiplier 403.

As a result, a color signal C12 whose color saturation, hue, and amplitude are controlled can be obtained from the multiplier 403.

FIG. 3 shows the color signal C1 input to the multiplier 403 described above.
, 1 and the second matrix coefficients RQ2 to BI2 input as coefficients KIO.

This multiplication processing result is supplied to a delay circuit 430 having a delay amount of one sample and an adder 431.

The output of the delay circuit 430 is also supplied to the adder 431 . Therefore, as shown in FIG. 3, the adder 431 demodulates and outputs color difference signals of (RY), ((, -Y), and (B-Y) every other sample. The color difference signals are latched into registers 432, 433, and 434 at timings corresponding to the respective signals, separated, and output.

The color difference signal is calculated using the following formula.

The timing signal (tn) necessary for the above system operation is generated by the timing circuit 441 using a burst flag pulse (BFP) and a color demodulation pulse (ΦC).
Supplied to each part.

In this embodiment described above, the information of the ACC signal is included in the second matrix coefficient by effectively utilizing the horizontal blanking period, and the color signal of the picture period is multiplied by this second matrix coefficient. You can obtain corrected color signals. That is, the periods during which the necessary arithmetic processing is required are effectively classified, and the arithmetic processing is performed on a time-sharing basis. This allows the system to be simplified and the number of multipliers that must be used to be reduced.

Furthermore, by making the above-mentioned time-sharing processing possible, the horizontal blanking period (TO) and the gain adjustment period (
T]) and the image period (T2), each necessary multiplication process can be performed by one multiplier. In other words, it is possible to implement the calculations necessary for color signal processing with a minimum number of multipliers.

[Effects of the Invention] As explained above, the present invention provides color signal processing (ACC1
The number of high-speed multipliers required for color saturation/hue adjustment and matrix calculations can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention; FIG. 2 is a timing and signal explanatory diagram for explaining the operation of the circuit in FIG. 1; FIG. 4 is a diagram showing a digital video signal processing circuit, and FIG. 5 is a circuit diagram showing a conventional color signal processing circuit. 401...Signal conversion circuit, 402.427.421~
426... Multiplexer, 403... Multiplier, 4
05...ACC circuit, 430...Delay circuit, 411
~416.432.433.434...Register. Applicant's agent Patent attorney Takehiko Suzue CJ'<

Claims (1)

[Scope of Claims] ACC generating means for generating a new ACC signal from a new color burst obtained by multiplying the color burst and the ACC signal in the color burst period of the digital color signal; means for preparing a second matrix coefficient by multiplying the ACC signal by the first matrix coefficient obtained from the system characteristics and the user's adjustment information; and means for obtaining a color difference signal from the sum of the corrected digital color signal and a signal delayed by one sample. color signal processing circuit.