JPH0216666B2 - - Google Patents

Info

Publication number
JPH0216666B2
JPH0216666B2 JP57044380A JP4438082A JPH0216666B2 JP H0216666 B2 JPH0216666 B2 JP H0216666B2 JP 57044380 A JP57044380 A JP 57044380A JP 4438082 A JP4438082 A JP 4438082A JP H0216666 B2 JPH0216666 B2 JP H0216666B2
Authority
JP
Japan
Prior art keywords
voltage
power supply
winding
capacitor
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57044380A
Other languages
Japanese (ja)
Other versions
JPS58163277A (en
Inventor
Takahiro Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Life Solutions Ikeda Electric Co Ltd
Original Assignee
Ikeda Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ikeda Electric Co Ltd filed Critical Ikeda Electric Co Ltd
Priority to JP57044380A priority Critical patent/JPS58163277A/en
Publication of JPS58163277A publication Critical patent/JPS58163277A/en
Publication of JPH0216666B2 publication Critical patent/JPH0216666B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Description

【発明の詳細な説明】 本発明はトランジスタを用いたインバータ回路
に関し、２次巻線側に発生するサージ電圧により
トランジスタが破損するのを防止するようにした
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inverter circuit using transistors, and is designed to prevent damage to the transistors due to surge voltage generated on the secondary winding side.

従来から知られているプツシユプルインバータ
回路として第１図に示すものがある。この構成を
説明すると、インバータトランスＴの１次巻線
NP1，NP2の中間タツプt1をチヨークCHを介し
て直流電源Ｅのプラス端子P1に接続すると共に、
同巻線NP1，NP2の各端子を夫々トランジスタ
TR1，TR2のコレクタ、エミツタを介して直流電
源Ｅのマイナス端子P2に接続しており、またト
ランスＴの帰還巻線NBの中間タツプをバイアス
抵抗Ｒを介してプラス端子P1に接続すると共に、
帰還巻線NBの各端子を夫々前記トランジスタ
TR1，TR2のベースに接続している。また１次巻
線NP1，NP2に並列に共振コンデンサC0を接続し
ている。なおＬは２次巻線NSの両端子P3，P4間
に接続した負荷である。 A conventionally known push-pull inverter circuit is shown in FIG. To explain this configuration, the primary winding of the inverter transformer T
Connect the intermediate tap t1 of NP 1 and NP 2 to the positive terminal P 1 of the DC power supply E via the chain yoke CH, and
Each terminal of the same winding NP 1 and NP 2 is connected to a transistor respectively.
The collectors and emitters of TR 1 and TR 2 are connected to the negative terminal P 2 of the DC power supply E, and the intermediate tap of the feedback winding NB of the transformer T is connected to the positive terminal P 1 through the bias resistor R. At the same time,
Each terminal of the feedback winding NB is connected to the transistor
Connected to the base of TR 1 and TR 2 . Furthermore, a resonant capacitor C 0 is connected in parallel to the primary windings NP 1 and NP 2 . Note that L is a load connected between both terminals P 3 and P 4 of the secondary winding NS.

次に動作を説明すると、トランジスタTR1，
TR2のいずれかをバイアス抵抗Ｒを介してベース
電流を流してオンさせ、帰還巻線NBに誘起され
る電圧によりトランジスタTR1，TR2を交互にオ
ン・オフさせて２次巻線NSに所定周波の交流電
力を誘起させる。即ち、帰還巻線NBに誘起させ
る電圧は１次巻線NP1，NP2のインダクタンスと
共振コンデンサC0の容量とで決定される共振電
圧と同期の正弦波の電圧であり、その極性は共振
に従つて交番し、帰還巻線NBの極性によりバイ
アス抵抗Ｒを介して流れる電流をトランジスタ
TR1のベースかトランジスタTR2のベースに流
し、トランジスタTR1，TR2をオンオフさせる。
例えば帰還巻線NBの極性が第１図のようになつ
ている場合、帰還巻線NBの電圧によりトランジ
スタTR2のベース、エミツタ間が順方向、トラン
ジスタTR1のベース、エミツタ間が逆方向に電圧
が印加される為バイアス抵抗Ｒを介して流れる電
流はトランジスタTR2のベースに流れ、トランジ
スタTR2がオンになり、トランジスタTR1がオフ
になり、帰還巻線NBの極性が反転するとトラン
ジスタTR1がオフしトランジスタTR2がオンにな
る。そして、トランジスタTR1，TR2に流れるベ
ース電流は直流電源Ｅの電圧、バイアス抵抗Ｒの
抵抗値及び帰還巻線NBの電圧で決定される。 Next, to explain the operation, the transistors TR 1 ,
Transistors TR 1 and TR 2 are turned on by passing a base current through the bias resistor R through the bias resistor R, and the voltage induced in the feedback winding NB turns transistors TR 1 and TR 2 on and off alternately. AC power of a predetermined frequency is induced. In other words, the voltage induced in the feedback winding NB is a sine wave voltage that is synchronous with the resonant voltage determined by the inductance of the primary windings NP 1 and NP 2 and the capacitance of the resonant capacitor C 0 , and its polarity is determined by the resonance voltage. According to the polarity of the feedback winding NB, the current flowing through the bias resistor R is
It flows into the base of TR 1 or the base of transistor TR 2 , turning transistors TR 1 and TR 2 on and off.
For example, if the polarity of the feedback winding NB is as shown in Figure 1, the voltage of the feedback winding NB will cause the voltage between the base and emitter of transistor TR 2 to be in the forward direction, and the voltage between the base and emitter of transistor TR 1 to be in the reverse direction. Due to the applied voltage, the current flowing through the bias resistor R flows to the base of the transistor TR 2 , turning on the transistor TR 2 and turning off the transistor TR 1 , and when the polarity of the feedback winding NB is reversed, the transistor TR 1 turns off and transistor TR 2 turns on. The base current flowing through the transistors TR 1 and TR 2 is determined by the voltage of the DC power supply E, the resistance value of the bias resistor R, and the voltage of the feedback winding NB.

ところが、このインバータ回路では以下の問題
がある。インバータ回路は直流電源Ｅよりトラン
ジスタTR1，TR2をインバータトランスＴを介し
てオンオフさせて、２次巻線NSより負荷Ｌに交
流電圧を供給するのであるが、反対に負荷Ｌ側か
らサージ電圧が２次巻線NSに印加されることが
あり、このときトランジスタTR1，TR2のコレク
タ、エミツタ間電圧が異常に高くなり、トランジ
スタTR1，TR2が耐圧を越え短絡破壊することが
ある。即ち、インバータ回路は通常時直流電源Ｅ
を交流に変えて負荷Ｌに供給するようになつてお
り、この場合においてトランジスタTR1，TR2の
耐圧が選定されているのであるが、負荷Ｌ側から
サージ電圧が印加されたときトランジスタTR1，
TR2に印加される電圧が通常よりも高くなること
があり、サージが大きくなるといくらでも大きく
なり、破壊につながることがある。 However, this inverter circuit has the following problems. In the inverter circuit, transistors TR 1 and TR 2 are turned on and off from a DC power supply E via an inverter transformer T, and an AC voltage is supplied to a load L from a secondary winding NS. may be applied to the secondary winding NS, and at this time, the voltage between the collector and emitter of transistors TR 1 and TR 2 may become abnormally high, causing transistors TR 1 and TR 2 to exceed their withstand voltage and be short-circuited and destroyed. . That is, the inverter circuit normally uses the DC power supply E.
is changed to alternating current and supplied to the load L. In this case, the withstand voltage of the transistors TR 1 and TR 2 is selected, but when a surge voltage is applied from the load L side, the transistor TR 1 ，
The voltage applied to TR 2 can be higher than normal, and the surge can be large enough to cause damage.

さらに具体的に説明すると、２次巻線NSにサ
ージ電圧が印加されると、１次巻線NP1，NP2に
サージ電圧が誘起しようとするが、１次巻線
NP1，NP2に並列に接続された共振コンデンサC0
でこのサージ電圧を吸収し抑えるように作用す
る。しかしサージ電圧が大きい場合は吸収しきれ
ず、１次巻線NP1，NP2の電圧が高くなり、トラ
ンジスタTR1，TR2のコレクタ、エミツタ間に高
電圧が印加される。サージ電圧によりトランジス
タTR1，TR2の電圧が高くならない様にするに
は、１次巻線NP1，NP2の電圧が高くなつたとき
に直流電源Ｅへ吸収するようにすると、サージ電
圧が高くなつても吸収は可能となり、トランジス
タTR1，TR2の電圧が高くならずに済む。ところ
が、第１図のインバータ回路ではチヨークCHが
直流電源Ｅと直列に接続されている為、１次巻線
NP1，NP2の電圧が高くなつても、直流電源Ｅの
方へは吸収できず、トランジスタTR1，TR2の電
圧が高くなつてしまう。 To explain more specifically, when a surge voltage is applied to the secondary winding NS, surge voltage tries to be induced in the primary windings NP 1 and NP 2 , but
Resonant capacitor C 0 connected in parallel to NP 1 and NP 2
It acts to absorb and suppress this surge voltage. However, if the surge voltage is large, it cannot be absorbed completely, and the voltage of the primary windings NP 1 and NP 2 becomes high, and a high voltage is applied between the collectors and emitters of the transistors TR 1 and TR 2 . In order to prevent the voltage of the transistors TR 1 and TR 2 from increasing due to surge voltage, when the voltage of the primary windings NP 1 and NP 2 increases, it is absorbed by the DC power supply E, and the surge voltage is Even if the voltage increases, absorption is possible, and the voltages of the transistors TR 1 and TR 2 do not increase. However, in the inverter circuit shown in Figure 1, since the chiyoke CH is connected in series with the DC power supply E, the primary winding
Even if the voltages of NP 1 and NP 2 become high, they cannot be absorbed into the DC power supply E, and the voltages of transistors TR 1 and TR 2 end up becoming high.

本発明は上記問題点を解消したもので、その特
徴とするところは、インバータトランスＴの１次
巻線NP1，NP2の中間タツプt1をチヨークCHを
介して直流電源Ｅの一端に接続すると共に、前記
１次巻線NP1，NP2の各端子を夫々トランジスタ
TR1，TR2のコレクタ、エミツタを介して直流電
源Ｅの他端に接続したトランジスタインバータ回
路において、 前記チヨークCHに、コンデンサC1とダイオー
ドD1との直列回路を該ダイオードD1が直流電源
側に位置しかつオン時に直流電源Ｅに逆方向に電
圧を印加するように並列接続し、前記チヨーク
CHに２次巻線a2を設け、該２次巻線a2の一端を
直流電源Ｅの前記チヨークCHとは反対側に接続
すると共に、他端をダイオードD1とコンデンサ
C1との間に接続した点にある。 The present invention has solved the above problems , and its feature is that the intermediate tap t1 of the primary windings NP1 and NP2 of the inverter transformer T is connected to one end of the DC power supply E via the chain yoke CH. At the same time, each terminal of the primary windings NP 1 and NP 2 is connected to a transistor, respectively.
In a transistor inverter circuit connected to the other end of a DC power source E through the collectors and emitters of TR 1 and TR 2 , a series circuit of a capacitor C 1 and a diode D 1 is connected to the transistor CH, and the diode D 1 is connected to the DC power source. and connected in parallel so as to apply a voltage in the opposite direction to the DC power supply E when turned on, and
A secondary winding a 2 is provided on CH, and one end of the secondary winding a 2 is connected to the opposite side of the DC power supply E from the aforementioned CH yoke CH, and the other end is connected to a diode D 1 and a capacitor.
It is located at the point connected between C1 .

以下、本発明を図示の実施例に従つて説明する
と、第２図に示す如く、チヨークCHに、コンデ
ンサC1とダイオードD1との直列回路を並列接続
し、チヨークCHに２次巻線a2を設けている。チ
ヨークCHの１次巻線a1と２次巻線a2とは同一鉄
心上に巻かれ、かつ第２図に示す極性に同一の巻
数で巻回されている。 Hereinafter , the present invention will be explained according to the illustrated embodiment. As shown in FIG. 2 are provided. The primary winding a 1 and the secondary winding a 2 of the chain yoke CH are wound on the same iron core, and are wound with the same number of turns with the polarity shown in FIG. 2.

次に動作を説明する。コンデンサC1は直流電
源Ｅより巻線a1，a2を介して充電されるが、この
とき巻線a1，a2のインダクタンスは打ち消しあ
い、コンデンサC1は第２図の極性に直流電源Ｅ
の電圧VEと同一電圧まで充電される。ダイオー
ドD1には１次巻線a1の電圧とコンデンサC1の電
圧の和が印加されるが、通常１次巻線a1の電圧は
コンデンサC1の電圧（電源電圧VE）より小であ
る為、ダイオードD1はオフしている。また第１
図のチヨークCHに流れる電流はリツプルをほと
んど含まない直流であり、第２図の回路において
も１次巻線a1に第１図の場合と同様に直流が流
れ、２次巻線a2には電源電圧が変化したときのみ
コンデンサC1の充放電電流が流れる。従つて１
次巻線a1、コンデンサC1、ダイオードD1は通常
動作に影響をあたえない。第３図の波形図を参照
して説明すると、第３図の波形イは直流電源Ｅの
電圧、波形ロは１次巻線NP1の電圧（１次巻線
NP2の電圧）、波形ハはチヨークCHの１次巻線a1
（２次巻線a2）の電圧、波形ホはダイオードD1の
電圧を示している。即ち、通常時の１次巻線NP1
（１次巻線NP2）の電圧は直流電源Ｅの電圧VEに
より波形ロの如く決定され、負荷Ｌが変動しても
一定である。また通常時ダイオードD1は常にオ
フ状態である。トランジスタTR1，TR2は交互に
オンオフしており、どの時期においても必ず一方
のトランジスタTR1，TR2はオンし、トランジス
タTR1，TR2のコレクタ、エミツタ間に印加され
る電圧（波形ニ）は１次巻線NP1，NP2の電圧の
和である。そして、サージ電圧により１次巻線
NP1，NP2の電圧が高くなると点P5，P2間の電圧
が高くなるが、点P5，P2間の電圧が直流電源Ｅ
の電圧VEの２倍の電圧より高くなると、コンデ
ンサD1がオンし、点P5，P2間の電圧は２・VEよ
り高くならず、このためトランジスタTR1，TR2
のコレクタ、エミツタ間電圧は４・VEより高く
ならない。従つて、サージ電圧により１次巻線の
電圧が高くなつても、その電圧を直流電源に吸収
させることができ、サージ電圧によるトランジス
タの破損を確実に防止できる。 Next, the operation will be explained. Capacitor C 1 is charged by DC power supply E through windings a 1 and a 2 , but at this time, the inductances of windings a 1 and a 2 cancel each other out, and capacitor C 1 is charged by DC power supply E with the polarity shown in Figure 2. E
is charged to the same voltage as the voltage VE . The sum of the voltage of the primary winding a 1 and the voltage of the capacitor C 1 is applied to the diode D 1 , but the voltage of the primary winding a 1 is usually lower than the voltage of the capacitor C 1 (power supply voltage V E ). Therefore, diode D1 is off. Also the first
The current flowing through the chain yoke CH in the figure is a direct current containing almost no ripples, and in the circuit shown in figure 2, direct current flows through the primary winding a1 as in the case of figure 1, and the current flows through the secondary winding a2. The charging/discharging current of capacitor C1 flows only when the power supply voltage changes. Therefore 1
The secondary winding a 1 , capacitor C 1 , and diode D 1 do not affect normal operation. To explain with reference to the waveform diagram in Fig. 3, waveform A in Fig. 3 is the voltage of DC power supply E, and waveform B is the voltage of primary winding NP 1 (primary winding
NP 2 voltage), waveform C is primary winding a 1 of CH
(Secondary winding a 2 ) voltage, waveform E shows the voltage of diode D 1 . In other words, the primary winding NP 1 during normal operation
The voltage of (primary winding NP 2 ) is determined by the voltage V E of the DC power supply E as shown in waveform B, and remains constant even if the load L fluctuates. In addition, the diode D1 is normally in an off state. The transistors TR 1 and TR 2 are turned on and off alternately, and one of the transistors TR 1 and TR 2 is always turned on at any time, and the voltage (waveform nil) applied between the collector and emitter of the transistors TR 1 and TR 2 is ) is the sum of the voltages of the primary windings NP 1 and NP 2 . The surge voltage causes the primary winding to
When the voltage of NP 1 and NP 2 increases, the voltage between points P 5 and P 2 increases, but the voltage between points P 5 and P 2 increases due to the DC power supply E.
When the voltage V E becomes higher than twice the voltage, the capacitor D 1 turns on, and the voltage between the points P 5 and P 2 does not become higher than 2·V E , so that the transistors TR 1 and TR 2
The voltage between the collector and emitter of is not higher than 4·V E. Therefore, even if the voltage of the primary winding increases due to a surge voltage, the voltage can be absorbed by the DC power supply, and damage to the transistor due to the surge voltage can be reliably prevented.

第４図は他の実施例を示し、チヨークCHに２
次巻線a2に加えて２次巻線a3を設けたものであ
り、点P5，P2間の電圧がサージにより高くなり
巻線a1，a2，a3の電圧が高くなつた時、２次巻線
a2、ダイオードD1、２次巻線a3、直流電源Ｅの
ループでダイオードD1がオン又は１次巻線a1、
コンデンサC1、ダイオードD1、２次巻線a3のル
ープでダイオードD1がオンし、巻線a2，a3の電
圧の和が電源電圧VE以下になり、また巻線a1，
a2の電圧の和をコンデンサC1の電圧（＝電源電圧
VE）に抑える事ができる。即ち、巻線a1（巻線
a2）の電圧を電源電圧VEより低く制御でき、点
P2，P5間の電圧を電源電圧VEの２倍より低く
（例えば3.7／２・VE）制御できる。 Figure 4 shows another embodiment, in which 2
A secondary winding a3 is provided in addition to the secondary winding a2 , and the voltage between points P5 and P2 increases due to a surge, and the voltage of windings a1 , a2 , and a3 increases. When the secondary winding
a 2 , diode D 1 , secondary winding a 3 , diode D 1 is on in the loop of DC power supply E or primary winding a 1 ,
Diode D 1 is turned on in the loop of capacitor C 1 , diode D 1 , and secondary winding a 3 , and the sum of the voltages of windings a 2 and a 3 becomes below the power supply voltage VE , and the windings a 1 ,
The sum of the voltages of a 2 and the voltage of capacitor C 1 (= power supply voltage
V E ) can be suppressed. That is, winding a 1 (winding
a 2 ) voltage can be controlled to be lower than the power supply voltage V E , and the point
The voltage between P 2 and P 5 can be controlled to be lower than twice the power supply voltage VE (for example, 3.7/2·V E ).

第５図はさらに他の実施例を示し、直流電源Ｅ
を、コンデンサC2，C3及びダイオードD2，D3，
D4を有する平滑回路Ｑと商用電源E1と整流回路
DBとにより構成すると共に、チヨークCHの１
次巻線を巻線a1′と巻線a1″とに分割し、コンデン
サC2へサージ電圧を吸収させるようにしたもの
であり、巻線a1′の電圧を１／２・VEに制御すること により、巻線a1′と巻線a1″との電圧の和を1.5／２VE に制限し、点P5，P2間の電圧を3.5／２VEに制限し ている。その他の点は前記実施例と同様である。
本発明によれば、チヨークCHに、コンデンサC1
とダイオードD1との直列回路を該ダイオードD1
が直流電源側に位置しかつオン時に直流電源Ｅに
逆方向に電圧を印加するように並列接続し、前記
チヨークCHに２次巻線a2を設け、該２次巻線a2
の一端を直流電源Ｅの前記チヨークCHとは反対
側に接続すると共に、他端をダイオードD1とコ
ンデンサC1との間に接続したので、サージ電圧
によりインバータトランスＴの１次巻線NP1，
NP2が高くなつても、その電圧を直流電源に吸収
させることができ、従つてトランジスタTR1，
TR2の電圧が一定以上に高くなることはなくな
り、サージ電圧によるトランジスタTR1，TR2の
破損を確実に防止できる。しかも、チヨークCH
に設けた２次巻線a2があるため、前記コンデンサ
C1やダイオードD1が通常動作に影響をあたえず、
非常に簡単な構成で通常時に従来通り動作させる
ことが可能になり、また２次巻線a2があるため
に、直流電源Ｅと、ダイオードD1及びコンデン
サC1の接続点との間に抵抗を設ける必要がなく
なり、このため、コンデンサC1の充放電時間が
略０になり、サージが連続して入つた場合でもこ
れを十分吸収でき、またこの部分での抵抗損がな
くなり、その効果は著大である。 FIG. 5 shows still another embodiment, in which the DC power source E
, capacitors C 2 , C 3 and diodes D 2 , D 3 ,
Smoothing circuit Q with D 4 and commercial power supply E 1 and rectifier circuit
It is composed of DB and 1 of Chiyoke CH.
The next winding is divided into winding a 1 ′ and winding a 1 ″, and the surge voltage is absorbed by capacitor C 2 , and the voltage of winding a 1 ′ is reduced to 1/2・V E By controlling to _ _ _ . Other points are the same as in the previous embodiment.
According to the invention, a capacitor C 1 is added to the capacitor CH.
The series circuit with diode D 1 and diode D 1
are located on the DC power supply side and are connected in parallel so as to apply a voltage in the opposite direction to the DC power supply E when turned on, and a secondary winding a 2 is provided on the CH yoke CH, and the secondary winding a 2
Since one end is connected to the opposite side of the DC power source E from the above-mentioned chain yoke CH, and the other end is connected between the diode D1 and the capacitor C1 , the surge voltage causes the primary winding NP1 of the inverter transformer T to ，
Even if NP 2 becomes high, the voltage can be absorbed by the DC power supply, and therefore the transistors TR 1 ,
The voltage of TR 2 will no longer rise above a certain level, and damage to transistors TR 1 and TR 2 due to surge voltage can be reliably prevented. Moreover, Chiyoke CH
Since there is a secondary winding a2 installed in the capacitor
C 1 and diode D 1 do not affect normal operation,
With a very simple configuration, it is possible to operate as before under normal conditions, and because there is a secondary winding A2 , there is no resistance between the DC power supply E and the connection point of the diode D1 and capacitor C1 . This eliminates the need to provide a capacitor C1 , and as a result, the charging and discharging time of the capacitor C1 becomes almost 0, and even if surges occur continuously, they can be sufficiently absorbed, and there is no resistance loss in this part, so the effect is It is significant.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来例を示す回路図、第２図は本発明
の一実施例を示す回路図、第３図は動作説明用の
電圧波形図、第４図及び第５図は夫々他の実施例
を示す回路図である。 Ｅ……直流電源、Ｔ……インバータトランス、
NP1，NP2……１次巻線、CH……チヨーク、a1
……１次巻線、a2……２次巻線、C1……コンデン
サ、D1……ダイオード。 Fig. 1 is a circuit diagram showing a conventional example, Fig. 2 is a circuit diagram showing an embodiment of the present invention, Fig. 3 is a voltage waveform diagram for explaining the operation, and Figs. 4 and 5 are respectively for other embodiments. FIG. 2 is a circuit diagram showing an example. E...DC power supply, T...Inverter transformer,
NP 1 , NP 2 ...Primary winding, CH...Chi York, a 1
...Primary winding, a2 ...Secondary winding, C1 ...Capacitor, D1 ...Diode.

Claims (1)

【特許請求の範囲】 １ インバータトランスＴの１次巻線NP1，NP2
の中間タツプt1をチヨークCHを介して直流電源
Ｅの一端に接続すると共に、前記１次巻線NP1，
NP2の各端子を夫々トランジスタTR1，TR2のコ
レクタ、エミツタを介して直流電源Ｅの他端に接
続したトランジスタインバータ回路において、 前記チヨークCHに、コンデンサC1とダイオー
ドD1との直列回路を該ダイオードD1が直流電源
側に位置しかつオン時に直流電源Ｅに逆方向に電
圧を印加するように並列接続し、前記チヨーク
CHに２次巻線a2を設け、該２次巻線a2の一端を
直流電源Ｅの前記チヨークCHとは反対側に接続
すると共に、他端をダイオードD1とコンデンサ
C1との間に接続したことを特徴とするトランジ
スタインバータ回路。[Claims] 1 Primary windings NP 1 , NP 2 of inverter transformer T
The intermediate tap t1 of is connected to one end of the DC power supply E via the chain yoke CH, and the primary winding NP1 ,
In a transistor inverter circuit in which each terminal of NP 2 is connected to the other end of a DC power supply E via the collectors and emitters of transistors TR 1 and TR 2 , respectively, a series circuit of a capacitor C 1 and a diode D 1 is connected to the chain CH. are connected in parallel so that the diode D1 is located on the DC power supply side and applies a voltage in the opposite direction to the DC power supply E when turned on, and the
A secondary winding a 2 is provided on CH, and one end of the secondary winding a 2 is connected to the opposite side of the DC power supply E from the aforementioned CH yoke CH, and the other end is connected to a diode D 1 and a capacitor.
A transistor inverter circuit characterized in that it is connected between C1 and C1 .
JP57044380A 1982-03-18 1982-03-18 Transistor inverter circuit Granted JPS58163277A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57044380A JPS58163277A (en) 1982-03-18 1982-03-18 Transistor inverter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57044380A JPS58163277A (en) 1982-03-18 1982-03-18 Transistor inverter circuit

Publications (2)

Publication Number Publication Date
JPS58163277A JPS58163277A (en) 1983-09-28
JPH0216666B2 true JPH0216666B2 (en) 1990-04-17

Family

ID=12689892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57044380A Granted JPS58163277A (en) 1982-03-18 1982-03-18 Transistor inverter circuit

Country Status (1)

Country Link
JP (1) JPS58163277A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4838429A (en) * 1971-09-17 1973-06-06

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4838429A (en) * 1971-09-17 1973-06-06

Also Published As

Publication number Publication date
JPS58163277A (en) 1983-09-28

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