JPH0216657A - Partial write control system - Google Patents

Abstract

PURPOSE:To reduce the number of access times when writing operations are made several times continuously and to shorten whole processing time by omitting the reading and writing operations at every partial write when specific conditions are satisfied. CONSTITUTION:A partial write control section 1, read data holding buffer 2, and write data holding buffer 3 are provided in a memory controller and 1st and 2nd buffers B1 and B2 for respectively inputting 1st and 2nd write data and their addresses are incorporated in the buffer 3. In addition, a write data checking section 6, address checking section 5, and partial condition discriminating section 7 are provided in the control section 1 and the 1st data and address are tentatively held in the 1st buffer B1. The 2nd data are also tentatively held in the 2nd buffer B2 and the deciding section 7 decides whether or not the 1st and 2nd data are continuous to each other. When the 1st and 2nd data are continuous, an Ecc preparing section 4 puts the data together for writing operations.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Figures 5 to 8) Means for Solving the Problems to be Solved by the Invention (Figure 1) Working Examples (Figures 2 to 4) Effects of the invention [Summary] Regarding the partial write control method, when performing a partial write, compare the previous rewrite data and address so that if it can be continuously rewritten, it can be rewritten at the same time. In a partial write control method that is equipped with a memory controller that reads data from a memory, holds it, and rewrites a part of the data, the read data holding means holds the read data read from the memory. and a write data holding means for holding write data and a write destination address.
A partial write control means is provided to compare addresses.
When the addresses of the previous write data and the next write data are compared and it is determined that the previous write data and the next write data can be written consecutively, the data is rewritten with the same write operation. It is.

[Industrial application field]

The present invention relates to a memory partial write control method,
More specifically, for example, in partial writing of a device that has a memory with check pits such as ECC (error correction code), it is possible to reduce the number of memory accesses by eliminating the need to perform memory access for each partial write. The present invention relates to a memory partial write control method.

[Prior Art] FIGS. 5 to 8 are diagrams for explaining a conventional memory partial write control method, in which FIG. 5 is a system configuration diagram, and FIG. 6 is a memory controller shown in FIG. The detailed drawings in FIG. 7 and FIG. 8 are diagrams showing examples of partial writing.

In FIG. 5, 50 is a central processing unit (hereinafter referred to as CPU), and this CPU 50 is connected via a system bus to a memory controller 51, an input/output device (hereinafter referred to as I10) (1) 53, ■/○ (II )54 etc. are connected.

Further, a memory 52 is connected to the memory controller 51 via a memory bus.

The memory 52 is, for example, a DRAM (dynamic RAM), and the memory controller 5 in this case
1 uses a DRAMC (dynamic RAM controller).

In the memory controller 51, as shown in FIG. 6, a partial write control section 54 and a read data holding buffer 55 are provided.

Now, if the system shown in FIGS. 5 and 6 is
It is a device having a memory with c (error correction code),
Assume that the data has a fixed length of 32 bits.

Partial write control in such a system was performed as follows.

First, when writing from the CPU 50 to the memory 52, Ec
It is necessary to create a checkpit for c.

Therefore, only on the memory bus, the memory controller 5
1 reads 32 bits of data from the memory 52 from the longword boundary address including the address that should originally be written, and then transfers the data to the read data holding buffer 55.
and hold it.

Next, the partial write control unit 54 rewrites the byte position of the data held in the read data holding buffer 55 to be rewritten with the write data of the CPU 50, creates an Ecc check pit with the data, and writes the data to the memory 52. Write to.

In this way, the same operation is repeated for each write to perform a partial write.

FIG. 7 shows an example of a 1-byte partial write to address 1, where (a) is CPU write data, (b) is read from the memory 52, and the read data holding buffer 5
5 shows the data temporarily stored and its Ecc check pit, and (c) shows the new write data and Ecc check bit after correction.

(B) The write data is 1 byte of data "B" at address 1, and (B) 1 byte of data "2" at address 1 of the 32 bits of write data is written as the above data "B."
B''.

As a result, new write data “lB54” like (c)
, create a new Ecc check bit with this data, and write it to the memory 52.

Repeat the same operation below.

FIG. 8 shows an example in which partial writes are performed twice in succession in words (2 bytes, 16 bits).

, First, as shown in FIG. 8(a), each word unit (
The read data in (b) is replaced with the data "AB" of 2 bytes) to obtain the new write data in (c).

Create a new Ecc check bit with this data "AB34" and write the data in c) and the Ecc check bit to the memory.

Next, as shown in (d), the CPU's second write data is the 2-byte, 16-bit data from address 2 "CD".
”.

Read data from memory is already “A” as shown in (e).
334'', so if this is replaced with the data in (d), it becomes “ABCD” as in (f).

Create an Ecc with this data and write it to memory.

The memory controller was performing read and write operations for each write request.

Therefore, when accessing with a longword boundary,
Word (2) accesses that require one long word write
Bytes, 16 bits), the CPU sometimes performed the process in two parts, which resulted in a lot of waste.

For example, in the example shown in FIG. 8, a total of four memory accesses, two reads and two writes, were required, resulting in many wasted accesses.

The present invention has been made to solve these conventional drawbacks, and there are many cases where longword data is written at a longword boundary regardless of the number of times it is written. The purpose is to eliminate access.

[Problems to be Solved by the Invention] The conventional devices as described above have the following drawbacks.

That is, in the conventional partial write method, one time [Means for Solving the Problem] In order to achieve the above object, the present invention is as follows.

FIG. 1 is a diagram showing the principle of a memory partial write control method according to the present invention, and the present invention will be described in detail below based on this diagram.

The first write data and address from the CPU are temporarily held in the write data holding buffer 3, and the second write data is awaited.

At this time, no read or write operations are performed for the first access.

Subsequently, when a second write request is made, the address is compared with the address held in the write data holding buffer 3 from the previous access, and the relationship is checked.

This check checks whether the address is a continuation or not at the first and second times.

Also, when the data width is combined with the data width of the data held in the read data holding buffer 3 from the previous access, it is checked whether the data width is a long word or a long word boundary.

That is, whether the addresses are consecutive and the data has a longword data width (for example, 32 bits), and
Checks whether it is a long word boundary, and if this condition is met, Ecc (
error correction code) and partial write control unit 1
writes directly to memory (no read).

If the above conditions are not met, the data is read and written to the memory during the second write.

At this time, if the first and second data are within the same longword boundary, the two data are replaced and written.

If it is different, replace only the first data and write.
The second data is held as is in the buffer in preparation for the next third access.

[Effect]

With the above configuration, by temporarily holding the first write in the write data holding buffer 3 and waiting for the next write, it is often possible to avoid the need to perform the first read and write as in the conventional method. .

Also, by checking whether the above conditions are met for the second write data and address,
Unlike the conventional method, there is no need to perform the read operation of the second read and write.

〔Example〕

Embodiments of the present invention will be described below based on the drawings. Second
4 to 4 are diagrams for explaining a memory partial write control method, which is an embodiment of the present invention, and FIG. 2 shows an embodiment of the present invention, and shows the main parts in the memory controller. In the block diagram, FIG. 3 is a diagram showing two successive partial writes, and FIG. 4 is a diagram showing a partial write in which the condition is not satisfied.

As shown in FIG. 2, a partial write control section 1, a read data holding buffer 2, and a write data holding buffer 3 are provided in the memory controller.

The write data holding buffer 3 includes a first buffer B for storing the first write data and its address, and a second buffer B2 for storing the second write data and its address. It also has a small amount of

Further, the partial write control section 1 includes a write data check section 6 and an address check section 5 for checking the write data temporarily held in the write data holding buffer 3 and its address. A partial write condition determination section 7 is provided which determines the partial write conditions based on the check data from the address check section 6 and the address check section 5.

Furthermore, an Ecc creation section for creating Ecc bits is installed.

In addition to the above-mentioned functions, the partial write control unit 1 has the same functions as conventional ones, that is, data replacement for partial write, read/write control of the memory bus, and the like.

Figure 3 is an example of performing partial write twice in a row. First, write data for the first time from the CPU (A).
Assume that it is sent as follows.

This is an example of writing 2 bytes of "AB" from address 0, and this data is temporarily held in the first buffer B in the write data holding buffer 3, and its address is also held.

Next, when the second write data as shown in (b) is sent from the CPU, it is temporarily held in buffer B: in the write data holding buffer 3, and its address is also temporarily held at the same time.

These write data and their addresses are checked by a write data check section 6 and an address check section 5 in the partial write control section 1.

As a result, in the example shown in Figure 3, the addresses of the write data are continuous and have a long word boundary, and the data width to be written is a long word (for example, 32 bits).
The partial write condition determining unit 7 determines that a predetermined condition is satisfied.

In the end, the first write data in Figure 3 (a) and (b)
The second write data has consecutive addresses and writes all 32 bits, so when this is judged by the partial write condition judgment unit 7, new write data as shown in (c) is generated. Partial light control unit
Created within.

Furthermore, based on the data in (c), the Ecc creation section goes up and creates an Ecc check pit, which is written to the memory together with the data "ABCD" in (c).

In this way, when writing all 32 bits of data, there is no need to read data from memory, and the CPU
It is possible to write write data directly to memory. Therefore, in this case, the number of accesses may be only once.

FIG. 4 is a diagram showing partial write when the above conditions are not met.

In example (1) where condition is not met, in (a) to (f), first,
As shown in (a), it is assumed that the first write data is 1 byte of data "A" at address O.

This data "A" is temporarily held in the first buffer B+ and waits for the second write data.

The second write data is 1 at address 1, as shown in (c).
This is to write byte data "B".

Therefore, in this case, the above conditions are not met, so read the data from the memory as in (d), replace the above data "A" and "B", and use this new write data as the Ecc Create check bits and write new write data such as (e) and Ecc check bits to memory.

Thereafter, buffers B and B2 are cleared as shown in (to) and wait for the next operation. In this case, the number of accesses to the memory may be two.

In addition, in example (2) where conditions are not met shown in (G) to (E), the first write data is 1 at address 0, as in (G).
Assume that byte data "A" is to be written.

Put this data into the first buffer B1 (ch),
Wait for next write data.

Assuming that the second write data is 1-byte data "F" at address 6 as in (1), it is held in the second buffer B2 for -1 time, and as a result of the determination by the partial write condition determination unit 7, Naturally, it is determined that the condition is not satisfied.

Therefore, in this case, 4 bytes (32 bits) are read from address 0 as shown in (N) and are temporarily held in the read data holding buffer 2.

This read data is then replaced with the first write data, a check pit is created based on this data, and it is written to the memory.

Next, the first buffer B+ is cleared, the second buffer B2 is held as it is (O), and the third write data is waited for.

Thereafter, the same operation is repeated in the same manner.

Note that although the above description is an example of a unit of 4 bytes (32 bits), the present invention is of course not limited to this.

〔Effect of the invention〕

As explained above, the present invention has the following effects.

That is, if a predetermined condition is satisfied, it is not necessary to read and write for each partial write, so the number of accesses when a write operation is performed several times in succession can be reduced.

In addition, the number of accesses to the memory is reduced (this has the effect of shortening the overall processing time).

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is a configuration diagram of an embodiment of the invention, Figs. 3 and 4 are explanatory diagrams of the operation of the invention, and Fig. 5 is a system configuration diagram of a data processing device. , FIG. 6 is an explanatory diagram of a conventional memory controller, and FIGS. 7 and 8 are explanatory diagrams of a conventional partial write. 4...Ecc check bit creation -5-Access check section 6--Write data check section 7--Partial write condition determination section

Claims (1)

[Claims] (1) In a partial write control method equipped with a memory controller that reads data from a memory, holds it, and rewrites a part of the data, the memory controller is provided with read data holding means (2) that holds read data read from the memory. ), write data holding means (3) that holds write data and write destination address, and partial write control means (1) that compares addresses, and compares the addresses of the previous write data and the next write data. A partial write control method characterized in that when it is determined that previous write data and next write data can be written consecutively, the data are rewritten in the same write operation.