JPH02165193A - Display circuit - Google Patents

Abstract

PURPOSE:To contrive the decrease of a program burden by presetting data for showing a position for displaying a cursor to a cursor address register by a CPU, and also, setting a kind of the cursor display to a mode control register. CONSTITUTION:The circuit is provided with a cursor address register 18, a coincidence detecting circuit 19 for detecting a fact that values of this cursor address register and an address counter 17 coincide with each other, and a mode control register 8 to which a display mode of a cursor is set. That is, a kind of the cursor is set to the mode control register 8, and data for showing a position for displaying the cursor is set to the cursor address register, by which when each common line is selected, the corresponding dot pattern data is outputted from a character generator, but when the contents of the address counter and the cursor address register coincide with each other, a cursor generating circuit is controlled, based on a detection output of the coincidence detecting circuit 19 and an output of the mode control register 8. In such a way, a program burden of a microcomputer is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a display circuit for displaying characters, numbers, symbols, etc. on a dot matrix display device, and in particular,
Related to a display circuit built into a one-chip micro combi coater.

(b) Prior Art Conventionally, one-chip microcomputers with a built-in display circuit capable of directly driving a dot matrix type liquid crystal display device have been developed as one of the additional functions of one-chip microcomputers.

This display circuit includes a display RAM in which a hood representing letters, numbers, or symbols, etc. is stored, and a code read from the display RAM as an address to display letters, numbers, or symbols according to the code. a character generator that generates dot pattern data, a shift register that sends the dot pattern data output from the character generator to a display drive circuit, and a display R
It is composed of a control circuit that controls AM readout, character generator readout, and operation of the display drive circuit.

Normally, a dot matrix type liquid crystal display device displays a - character with 5 x 7 dots, so 7
A common line for the book and 7XN (N is the number of displayed characters) segment lines are provided. Therefore, when driving this liquid crystal display device with the above display circuit, in order to obtain dot pattern data to be displayed on the selected common line,
The display RAM is accessed, the code of the character, number, or symbol to be displayed is read out, and the dot pattern data corresponding to the common line to be selected is output from the character generator accessed by the code to the shift register, and then the dot pattern data corresponding to the common line to be selected is output from the shift register. Transfer to the liquid crystal drive circuit.

By performing this operation as many times as the number of characters to display,
A dot pattern for the common line to be selected is obtained. Furthermore, the display is completed by repeating the same operation for each line.

(8) Problem to be solved by the invention When attempting to display a cursor in the above display circuit, it is necessary to use a display device with 8 common lines provided with a cursor line, but the display circuit The operation content must be changed depending on the 8 common line display device.

Therefore, the design of the control circuit that controls the read timing of the display RAM and character generator must be changed. Also, in the operation of the display circuit, when the common line on which the cursor is displayed is selected, the display R
Rewrite the AM letters, numbers, symbols, etc. code,
You must write the code that indicates the cursor at the address that corresponds to the position where the cursor will be displayed. Alternatively, it is necessary to provide an address area for storing codes indicating a cursor in a number equal to the number of characters to be displayed in the display RAM, and write a code indicating an address number cursor corresponding to the cursor position in the address area. Also, when the common line to display the cursor is selected, the display RA
The hood indicating the cursor must be read from M, and the dot pattern data for displaying the cursor must be obtained from the character generator.

Therefore, it is necessary to expand the address area of the display RAM and the character generator, and there is also the problem that the program load on the microcomputer increases.

(d) Means for Solving the Problems The present invention has been made in view of the above points, and includes a display RAM, an address counter for specifying an address of the display RAM, a character generator, and a shift register. In the display circuit, there is a cursor address register in which cursor address data indicating the position to display the cursor is set, a match detection circuit that detects when the values of the cursor address register and address counter match, and a cursor display mode is set. The dot pattern data read from the character generator is inverted or predetermined dot pattern data is created based on the mode control register, the detection output of the match detection circuit, and the control signal of the mode control register. The cursor can be automatically displayed by providing a cursor generating circuit for holding the cursor.

(*) Effect According to the above means, by setting the type of cursor in the mode control register and setting data indicating the position to display the cursor in the cursor address register, when each common line is selected, The address counter sequentially accesses the display RAM, and the character generator outputs dot pattern data corresponding to the common line selected by the read hood, but when the contents of the address counter and the cursor address register match, the match detection circuit The cursor generation circuit is controlled based on the detection output of and the output of the mode control register. especially,
In a mode in which characters are displayed in a single line by inverting them, when each common line is selected, the dot pattern data output from the character generator is inverted and output to the shift register according to the detection output. In addition, in a mode in which a cursor is displayed below a character, when that common line is selected, dot pattern data of the cursor is output to the register based on the detection output.

As a result, a cursor can be displayed using the reversed characters or the line displayed below the characters.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. (not shown) can store up to 40 characters of codes such as letters, numbers, or symbols.
In addition, in the graphic mode, writing and reading of the 0 display RAM (1), which can store up to 320 dots of display data for instructing dots to turn on and off, can be performed by a CPU (not shown); This can also be done by the display control circuit (2) independently of the CPU. (3) is an 8-bit latch circuit that holds data read out from the display RAM (1). (4) is a ROM for the character generator. In the case of character mode, the ROM (4) for the character generator is addressed by a hood indicating letters, numbers, or symbols held in the latch circuit (3). Outputs dot pattern data for displaying letters, numbers, symbols, etc. The character patterns stored in this character generator ROM (4) can be set by the user using mask options, and up to 16 arbitrary patterns of character fonts of 5 dots horizontally x 7 dots vertically can be set.
0 types can be set. (5) is a switching gate, which connects the output of the latch circuit (3) and the character generator RO
The output of M(4) is selected and outputted by the mode selection signal C/G. (6) is a cursor display circuit that generates dot pattern data according to the type of cursor in the character mode. This cursor display circuit (6) will be explained in detail later. (7) is a shift register that serially transfers dot pattern data to a drive circuit (not shown) of a dot matrix display device. <8) is a mode control register, in which data for switching between character mode and graphic mode and data indicating the type of cursor are set in advance.

The display control circuit (2) includes a counter (9) that counts the number of horizontal dots for - characters, and a counter (9) that counts borrow signals of the counter (9) and counts the number of displayed characters for - lines.
10) and the borrow signal of the counter (10),
- A counter (11) that counts the number of dots in the vertical direction of characters, a counter (12) that counts the number of drive lines of the dot matrix display device, and each counter (9) (10) (11).
) Registers (13) (14) (15) (16) that hold the predetermined value in order to set the value in <12>.
) and an address counter (17) of the display RAM (1) that counts up in response to a borrow signal from the counter (10). The counter (9) is a shift register (7).
) are counted, and the output pulses RPC3 to HPCO output from the counter (9) based on the counted value are used as operation timing signals for each circuit.

For example, as shown in FIG. 2, when 8 characters are displayed on a dot matrix display device with 5 horizontal dots and 7 vertical dots and 8 lines, "5" is displayed in the register (13), and "5" is displayed in the register (13).
14), "81" in register (15), "7" in register (16), and "8." in register (16) are preset by the CPU in advance.Of course, the address counter (17) is reset. That is, this initial state is , line L1 in Fig. 2
This is the state for displaying. clock pulse CLK
is applied, the counter (9) counts down, and when the signal HPC3 is outputted when the count value reaches "r4", the address of the display RAM < 1) specified by the contents of the address counter (17) , that is, address "0" is accessed. The code read by this access is latched into the latch circuit (3) by the fall of the signal HPC3. In the character mode, when the signal HPC2 is output from the counter (9), the character generator ROM (4) is accessed using the code latched by the latch circuit (3) and the contents of the counter (11) as an address. That is, the code can be letters, numbers,
Alternatively, a symbol or the like is designated, and the counter (11) designates a dot pattern line of that letter, number, symbol, or the like. Dot pattern data read out from the character generator ROM (4) (in this case, line Ll)
) is connected to the cursor display circuit (6) via the switching gate (5).
) is output. When the cursor display circuit (6) is not in the cursor display mode, the cursor display circuit (6) transfers the dot pattern data as is to the shift register (7). Then, when the count value of the counter (9) becomes "0" and a borrow signal, that is, HPCO is output, the dot pattern data is held in the shift register (7) by the HPCO, and this dot pattern data is used for the next The signals are sequentially shifted to the display drive circuit by the clock CLK for the character read operation. Furthermore, when the above-mentioned HPCO occurs, the counter (10) counts down, the address counter (17) increments, and the register (1
3) The content that can be retained is preset. Thereafter, by the same operation as described above, the dot pattern data on line L1 is completely read out and output from the shift register (7). Then, when the scanning of the - line is completed, the counter (10
), the address counter (17) is reset, the counter (10) is preset with the contents held in the register (14), and further,
The counters (11) and (12) can count down. That is, as the counter (12) counts down, the next "in L2" is scanned. Then, when the scanning of the line L7 is completed, the counter (11) has finished counting down and the count value becomes "0". So, this “0
'', the counting operation of the counter (11) and the reading operation of the display RAM (1) and character generator ROM (4) are prohibited. At this time, the counter (12) is set to "1", that is, the content designates line L8, and when scanning line L8, all dot pattern data output from the shift register (7) becomes "0". When a borrow signal is output from the counter (12), the contents held in the register (15) are preset to the counter (11>) and the contents held in the register (16) are preset to the counter (11>).
The contents held in the counter (12) are preset to the counter (12), and the line L1 returns to its initial state.

Therefore, the registers (13) (14) of the display control circuit (2)
) (15) and (16) can be easily adapted to various dot matrix display devices by changing the contents set in (16) according to the character font of the character generator ROM (4).

Next, the cursor display circuit (6) will be explained. The cursor display circuit (6) includes a cursor address register (tS) in which data indicating the display position of the cursor is preset.
), a coincidence detection circuit (19) that detects a coincidence between the contents of the cursor address register (18) and the address counter (17), a detection output Cow of the coincidence detection circuit (19), and a mode control register (8). ) and a cursor generation circuit (20) controlled by the cursor generating circuit (20).

That is, the cursor address register (18), like the address counter (17), can be set to a value from 1 to 40, and the cursor address register (18) and address counter (17) match each line. L1~L8
, the type of cursor display set in the mode control register (8), which is once, is below the displayed character.
That is, there are underline display in which an underline is displayed on line L8, inversion display in which the character at the cursor position is inverted, and flashing display in which the underline display is blinked. For this purpose, the cursor generation circuit (20)
Signal S Is detection output C indicating underline display from mode control register (8).

ml, an AND gate (21) to which a signal "1" is applied when the counter (12) becomes "1", that is, when line L8 is fully selected, and a mode control register (8).
An AND gate (22) to which a signal S indicating an inverted display of , and a detection output Cof11 are applied, a signal S indicating a blinking underline, and a pulse corresponding to the blinking period are applied, and the output is an AND gate (21). 8 E-OR gates (24) that input each bit of the 8 bits output from the switching gate (5) and are controlled by the output of the AND gate (22). and an OR gate (25) which inputs the output of each E-OR gate (24), can be commonly controlled by the output of the AND gate (21), and whose output is applied to the shift register (7). configured.

In this cursor display circuit (6), when inverted display is selected, the signal S is at the "1" level. In each line L1 to L8, if the address counter (17) does not match the contents set in the cursor address register (18), the outputs of the AND gates (21) and (22) are "0" level. Therefore, the dot pattern data read from the character generator ROM (4) is directly transmitted to the E-OR gate (24) and the OR gate (24).
25) to the shift register (7). On the other hand, when the address counter (17) reaches a value that matches the value stored in the cursor address register (18), the detection output of the negative output circuit (19) becomes "1" level, so the AN
The output of the D gate (22) becomes the "al" level. As a result, the dot pattern data read from the character generator ROM (5) is output to the E-OR gate (24).
) and applied to the shift register (7) via the OR gate (25). Therefore, the character at the display position set in the cursor address register (18) is reversed.

Additionally, when the signal SI that instructs underline display reaches the 1" level, the counters (
Since the output “1” of 12) is at the “0” level, the AND
The output of the gate (21) is at the 0" level. Therefore, when scanning lines L1 to L7, even if the detection output Cow from the output circuit (19) reaches the 1" level, the character generator ROM ( The dot pattern data read from 4) is directly applied to the shift register (7). Then, when the line L8 is selected, the output "1" of the counter (12) becomes the "1" level, so the output of the AND gate (21) becomes the "1" level, and the output of the OR gate (25) becomes the "1" level. Output is “1” in all bits
” level. Therefore, when line L8 is selected, an underline will be displayed on line L8 at the display position set in the cursor register (18). In this case, the underline will not blink. an instruction signal S,
is at the "0" level, so the output of the NAND gate (23) is at the "1" level.

When the signal S, which instructs the blinking of the underline, is set to the "1" level while the signal SI is at the "1" level, the NAND gate (23) is activated at the cycle of the blinking period signal input to the NAND gate (23). Since the output is at the "0" level and the 41" level, the underline blinks.

When the cursor is not displayed, the signal sI is set depending on the contents set in the mode control register (8).

S=, Ss may be set to 0'' level.

(G) Effects of the Invention As described above, according to the present invention, data indicating the position to display the cursor is stored in the cursor address register (18) by the CP.
By presetting by U and setting the type of cursor display in the mode control register (8), it is possible to reduce the program load. Furthermore, display RAM (1) and character generator ROM (4)
There is an advantage that there is no need to provide an address setting area for the cursor in >.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing dots in a dot matrix. (1>...Display RAM, (2)...Display control circuit, (3)...Latch circuit, (4)...Character generator ROM, (5)...Switching gate, (
6)...Cursor display circuit, (7)...Shift register, (8)...Mode control register.

Claims (2)

[Claims] (1) A display RAM that stores at least a code representing a letter, number, symbol, etc., an address counter that specifies the address of the display RAM, and a code read from the display RAM that corresponds to the code as an address. a character generator that generates dot pattern data for displaying letters, numbers, symbols, etc.;
A display circuit including a shift register that holds dot pattern data output from the character generator and outputs it to a drive circuit of a display device, comprising: a cursor address register in which cursor address data indicating a position to display a cursor is set; a coincidence detection circuit that detects that the values of the cursor address register and the address counter match; a mode control register that sets a cursor display mode; and a detection output of the coincidence detection circuit and a control signal of the mode control register. Inverting the dot pattern data based on
Alternatively, the display circuit includes a cursor generation circuit that creates predetermined dot pattern data and causes the shift register to hold the data. (2) The display mode of the cursor includes a first mode in which characters are inverted, a second mode in which a line is displayed under the characters, and a third mode in which the line displayed under the characters is blinked, The cursor generation circuit includes a first gate circuit that is controlled in the first mode and inverts dot pattern data, a second gate circuit that is controlled in the second mode and generates predetermined data, and a second gate circuit that is controlled in the second mode and generates predetermined data. 2. The display circuit according to claim 1, further comprising a third gate circuit which is controlled and inhibits generation of the predetermined data at predetermined intervals.