KR0150130B1 - Line unit display shift device in a lcd controller for charactor - Google Patents

Abstract

The present invention relates to a line-by-line display shift device of an LCD controller for a character, and is configured as an up / down counter utilizing a register that specifies a start pointer value of a scan counter for reading DDRAM data. By selecting only the lines, DDRAM can be used efficiently, and various functions can be implemented in the LCD display.

Description

Line-by-line display shift device for character controller

(A) and (b) of FIG. 1 are exemplary diagrams for displaying lines of a conventional LCD controller for characters.

(C) of FIG. 1 is a block diagram of a display line for a conventional LCD controller for characters.

2 is an exemplary view for each line of the LCD controller for characters according to the present invention,

3 is a block diagram of the display circuit for each character of the LCD controller for characters according to an embodiment of the present invention,

4 is an operating waveform diagram of FIG.

5 is a detailed internal circuit diagram of the start pointer register of FIG.

(A)-(d) of FIG. 6 are relationship diagrams of the main counter value and the LCD screen according to each case of the present invention.

* Explanation of symbols for main parts of the drawings

10: combination circuit

20: start pointer register section

21,22: Start pointer register 211,213: latch circuit

212 control circuit 30 control device for the select line

40: main counter 50: DDRAM (Display Data Ram)

The present invention relates to a line-by-line display shift device of an LCD controller for characters, and more specifically, to an LCD controller for a character that enables characters to be moved only in a line to be moved when performing a character shift command for viewing invisible characters on the LCD display device. Relates to a line-by-line display shift device.

The conventional LCD controller for characters stores a total of 80 characters to display in a DDRAM (Display Data Ram). When the user writes the character to display (address of ROM FONT, 41H (hex) for A letter) to DDRAM, the scan counter periodically reads DDRAM data, which is the address of ROM, and then saves the data through ROM To display the characters on the LCD screen.

In order to take advantage of set space, an LCD module is widely used to display small characters such as 8, 12, 20, and 24 characters. In the case of displaying a small amount of characters in this way, the user can select from 8 characters, 12 characters,..., Depending on the type of each module. … 72 characters, 68 characters which are invisible because we see only… … You can see all 80 characters by executing the display shift right_left command to see the characters of.

Referring to the accompanying drawings, the line-by-line display shift function of the conventional LCD controller is as follows.

(A) and (b) of FIG. 1 are exemplary diagrams of a module displaying a conventional two-line twelve characters line by line.

As shown in FIG. 1, since the module shown in (a) is a two-line module of 12 characters, characters 13 through 40 and 53 through 80 of each line do not appear on the LCD screen.

Therefore, in order to see the characters written on the second line, the display shift left command must be executed six times as shown in (b) of FIG. 1 so that the remaining characters of the two lines can be seen.

In other words, when the IC (IC) that is actually viewing the LCD has a total of two lines of 40 characters, the size of the LCD can only display two lines of 12 characters as shown in (a) of FIG. You will see the hidden characters through.

Here, (c) of FIG. 1 relates to a conventional LCD display, and implements a line-by-line display shift device of an LCD controller for a character in a 16 COM, 2-line module. The configuration consists of a scan counter 4 which sequentially performs 7-bit up counting and outputs a address value and a DDRAM 5 which is sequentially scanned from the beginning by the address output from the scan counter 4. Here, since the scan counter 4 is a simple counter which operates in cycles in synchronization with a clock, the first and second lines commonly connected to the output of the simple scan counter are simultaneously shifted so that when the user displays a message in FIG. As in b), the first and second lines are moved simultaneously.

Therefore, a disadvantage of the conventional shift method is that one-line and two-line characters are shifted simultaneously regardless of the user's will.

That is, in the case of 4-line module, if the shift command is executed to see the invisible characters, the character shift is made from 1 line to 4 lines at the same time, and the character is moved to the line that you do not want to move. Occurs.

Therefore, when a user wants to see an invisible character through the display shift, it is inconvenient to carry out the shift command with the mind that the display state of the other line is also changed.

Therefore, an object of the present invention is to solve the above disadvantages, and in the present invention, a circuit is provided so that only a predetermined line can be moved to a light or left during display shift as illustrated in FIG. To provide.

2 shows a display shift left six times without enabling one line (L1 = 0) and enabling only two lines (L2 = 1) through a microcomputer command to view two invisible characters. It shows an example in which only one line, which is the title, is moved, not the first line, which is the title. The line enable setting command utilizes the existing Don't Care bit to create the L1, L2, L3, and L4 bits for the 2 lines and the L1, L2, L3, and L4 bits for the 4 lines to enable the shift command. Specify each.

A configuration of the present invention for achieving the above object comprises: a combination circuit for receiving a plurality of line selection signals and a plurality of shift signal inputs and performing a negative AND to output a plurality of enable signals; A start pointer register unit which operates as the enable signal of the combination circuit and receives an initial address setting signal and a write_left selection signal as inputs and newly calculates and outputs a start address of a line; The plurality of start addresses are inputted from the start pointer register unit, and a start address corresponding to the currently displayed line is selected from the start pointer register according to a block selection signal indicating a line currently displayed. A select circuit; The start address of the select circuit is input in the start pointer register section of the scan_start pointer register signal in synchronization with a clock signal, and 7-bit up counting is sequentially performed from the start address in the scan section of the scan start pointer register signal. A main counter configured to output a street address; It consists of DDRAM which is sequentially scanned from the beginning by the address output from the main counter.

In this case, the combination circuit includes a plurality of negative AND products which input one of a plurality of line selection signals, receive a shift signal as a common input, and perform negative AND to output.

In addition, the configuration of the start pointer register unit includes one of the outputs of the plurality of negative AND products as an input, and receives an initial address setting signal and a write_left selection signal as a common input to generate a start address of a line. It consists of a number of start pointer registers to output.

The specific internal circuit configuration of the start pointer register is composed of a latch means for temporarily storing 1-bit information and a control circuit for controlling the enable signal, the write_left select signal, and the initial address setting signal input. Specifically, first latch means for receiving the outputs of the clock 1 and the second latch means as inputs, temporarily storing one bit of information and outputting the information; A control circuit which receives an output of the first latch means, an enable signal, a write_left selection signal, and an initial address setting signal as inputs and controls an operation according to each signal; A second latch means for receiving the output of the combination circuit and the clock 2 as an input, temporarily storing one bit of information and outputting the information.

The configuration of the control circuit includes: first exclusive OR means for receiving an output of the first latch means and an enable signal as an input, performing an exclusive OR, and outputting a value; Second exclusive OR means for receiving an output of the first latch means and a write_left selection signal as an input and performing an exclusive OR; Logical multiplication means for receiving the output of the second exclusive OR means and an enable signal as an input, performing a logical multiplication, and outputting a value; First negative logic OR means for receiving an input from the output of the first exclusive OR and initial signal and performing a negative AND to output a value; And a second negative logic sum means for receiving a reset input from the output of the negative logic sum means and the initial signal, and performing a negative logic sum to output a value.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

3 is an embodiment of the present invention, which implements a line-by-line display shift device of an LCD controller for a character in a 16 COM, 2-line module.

As shown in FIG. 3, the configuration of the line-by-line display shift device of the character LCD controller includes a combination circuit 10 that receives line selection signals L1 and L2 and a shift signal input and performs a negative logical product to output the result. Wow; A start pointer register section 20 which receives the output of the combination circuit 10, an initial address setting signal, and a write_left selection signal as inputs and generates and outputs a start address of a line; A selector 30 which receives two inputs from the start pointer register section 20 and a block A_B selection signal as inputs, selects one of two inputs from the start pointer register according to the block A_B selection signal, and outputs a value thereof. )Wow; A main counter 40 which receives the output of the selector 30, a clock signal, and a scan_start pointer register signal as inputs, sequentially performs 7-bit up counting, and outputs a address value; A total of 80 addresses (00H to 27H, 40H to 67H) are sequentially scanned from the beginning by the address output from the main counter 40, and the DDRAM 50 is scanned.

In this case, the combination circuit 10 includes two NAND gates each having one of two line selection signals L1 and L2 as inputs, and receiving a shift signal as a common input and performing an AND logic to output the result.

In addition, the start pointer register unit 20 is configured by inputting one of the outputs from the two NAND gates as an input, and receiving an initial address setting signal and a write_left selection signal as a common input. It consists of two start pointer registers 21 and 22 which generate and output.

In addition, according to an embodiment of the present invention, the configuration of the specific internal circuit of the start pointer register 21 is shown in FIG. 5, and the internal circuit configuration of the illustrated start pointer register is a total of seven cells having the same configuration. One cell is implemented.

As shown in FIG. 5, the specific internal circuit configuration of the start pointer register 21 controls two latch circuits for temporarily storing 1-bit information, an enable signal, a write_left selection signal, and an initial address setting signal input. A first latch circuit 211 which receives the outputs of the clock 1 and the latch circuit 2 213 as inputs, temporarily stores one bit of information, and outputs the information; A control circuit 212 which receives an output of the first latch circuit 211 and an enable signal, a write_left selection signal, and an initial address setting signal as inputs and controls an operation according to each signal; The second latch circuit 213 receives the output of the control circuit 212 and the clock 2 as an input, temporarily stores one bit of information, and outputs the information.

The configuration of the control circuit 212 may include an exclusive OR gate EX-OR1 that receives an output of the first latch circuit 211 and an enable signal as an input, performs an exclusive OR, and outputs a value; An exclusive OR gate EX-OR2 that receives the output of the latch circuit 1211 and the write_left select signal as an input and performs an exclusive OR; An AND gate AG which receives the output of the exclusive OR gate EX-OR2 and an enable signal as an input, performs an AND, and outputs a value; A NOR gate NOR1 that receives an input from the output of the exclusive OR gate EX-OR1 and an initial signal, performs a negative OR, and outputs a value; The NOR gate NOR2 receives a reset input from the output of the NOR gate 1 and the initial signal and performs a negative logic sum to output a value.

In the present invention, the main counter 40 of FIG. 3 is a 7-bit up counter which is sequentially counted up in synchronization with the clock signal CLOCK. The scan start pointer register signal (SCAN_SPR) is a signal corresponding to the one-com period of the start of a line when counting from the line counter to COM1 to COM16. Here, the first line is displayed when counting from COM1 to COM8, and the second line is displayed when counting from COM9 to COM16. The block AB signal (BLOCK A_B) is a signal representing the line currently being displayed as shown in FIG. 4 to select either the first start pointer register 21 or the second start pointer register 22 at the start pointer register time. do.

The operation of the line-by-line display shift device of the character LCD controller according to the embodiment of the present invention by the above configuration will be described with reference to the accompanying drawings.

As shown in FIG. 4, the main counter 40 keeps counting up in synchronization with the clock CLOCK at the scan time SCAN, and then the start pointer whose scan start pointer register signal SCAN_SPR is low. At the register time SPR, the value of the main counter 40 is forcibly set to SPR0: 6, which is a start pointer register value. That is, the main counter 40 is initially set to the start pointer register value and continues counting up to scan all the DDRAMs 50 corresponding to one line, and then resets to SPR0: 6 when the start pointer register time is reached again. The next line will be scanned.

Therefore, the main counter 40 counts periodically from the initial value designated by the start pointer register 20 to the moment designated again. The period of the main counter 40 is determined by the scan start pointer register signal SCAN_SPR, which corresponds to the one-combe displayed one row, and the counting value is adjusted by the start pointer register 20. The first start pointer register 21 of the start pointer register section 20 of FIG. 3 stores the starting point of the COM1 to COM8 blocks (A blocks) corresponding to one line, and the second start pointer register 22 is two lines. The starting point of the corresponding COM9 to COM16 block (B block) is stored.

The operation of the first start pointer register 21 and the second start pointer register 22

As shown in FIG. 5, the enable and write / left signals Right_Left are 7-bit registers having a function of decreasing -1 at shift write and +1 at shift left. The start pointer register is initialized to 00H address and the second start pointer register 22 to 40H address by an initial signal.

As shown in FIG. 3, the line select signals L1 and L2 are signals indicating the line shift enable state at the time of display shift, and are set to high / low by a command of the microcomputer. The shift signal Shift is enabled high during the display shift command. If one line is enabled according to the state of the line select signals L1 and L2, the first start pointer register 21 is enabled and the shift signal Shift is enabled. The one-start pointer register 21 is operated to be +1 or -1 depending on the write / left signal.

6A shows that in the initial state in which the user does not shift, the right_left signal Right_Left and the shift signal Shift are not input, and the respective line enable signals L1 and L2 are not input. ) Is not input from the microcomputer. Therefore, the first start pointer register 21 and the second start pointer register 22 are set to 00H and 40H as initial addresses of the respective lines by the initial address setting signal Initial. Here, the block AB signal BLOCK A_B includes two initial addresses (the output values of the SPRA 21 and the SPRB 22 inputted by the select unit 30 from the scan pointer register unit 20 at COM1 to COM8 indicating each first line). ) Outputs the output value of the first start pointer register 21 corresponding to the first line to the main counter 40 (SPR0: 6). Accordingly, the main counter receives an initial address SPR0: 6 during the SPR period of the scan start pointer register SCAN_SPR and counts the SCAN period in the SCAN period and outputs the count to the DDRAM (SPR0: 6).

Next, as shown in (b) of FIG. 6, the user shifts the second line to the left. At this time, the microcomputer outputs the values L1 = 0 and L2 = 1 to the combination circuit 10 and shifts the shift signal, The write_left signal Right_Left is input to the start pointer register unit 20. The second negative AND of the combination circuit unit 10 enables the second start pointer register 22 of the start pointer register unit 20 to perform a new start address (+1) at the initial address 40H. 41H) is output to the select unit 30. Here, the selector 30 is the initial address 00H of the first start pointer register 21 when the scan start pointer register SCAN_SPR is an SPR interval in COM1 to COM8 where the block AB signal BLOCK A_B indicates the first line. Is output to the main counter 40H, and the newly calculated second start pointer register 22 when the scan start pointer register SCAN_SPR is in the SPR section at COM9 to COM16 where the block AB signal BLOCK A_B points to the second line. Start address of the output to the main counter (40). The main counter 40 is displayed in the shifted state of only the second line shifted by the user by counting from the start addresses 00H and 41H received when the scan start pointer register SCAN_SPR is in the SCAN period.

In the case of (c) of FIG. 6, the first line is shifted to the right in (a) of FIG. 6, and the basic operation is the same as in the case of (b) of FIG. The first start pointer register 21 is -1 at the initial address (00H) by the write_left signal (Right_Left) to be outputted as) so that the last address 27H is newly reset to the start address. Here, the shift method of DDRAM is a circular arrangement.

In the case of (d) of FIG. 6, the first and second lines are shifted to the left in FIG.

Therefore, the effect of the present invention operating as described above is that the user can shift all the lines when performing the display shift command or only the specified specific lines, so that not only 80 DDRAMs can be efficiently used, but also the LCD display device. Various display functions can be implemented. In particular, in the case of four lines, this function can be used to allocate a unique display area to each line and to display a large amount of data in a multifunctional manner through the display shift using this function.

Claims (12)

A combination circuit for receiving a plurality of line selection signals and a plurality of shift input signals and performing a negative AND to output a plurality of enable signals; A start pointer register unit which operates as the enable signal of the combination circuit and receives an initial address setting signal and a write_left selection signal as inputs and newly calculates and outputs a start address of a line; Selecting and outputting a start address corresponding to the currently displayed line from the plurality of start addresses from the start pointer register according to a block selection signal indicating a plurality of start addresses received from the start pointer register; A select circuit; The start address of the select circuit is input in the start pointer register section of the scan_start pointer register signal in synchronization with a clock signal, and 7-bit up counting is performed sequentially from the start address in the scan section of the scan_start pointer register signal. A main counter for outputting a street address; Display shift device for each character line of the LCD controller for character characterized in that consisting of DDRAM sequentially scanning from the beginning by the address output from the main counter. The display shift of each character line of the character LCD controller of claim 1, wherein the combination circuit receives a line selection signal for each of the plurality of lines from the microcomputer when the shifting operation of a specific line is performed among the plurality of lines. Device. The start pointer register unit of claim 1, wherein the start pointer register unit receives an output of a plurality of negative AND products in the combination circuit, receives an initial address setting signal, a write_left selection signal, and generates a start address of a line. And a plurality of start pointer registers to be outputted. The method of claim 1, wherein the main counter comprises a counter circuit device that counts periodically from one starting point to the next starting point, and adjusts the starting point of each of the other devices arbitrarily, and selects one according to the case. Line-by-line display shifting device of character LCD controller for character. 3. The circuit according to claim 2, wherein the circuit having a function of selecting only a specific line is a plurality of negative AND products for inputting one of a plurality of line selection signals and receiving a shift signal as a common input and performing an AND logic to output the result. Display shift device for each line of the LCD controller for characters, characterized in that consisting of. The display shift for each character line of the character controller of the character controller according to claim 3, wherein the start pointer register comprises a register which designates a start address of a line so that only a specific specified line is shifted in a display shift write_left command. Device. 6. The method of claim 5, wherein the plurality of negative AND products comprises a plurality of NAND gates each inputting one of a plurality of line selection signals and receiving a shift signal as a common input and performing an AND logical output. Display shift device for each line of LCD controller for character. 7. The register of claim 6, wherein the register designating the start address of the line comprises: latch means (211, 213) for temporarily storing one bit of information until a new input value is received, an enable signal, a write_left select signal, And a control circuit 212 for controlling the initial address setting signal input. In more detail, the output of the clock 1 and the second latch means 213 is received as an input, and temporarily stores 1-bit information. First latch means 211 for outputting the information at the same time; A control circuit 212 which receives the output of the first latch means 211 and an enable signal, a write_left selection signal, and an initial address setting signal as inputs and controls an operation according to each signal; Line-by-line character character controller comprising a second latch means 213 for receiving the output of the control circuit 212 and the clock 2 as an input, and temporarily storing one-bit information and outputting the information. Display shift device. The first exclusive OR unit EX-OR1 of claim 8, wherein the control circuit 212 receives an output of the first latch circuit 211 and an enable signal as an input and performs an exclusive OR to output a value. and; Second exclusive OR means EX-OR2 that receives the output of the first latch circuit 211 and the write_left selection signal as an input and performs an exclusive OR; Logical multiplication means (AG) for receiving the output of the second exclusive logical OR means (EX-OR2) and the enable signal as an input and performing a logical multiplication to output a value; First negative logical OR means (NOR1) receiving a set input from the output of the first exclusive logical OR means (EX-OR1) and performing a negative OR to receive a set input from the initial signal; An LCD controller for a character comprising: an output of the first negative OR unit and a second negative OR unit NOR2 that receives a reset input from an initial signal and performs a negative OR to output a value; Line-by-line display shift device. 10. The line-by-line display shift device of claim 9, wherein the exclusive OR means comprises an exclusive OR gate. 10. The display shift device for each line of an LCD controller for a character according to claim 9, wherein the logical AND means comprises an AND gate. 10. The line-by-line display shifting device of a character LCD controller for character characterization according to claim 9, wherein the negative OR means comprises a NOR gate.