JPH0216476B2 - - Google Patents

Abstract

PURPOSE:To edit voice information to be stored fast by assigning addresses and storing the voice information successively into an RAM. CONSTITUTION:When a write switch of a switch part 16 is operated, a recording state is set. When voice is inputted from a microphone 24 in this state, it is A/D converted 25, is encoded 21, and is stored in an RAM19. At this time, the address of the RAM19 fed from an address part is displayed in a display part 14. To edit the voice information stored in the RAM19, a mode select switch and a run switch are operated to feed clock selection signals for fast feed to a clock selecting part 17. The address assignment signal of the address part 18 is fast fed to assign the addresses of the RAM19. When the address displayed in the part 14 assumes a desired value, the run swith is stopped, and again the mode select switch is operated to write the voice information of the assigned address in a temporary storage part 20, and is transferred to the RAM19 of the assigned address.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic device with a recording function capable of digitally recording audio and the like.

2. Description of the Related Art Conventionally, it has been considered to link an electronic device such as an electronic clock and a recording device such as a tape recorder to output a melody at an alarm time and a sound indicating what is scheduled for that alarm time. It has not been possible to provide such a function to small electronic devices such as electronic wristwatches or small electronic calculators such as electronic desktop calculators because the size of the devices would increase. Also, if you record multiple combinations of melodies and words announcing business (meetings, going out, etc.) as the recording content to notify at alarm times, you can record the corresponding business audibly in response to multiple alarm times. In addition to the notification, it is also possible to make a melody sound before and after the audio notification. However, when recording melodies and business matters on a tape recorder, the melodies and business matters must be recorded in the order in which they are broadcast, and when multiple tape recorders are used, editing work must be performed.
The drawback was that the work was cumbersome and time-consuming.

This invention was made in view of the above points,
The purpose is to miniaturize the storage device that stores melodies and business matters (meetings, going out, etc.) that are announced at alarm time, and to develop electronic equipment with a recording function that can quickly edit the melodies and business matters stored in the memory device. It is about providing.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is an overall block diagram of an electronic device with a recording function, such as an electronic wristwatch. In the figure, reference numeral 11 denotes an oscillation circuit, and a reference frequency signal outputted from the oscillation circuit 11 is divided into a signal having a cycle of, for example, 1 second via a frequency dividing circuit 12, and is input to a clock circuit 13. This clock circuit 13 counts the input one-second signals and obtains time information of "hours", "minutes" and "seconds". The time information counted by the clock circuit 13 is sent to the display section 14 and displayed. The clock circuit 13 has a counter that stores the alarm time, and outputs an alarm coincidence signal AL to the recording control section 15 when the current time counted by the clock circuit 13 matches the alarm time. The detailed configuration of this recording control section 15 will be described later using FIG. 2. Operation signals of various switches provided in a switch section 16 are inputted to this recording control section 15. The detailed structure of this switch section 16 will be described later using FIG. 2. The recording control section 15 then sends out a signal that determines the display of the display section 14, such as "fast forward" or "slow forward." In addition, the recording control section 15
The clock signal selection signal is sent to the clock selection section 17.
Then, the increment designation signal a and the reverse designation signal b of the counter are sent to the address section 18, and the read/write signal R/
W ₁ to RAM (Random Access Memory) 19
The read/write signal R/W ₂ is stored in the temporary storage unit 2.
0, the operation signal C is outputted to the encoding circuit 21, and the operation signal d is outputted to the encoding circuit 22 in parallel. The reference frequency signal outputted from the oscillation circuit 11 is frequency-divided in the clock selection section 17 based on the clock selection signal and sent to the address section 18 as a predetermined clock signal. The address unit 18 sends a count-up or count-down address designation signal to the RAM 19 based on the clock signal and the step designation signal a or the reverse designation signal b. Further, this address designation signal is sent to the decoder 23, and the address of the RAM 19 designated by the address section 18 is displayed on the display section 14. However, microphone 24
The audio input from the A/D conversion circuit 25 is converted into a digital signal and input to the encoding circuit 21. This encoding circuit 21 encodes the input digital signal and converts it into audio information.
Output to RAM19. A data bus is connected from the output terminal OUT of this RAM 19 to the temporary storage section 20. Furthermore, a data bus is connected from this temporary storage section 20 to the input terminal IN of the RAM 19. Further, the audio information output from the RAM 19 is encoded by the encoding circuit 22 and input to the audio signal circuit 26. And this audio signal circuit 2
6 outputs the synthesized audio signal to the speaker 27.

Next, FIG. 2 shows the detailed configuration of the recording control section 15 and the switch section 16. In the figure, the switch section 16 includes a transfer switch S ₁ , a write switch S ₂ , an execution switch S ₃ , and a mode selection switch.
S ₄ and demonstration switch S ₅ . The operation signals of switches S ₁ and S ₂ are OR circuit 31
The signal is input to the OR circuit 32 via the OR circuit 32. Furthermore, the output signal of the OR circuit 31 is the read/write signal R/
Sent to RAM 19 as W ₁ and OR circuit 3
Sent on 3rd. Further, the operation signal of the switch _S2 is sent to the encoding circuit 21 as an operation signal C. Further, the alarm coincidence signal AL outputted from the clock circuit 13 is inputted to the OR circuit 33a. The output signal of this OR circuit 33a is input to OR circuits 32-34. The operating signal of the demonstration switch _S5 is input to the OR circuit 33a. Furthermore, the operation signal of the switch _S4 is input to the one shot circuit 35. The one shot pulse output from the one shot circuit 35 is input to a hexadecimal counter 36. Furthermore, the output line "1" of the hexadecimal counter 36 ~
The "1" signal is sequentially sent to "5" by operating the switch _S4.The output lines "1" to "5" of the hexadecimal counter 36 are connected to the display section 14. Further, the output lines “1” to “5” are input to the decoder 37. The signals on output lines l ₁ to _{l 4} of this decoder 37 are sent to the clock selection section 17. Further, the signals on the output lines l ₁ and l ₂ of the decoder 37 are input to the OR circuit 32 , and the signals on the output lines l ₃ and l ₄ are input to the OR circuit 38 . Furthermore, the signal on the output line _l5 of the decoder 37 is sent to the temporary storage section 20 as a read/write signal R/ _W2 , and the signal is sent to the OR circuit 32 as a read/write signal R/W2.
~34. Next, the operation signal of switch _S3 is sent to the decoder 37 as an enable signal. The output signal of the OR circuit 34 is sent to the encoding circuit 22 as an operation signal d, the output signal of the OR circuit 32 is sent to the address section 18 as a step designation signal a, and the output signal of the OR circuit 38 is sent to a reverse designation signal. It is sent to the address section 18 as a signal b. In addition, the output lines l ₁ to _{l 4} of the decoder 37
If the “1〓 signal is sent from “Fast Forward”,
``Delayed forward'', ``early return'', and ``late return'' are specified. moreover,
When the OR circuit 33 outputs a "1" signal, "normal" address updating is performed.

Next, FIG. 3 shows the external appearance of the electronic wristwatch with a recording function, where 41 is the case body. and,
This case body 41 has a display section 14 switch S ₁ ~
S ₅ , a microphone 24, and a speaker 27. Furthermore, the display section 14 displays "hours,""minutes," and "seconds."
, digital displays 14a to 14c for displaying , and displays 141 to 144 for displaying the count up or count down speed of the address designation signal sent from the address section 18 to the RAM 19. There are four types of display methods for the display bodies 141 to 144, as shown in FIG. 4 A to D.
indicates that the address is specified by slow forward, B in the same figure by fast forward, C in the same figure by slow return, and D in the same figure by fast return.

Next, the operation of the present invention configured as described above will be explained. First, the reference frequency signal output from the oscillation circuit 11 is passed through the frequency dividing circuit 12 to, for example, 1
The frequency of the signal is divided into a second period signal and input to the clock circuit 13. This clock circuit 13 counts the input one-second signals and obtains time information of "hours", "minutes" and "seconds".
The time information counted by the clock circuit 13 is sent to the display section 14 and displayed.

Next, a case will be described in which the audio input from the microphone 24 is stored in the RAM 19.
First, the write switch _S2 of the switch unit 16 is kept closed, and audio is input from the microphone 24. When the write switch _S2 is closed, the operation signal C is sent to the encoding circuit 21 via the OR circuit 31.
Write signal W ₁ to RAM 19, OR circuit 31 and 3
The increment designation signal a is sent to the address section 18 via 2, and a clock selection signal with a "normal" rate is sent to the clock selection section 17 via OR circuits 31 and 33. Now, for example, if the word "meeting" is input as a voice from the microphone 24, the voice is converted to a digital signal via the A/D conversion circuit 25 and input to the encoding circuit 21. and,
This encoding circuit 21 encodes the input digital signal and sends it to the RAM 19. Here, the clock selection signal at the "normal" speed is sent to the clock signal selection section 17, and the write signal _W1 is sent to the RAM 19, so the encoded audio information is sequentially written into the RAM 19. It will be done. Further, the address of the RAM 19 sent from the address section 18 is displayed on the digital display 14d of the display section 14. As described above, the sound notified at the alarm time is "meeting" or RAM 19.
is memorized. When the current time counted by the clock circuit 13 matches the alarm time preset in the clock circuit 13, an alarm coincidence signal AL is output to the recording control section 16. As a result, the encoding circuit 22 through the OR circuit 34
An operation signal d is sent to the address section 18 via the OR circuit 32, a step designation signal a is sent to the address section 18, and a clock selection signal at a "normal" speed is sent to the clock selection section 17 via the OR circuit 33. As a result, the audio information stored in the RAM 19 is sequentially transferred to the encoding circuit 22 based on the address specified from the address section 18.
The signal is sent to the encoding circuit 21, where the encoding is reversed to that performed by the encoding circuit 21. Then, the signal encoded in the encoding circuit 22 is synthesized into a voice signal in the voice synthesis circuit 26 and sent to the speaker 27. As a result, the speaker 27 issues a sound saying "meeting".

The audio information set in the RAM 19 can be edited arbitrarily, for example, the address "50" displayed on the digital display 14d of the display section 14.
~If you want to transfer the voice information stored in "60", for example "meeting", to addresses "20" to "30", operate mode selection switch _S4 and set the content of hexadecimal counter 36 to "1". After setting, operate execution switch _S3 . As a result, a "1" signal is output to the output line _l1 of the decoder 37, and a "fast forward" clock selection signal is sent to the clock selection section 17. Further, an increment signal a is sent to the address section 18 via the OR circuit 32, and the address designation signal for the RAM 19 output from the address section 18 is counted up in fast forward mode. Then, display section 1
RAM1 displayed on the digital display 14d of No.4
When the specified address of 9 approaches "50",
Operate mode selection switch S ₂ to select hexadecimal counter 3.
After setting the value of 6 to ``2'', operate the execution switch _S3 . As a result, the address designation signal for the RAM 19 output from the address section 18 is counted up in a slow manner. Then, when the address displayed on the digital display 14d reaches "50", the operation of the execution switch _S3 is stopped. Then, operate the mode selection switch _S4 to select the hexadecimal counter 36.
After setting the content to "5", continue operating the execution switch S3 until the address displayed on the digital display ₁₄ becomes "60". As a result, the "1" signal is output from the output line _l5 of the decoder 37, the write signal _W2 is sent to the temporary storage section 20, the operation signal d is sent to the encoding circuit 34, the step signal a is sent to the address section 18, and the clock selection section A "normal" speed clock selection signal is sent to 17. Therefore, the audio information "meeting" stored at addresses "50" to "60" displayed on the digital display 14d is written into the temporary storage section 20. Next, operate mode selection switch _S4 to set the content of hexadecimal counter 36 to "3".
Alternatively, set it to "4" and operate the execution switch _S4 . As a result, the address designation signal output from the address unit 18 is fast-returning when the content of the hexadecimal counter 36 is "3", and slow-returning when the content is "4". Then, when the address displayed on the digital display 14d returns to "20", the transfer switch _S1 is operated. As a result, the write signal R is sent to the RAM 19 via the OR circuit 31, and the OR circuit 3
The increment signals a,
A clock selection signal at a "normal" speed is sent to the clock selection section 17 via the OR circuit 33. As a result, the audio information "meeting" stored in the temporary storage unit 20 is transferred to the digital display unit 1.
It is forwarded to addresses "20" to "30" displayed in 4d. In addition, the digital display body 14 of the RAM 19
I want to pre-store "meeting" as audio information in addresses "60" to "70" displayed in d, and "telephone" as audio information in addresses "70" to "80", and have them sound at the alarm time. In this case, the voice information "Meeting" stored in the above addresses "50" to "60" was transferred to addresses "20" to "30" to sound at the alarm time. Just transfer it to "20" to "30".
Here, the addresses "0" to "10" and "20" to "30" of the RAM 19 are sounded at the alarm time. Furthermore, if the user wishes to make sound information already stored in the RAM 19 sound at a time other than the alarm time, the demonstration switch _S5 is operated. At this time, the user operates the execution switch _S3 and the mode selection switch _S4 to display on the digital display 14d the address where the audio information to be sounded is stored. Next, turn on the demonstration switch.
When _S5 is operated, an operation signal d is sent to the encoding circuit 22 via the OR circuit 34, an increment designation signal a is sent to the address section 18 via the OR circuit 32, and a "normal" speed clock is sent via the OR circuit 33. A selection signal is sent to clock selection section 17. Thereafter, a sound is output from the speaker 27 in the same manner as the sounding operation of the alarm time. Further, when erasing the contents of the RAM 19, the address of the RAM 19 is designated and the transfer switch _S1 is operated in a state where nothing is stored in the temporary storage section 20.

As detailed above, according to the present invention, there is provided an A/D conversion circuit 25 that converts externally input audio from analog to digital, and a digital signal output from the A/D conversion circuit that is encoded into an audio information signal. encoding circuit 21
an address circuit 18 that counts clock signals of a predetermined period and outputs this count value as an address designation signal for sequentially updating addresses; and an address circuit 18 that is addressed by the address designation signal from this address circuit 18. Audio information storage that stores audio information signals encoded in
RAM 19; audio signal circuits 22 and 26 that read the audio information signal stored in the audio information storage RAM and output the audio signal; and sound generating means 27 that is supplied with the audio signal from this audio signal circuit and produces audio. an electronic device with a recording function, comprising: address display means 14d for displaying contents of address designation by the address circuit; Clock signal selection control means l ₁ , 32, 17 for updating the addressing of the information storage RAM at a cycle earlier than the clock signal having the predetermined cycle.
After the address designation has been updated by the selection control means, the clock signal of the predetermined cycle is supplied to the address circuit to update the audio information stored in the audio information storage RAM after the address designation. Since it is equipped with the means 33, 33a, 34 and the signal d for reading out and producing sound at a predetermined period, even if the content recorded by the RAM 19 is long, it can be quickly forwarded and played back to the address position where the desired content is stored. It is possible to provide an electronic device with a recording function capable of recording.

[Brief explanation of drawings]

The drawings show one embodiment of the invention.
The figure is an overall block diagram of the electronic device with a recording function, Figure 2 is a detailed diagram of the recording control section and switch section, Figure 3 is an external view of the electronic wristwatch with a recording function, and Figures 4A to D are It is a figure which shows a display state. 11...Oscillation circuit, 15...Recording control section, 16
...Switch section, 17...Clock selection section, 18
...address section, 19...RAM, 20...temporary storage section, 27...speaker.

Claims (1)

[Claims] 1. An A/D conversion circuit 25 that converts externally input audio from analog to digital, and an encoding circuit that encodes the digital signal output from the A/D conversion circuit into an audio information signal. 21
an address circuit 18 that counts clock signals of a predetermined period and outputs this count value as an address designation signal for sequentially updating addresses; and an address circuit 18 that is addressed by the address designation signal from this address circuit 18. Audio information storage that stores audio information signals encoded in
RAM 19; audio signal circuits 22 and 26 that read the audio information signal stored in the audio information storage RAM and output the audio signal; and sound generating means 27 that is supplied with the audio signal from this audio signal circuit and produces audio. an electronic device with a recording function, comprising: address display means 14d for displaying contents of address designation by the address circuit; Clock signal selection control means l ₁ , 32, 17 for updating the addressing of the information storage RAM at a cycle earlier than the clock signal having the predetermined cycle.
After the address designation has been updated by the selection control means, the clock signal of the predetermined cycle is supplied to the address circuit to update the audio information stored in the audio information storage RAM after the address designation. An electronic device with a recording function, characterized in that it comprises means 33, 33a, 34 for reading and producing sound at a predetermined period, and a signal d.