JPH02164038A - Formation of flattened metal wiring - Google Patents

Abstract

PURPOSE:To assure flattened metal wiring by performing ion-implantation into an insulating film, and thereafter etching the insulating film in the shape of a wiring pattern halfway, and forming a conductor film selectively only in a groove in an etched portion. CONSTITUTION:An SiO2 film 4 and a resist film 2 are formed on a Si substrate 5, and an opening portion through the resist mask 2 is adapted to correspond to a pattern, according to which wiring is formed. In this situation, ion- implantation is performed to form a damage area 3 inside the SiO2 film 4 over the opening portion of the resist mask 2 at a depth specified by ion-implantation energy and ion species. For ion species Si and O or rare gas ion are used for example. Then, the SiO2 film 4 is etched up to a damage region 3 to expose the damage region 3 on the bottom of a groove, and remove the resist mask 2. Thereafter, a metal film 6 is formed only in the groove formed in the surface of the SiO2 film 4 by a reduced pressure CVD process. The metal film 6 flattened with respect to the SiO2 film 4 can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a metal thin film, and more particularly to a method for forming a flattened metal wiring suitable as an LSI wiring material.

[Conventional technology]

L S I (Large 5ca1.e Integ
In recent years, surface planarization has become increasingly important.

Multilayer wiring is mainly achieved by flattening an interlayer insulating film formed on a wiring pattern.

Typical examples include etchback method, glass coating method,
There are bias sputtering methods, etc.

The etch-back method is performed as follows. After metal wiring is formed, an insulating film is first deposited so as to completely fill the trenches between the wirings, and then a flattening sacrificial film such as photoresist is coated on top of the insulating film by spin coating. Since the resist is fluid, its surface is flat. When this sacrificial planarity film and the insulating film are etched at the same rate, a flat insulating film remains on the metal wiring.

In the glass coating method, a solution of an organic silicon compound is spin-coated and then vitrified by heat treatment.

The bias sputtering method is a method of depositing an insulating film by sputtering and simultaneously forming and planarizing the insulating film by utilizing the dependence of the etching rate on the ion incidence angle in sputter etching.

In addition, there are organic resin coating methods, glass flow methods, and other glabella insulating film flattening methods.
orld), 1987, 3.

"Recent progress in p, 36r multilayer wiring planarization technology".

[Means to solve the problem]

The above purpose is to form areas where nucleation, which is the initial stage of film formation, is preferentially caused in the insulating film by ion implantation, or where some types of impurity atoms are evident. This is achieved by etching to expose the layer in which nucleation occurs preferentially at the bottom of the trench, and selectively forming a metal film only inside the trench by CVD or the like. This will be explained in detail below using FIG.

In FIG. 1(a), 540. A film 4° resist mask 2 has already been formed. The Si◯2 film 4 corresponds to a first passivation film or an insulating film between the eyebrows between multilayer interconnections. Further, the opening portion of the resist mask 2 corresponds to a pattern in which wiring is to be formed. At this stage, ion irradiation is performed to remove Sio from the openings of the resist mask 2 and the film 4.
A damaged region 3 is formed at a depth determined by the ion implantation energy and ion species. For example, Si, Ol, or rare gas ions are used as the ion species. Next, as shown in FIG. 1(b), S i O and JFJ 4 are etched up to the damaged area 3.
A damaged area 3 is exposed at the bottom of the groove. Subsequently, after removing the resist mask 2, as shown in FIG.
A metal film 6 is formed by a method. As a result, Sio, membrane 4
The metal film 6 can be formed flat against the surface. By further forming a SiO□ film 4' on top of this and repeating the same process, it is possible to form a flat multilayer wiring.

In actual processes, contact holes and through holes are formed in an insulating film, and semiconductors, metals, or compounds thereof (for example, silicide) are often exposed. In such a case, it is also possible to simultaneously fill contact holes and through holes.

In this description, it is assumed that the damaged region 3 is formed by ion implantation, but the impurity region may be formed using metal element ions.

Further, as a means for forming the metal film 6, optical CVD using a light source such as a laser can be used.

According to the photo-CVD method, it is possible to form a metal film at high speed at low temperatures, and by removing the resist mask 2 after forming the metal film 6 with the resist mask 2 attached, the metal film can be deposited in unnecessary locations. It can be prevented.

[Problem to be solved by the invention]

Problems with the above conventional technology will be explained below.

In the etch-pack method, it is important to completely fill the trenches between wires with an insulating film, but if the trench width becomes narrower as the wire spacing increases, a problem arises in that cavities are formed within the trenches.

The glass coating method has only a small effect in that the inclination of the stepped portions at the edges of the wiring is somewhat relaxed, and there is also the problem that the crack resistance of the glass itself is low.

In the bias sputtering method, there are interlayer points such as damage to the device due to ion llrml and charge-up of the insulating film, and contamination due to heavy metals sputtered from the inner wall of the chamber.

As described above, there are various methods for planarizing an interlayer insulating film after metal wiring is formed, but there are many problems that need to be solved. Therefore, an object of the present invention is to planarize the surface by selectively depositing a metal material only in the grooves formed on the surface of the underlying insulating film.

[Effect]

The present invention takes advantage of the fact that nucleation, which is the initial stage of film formation, occurs preferentially in damaged areas formed by ion irradiation or in impurity areas.For example, WF is decomposed by the H2 reduction method. When forming a W film using
There are conditions in which film formation progresses only on Si, and almost no film formation occurs on SiO□. This is thought to be because the nucleation necessary at the initial stage of film formation occurs only on Si.

Therefore, in order to form a W film on a SiO film by the CVD method, it is necessary to modify the Si film surface to facilitate nucleation. The regions are formed in the SiO□ film and then etched to create a surface that is susceptible to nucleation.

〔Example〕

Examples of the present invention will be described below.

[Example 1] Example 1 shows the effects of the present invention in the simplest manner. The explanation will be given below according to FIG.

In FIG. 1(a), a film with a thickness of 1.8 μm is formed on the Si substrate 5.
A film 4 of Sin is formed. The openings in the resist mask 2 correspond to the metal wiring patterns. Here, S
Using i+ ion beam 1, range Rp is sio, membrane 4
Ion implantation was performed under conditions such that the depth was approximately 0.8 μm, and the damaged region 3 was formed at a portion slightly shallower than 0.8 μm.

Next, etching the Sio film 4 and forming the 111(b)
The damaged area 3 was exposed at the bottom of the groove as shown in FIG. S
io, anisotropic dry etching was used for etching the film 4.

Subsequently, after removing the resist mask 2, selective CVD was performed on the W film 6 to fill the trench as shown in FIG. 1(c). In this example, selective CVD was performed at a substrate temperature of 300° C. using WF and H2 as source gases, and the trench could be filled in 10 minutes. In addition, SiO□ other than the groove
No W nuclei or film formation was observed on the surface of film 4.

As described above, since the wiring was formed flat on the SiO□ film 4, a SiO
□The film 4' can be formed flat, and multilayer wiring can be easily realized.

[Example 2] This example describes a case in which the selectivity of metal CVD is low and nucleation and film formation occur in areas other than the damaged area (or impurity area) formed by ion implantation. It was applied.

For example, if a W film is formed using laser CVD, it is possible to form the film at a lower temperature and at a higher speed. However, if the same procedure as in Example 1 is used, the 1 selectivity decreases and
Nucleation and film formation also occur on the surface of.

Therefore, as shown in FIG. 2(a), a resist mask 2
Laser CVD was performed on the W film without removing it. As a result, the grooves could be filled in 2 minutes under the condition that the substrate temperature was 150°C. and.

W6' on the resist mask 2 could be removed at the same time as the resist mask 2, leaving the W film 6 only in the grooves as shown in FIG. 2(b).

[Embodiment 3] In this embodiment, after performing ion implantation, a resist mask is formed and a 5in2 film is etched to form a groove.

As shown in FIG. 3(,), ions were implanted into the entire surface of the Sio2 film 4 formed on the Si substrate 5 to form a damaged region 3. Next, after forming a resist mask 2, the Sio2 film 4 was etched to expose the damaged region 3 at the bottom of the groove. Next, the resist mask 2 was removed and selective CVD of W was performed to obtain the structure shown in FIG. 3(Q). The conditions for selective CVD of W are the same as in Example 1.

[Example 4] In this example, an FIB was used for ion implantation.

First, as shown in FIG. 4(a), a Ti impurity region 8 was formed in the Sio film 4 using a Ti+ FIB. Next, as shown in FIG. 4(b), a damaged region 3 is formed in the SiO□ film 4 on the Ti impurity region 8 using a Si4 FIB.
was formed. Next, by wet etching using hydrofluoric acid, the damaged region 3 could be selectively etched as shown in FIG. 4(c), and the Ti impurity region 8 could be exposed at the bottom of the trench. . After this, W's selection C
VD was performed to form a W film only within the groove.

As described above, this example utilizes the fact that nucleation occurs preferentially in the impurity region of the metal element and a metal film can be selectively formed.

Incidentally, since the range can be freely changed depending on the implantation conditions (acceleration voltage), the order of Ti+ ion implantation and Si4 ion implantation may be reversed.

In this way, by using FIB, it is possible to form a groove in the shape of a metal wiring pattern without using a resist mask, and selectively form a metal film within the groove.

〔Effect of the invention〕

According to the present invention, metal wiring can be formed flat on the first passivation film and glabellar insulating film in an LSI, so (1) steps that are likely to cause disconnection are reduced; (2)
Photolithography mask alignment becomes easier (
3) There is an effect that wiring can be easily multilayered.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the means for solving interlayer points in the present invention and Example 1, and FIG. 2 is a diagram for explaining Example 2.
FIG. 3 is a diagram for explaining the third embodiment, and FIG. 4 is a diagram for explaining the fourth embodiment. DESCRIPTION OF SYMBOLS 1...Si+ ion beam, 2...Resist mask, 3...Damage area, 4...Sin, film, 4'.
...Sin. Film, 5...Si substrate, 6...W film, 6'...W,
7...Ti+ FIB, 8...Ti impurity region, 9
...Si4 FIB. 7th eye 3: Damage゛4j! A t: w-th term, 28 Z': W-th Σ

Claims (1)

[Claims] 1. After implanting ions into an insulating film, the insulating film is etched halfway into a wiring pattern, and a conductive film such as metal or silicide is selectively etched only inside the grooves of the etched portion. A method for forming a planarized metal wiring, the method comprising: forming a flattened metal wiring; 2. The method of forming a planarized metal wiring according to claim 1, wherein the ion implantation is performed using an ion beam containing an element constituting the insulating film. 3. The method of forming a planarized metal wiring according to claim 1, wherein the ion implantation is performed using an ion beam containing a metal element. 4. The method for forming a planarized metal wiring according to claim 1, wherein the ion implantation is performed on the entire surface of the wafer, and then the insulating film is etched halfway into a wiring pattern using a resist mask. . 5. The method of forming a planarized metal wiring according to claim 1, wherein the ion implantation is performed after forming a resist mask pattern, and then the insulating film is etched halfway. 6. Claim 1, wherein the ion implantation is performed using a focused ion beam (FIB), and only the ion-irradiated portion of the insulating film is selectively etched halfway.
A method of forming a planarized metal interconnect as described. 7. A means for selectively forming a metal film only inside the groove of the etched portion is low pressure CVD (Chemical Vapor Deposition).
2. The method for forming a planarized metal wiring according to claim 1, wherein the method is the method n). 8. The method of forming a planarized metal wiring according to claim 1, wherein the means for selectively forming the metal film only inside the groove of the etched portion is a photo-CVD method.