JPH0216312Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to an audio clock that notifies the time by voice.

(Prior art) Conventionally, Utility Models 1988-44486 and 1987-
As shown in No. 42788, a clock has been developed that announces the time audibly at a fixed time or in response to the operation of an external switch.

These have a built-in voice synthesizer that reads audio data for audio notification based on time data measured by a clock circuit and outputs an audio signal based on this audio data.

(Problem that the invention aims to solve) However, although these clocks emit complex sounds like humans, there is no visual change when the sounds occur, and they lack interest.

(Means for Solving the Problems) An object of the present invention is to provide a voice clock that visually changes when a voice is generated.

To this end, the present invention provides a shift register that inputs a detection signal that detects that an audio signal is output from a speech synthesis circuit as a data signal, and that receives a constant periodic signal from a clock circuit as a clock input. The present invention is characterized in that by providing a light emitting display element on each output side of the shift register, the light emitting display elements are sequentially turned on in a fixed direction simultaneously with the sound generation.

(Embodiment) FIG. 1 is a circuit diagram of a voice clock in an embodiment of the present invention.

In the figure, 2 is a clock circuit, which measures time based on an oscillation frequency signal generated by a connected oscillation element 4. The measured time is then supplied as a display signal to the connected display section 6, where the time is displayed.

An external switch 8 is also connected to the clock circuit 2, and when the external switch 8 is operated, address data corresponding to the time is output to six output lines _A0 to _A5 .

Output lines A ₀ to _{A 5} are connected to the speech synthesis circuit 10 . The speech synthesis circuit 10 uses these output lines A ₀ to _{A 5}
The necessary audio data is read out from the internally stored audio data based on the address data from the audio data, and a desired audio signal with an analog waveform is synthesized. In addition to this, the voice synthesis circuit 10 receives a constant periodic signal from the clock circuit 2 that is the basis of operation and voice signal synthesis at the input/output terminal φ, and inputs a reset signal for returning the operation to its initial state at the input terminal CL. . Conversely, the output terminal of the speech synthesis circuit 10
A one-shot pulse is supplied from the BURY/NAR to the _K2 input terminal of the clock circuit 2 from the speech synthesis circuit 10 every time the voice of a desired word, such as "ichi", "ji" or "hun", ends. There is. The clock circuit 2 receives this one-shot pulse and outputs address data corresponding to the next word to be generated.

On the other hand, the analog waveform audio signal synthesized by the audio synthesis circuit 10 is sent to the output terminals DAU and DAL.
is output from. At the same time, the output terminal SPE
, outputs an "H" level signal while an analog waveform audio signal is being output.

The drive circuit 12 is an output terminal of this speech synthesis circuit.
This circuit receives signals from the DAU, DAL, and SPE, drives the connected speaker 14, and generates audio.

In the present invention, a shift register 18 (for example, a Motorola 74
HC164). A transistor 20 is connected to the VDD terminal, which is the power supply terminal of this shift register 18.
The emitter terminal of is connected. An "H" level signal is input to the collector terminal of this transistor 20, and the SPE terminal is connected to the base terminal. Therefore, when audio is being output and the signal from the SPE terminal is at the "H" level, the transistor 20 is turned on, and the shift register 1 is thereby turned on.
8 becomes operational.

In addition, another data input B of the shift register 18 receives BURY/
A signal from the NAR terminal is input, and a display drive signal (32Hz) from the terminal COM of the clock circuit 2 is input to the clock input φ.

Furthermore, the output Q _A ~Q _F of this shift register 18
is connected to the LED 28a via the pull-down resistor 26.
~28f are connected.

The operation will be explained below using the time chart shown in FIG.

When the external switch 8 is operated, the speech synthesis circuit 10
When the audio signal from the DAU terminal is output,
A “H” level signal is output from the SPE terminal,
The shift register 18 becomes operational. A positive single pulse is generated from the data input terminal B between the words of the generated speech, and this pulse signal is output from the output Q _A in synchronization with the constant periodic signal φ supplied to the clock input φ. Q _F , and the LED 28a to which the "H" level signal was input
~28f lights up. Therefore, when an audio signal is generated, the LEDs 28a to 28f are lit in this order.

(Effects of the Invention) As described above, according to the present invention, the light-emitting display elements light up sequentially in a certain direction at the same time as the sound is generated, making it possible to give an interesting appearance. Furthermore, the light-emitting display elements may have various colors, which can significantly increase the commercial value.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a voice clock according to an embodiment of the present invention. FIG. 2 is a time chart showing the operation of FIG. 1. 2...Clock circuit, 10...Speech synthesis circuit, 16
... Sound generation circuit, 18 ... Shift register, 28a
~28f...LED.

Claims (1)

[Scope of utility model registration request] an oscillator, an external switch, and an oscillator that receives an oscillation output signal from the oscillator, measures time, outputs a time display signal, outputs address data corresponding to the time in response to operation of the external switch, and further oscillates the oscillator. a clock circuit that outputs a constant periodic signal obtained by dividing the output signal; a display section that receives a time display signal from the clock circuit and displays the time; and a display section that receives an address data signal from the clock circuit and displays the address data. A speech synthesis circuit that reads out the data necessary for speech generation in response to the output and outputs a speech signal, and also outputs a speech output detection signal to notify that the speech signal is being output, and a speech synthesis circuit that receives the speech signal from this speech synthesis circuit. and a sound generation circuit that generates a sound using a clock circuit, the sound clock is operable only when the sound output detection signal is output, and the sound output detection signal is connected to a data input, and the sound output detection signal is connected to a data input, and 1. An audio clock comprising: a shift register to which a periodic signal is connected to a clock input; and a plurality of light emitting display elements connected to the output side of the shift register.