JPH02162717A - Formation of quantum fine wire - Google Patents

Abstract

PURPOSE:To form the arrangement of a quantum fine wire, having the width of several atomic layers in the same thickness as the stepping of crystal face, in a highly precise manner by a method wherein a quantum well semiconductor layer, which is epitaxially grown, is formed by controlling its thickness and width smaller than the de Broglie wavelength. CONSTITUTION:The crystal face of a substrate is formed into a face (111)B which is inclined in orientation <110>. As a result, the substrate surface is turned to the face (111)B having a stepping periodically. The side face constituting the stepping is a face (110). In the first atomic layer epitaxy, a semiconductor layer having a wide forbidden band width, which becomes the barrier of quantum well, is deposited. As it is an isotropic qrawing method, the stepping on the substrate crystal surface is in the state as it is. When a semiconductor, which becomes a confinement layer, is coated thereon using an anisotropic crystal growth method, no crystal growth progresses on the face (111)B, and crystal growth progresses only on the face (110) of the stepped part. As a result, a confinement layer, having the controlled atomic column number in lateral direction, is formed in the thickness same as the stepping. In the subsequently conducted atomic layer epitaxy, the barrier layer of a quantum well is formed enveloping the formed carrier confinement layer, and a quantum fine line is formed.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a method for forming a quantum well structure that confines carriers by utilizing the energy band structure of a semiconductor.
The purpose of the present invention is to provide a method for forming a first semiconductor layer having a wider forbidden band width by isotropic atomic layer epitaxy on the surface of a semiconductor substrate having a step in the crystal plane, and the above process. a step of depositing a second semiconductor having a narrower forbidden band width by anisotropic atomic layer epitaxy on the crystal plane step portion existing on the surface of the semiconductor substrate subjected to the step; The method includes the step of forming the first semiconductor layer by isotropic atomic layer epitaxy on the surface of the substrate on which the second semiconductor is deposited.

[Industrial application field]

The present invention relates to a quantum well that confines carriers by utilizing the energy band structure of a semiconductor, and particularly relates to a method for forming a quantum wire, which is a quantum well structure that confines carriers in two dimensions.

The shape of a quantum well is a type of superlattice structure in which a semiconductor layer with a narrow bandgap is sandwiched between semiconductor layers with a wide bandgap.
The thickness of the narrow bandgap semiconductor layer is smaller than the de Broglie wavelength of carriers. Furthermore, when a quantum well is used in an active element, the thickness of a semiconductor layer with a wide forbidden band that serves as a carrier confinement barrier may be set to such a level that the carrier tunneling probability becomes a significant value.

The commonly known one-dimensional confinement quantum well is
The structure that suppresses carrier motion in one dimension only is called a quantum wire, and the structure that suppresses it in two dimensions is called a quantum box. .

In a one-dimensional confinement structure, it is only necessary to control the thickness of the confinement layer to a few atomic layers, whereas in the case of quantum TA lines, the width is also required to be of a similar value.

There are various types of active elements that utilize quantum well structures, but it is known that, for example, quantum conversion efficiency can be greatly improved by making the active layer of a semiconductor laser, where oscillation occurs through recombination, a quantum well structure. It is believed that the quantum conversion efficiency can be further improved by changing the quantum well structure from a one-dimensional confinement structure to a quantum wire, which is a two-dimensional confinement structure.

[Prior art and problems to be solved by the invention] A one-dimensional confinement quantum well structure has been developed using atomic layer epitaxy (AL).
E) is formed. Typically, in ALE, each element constituting a semiconductor is repeatedly adsorbed onto a substrate one atomic layer at a time, resulting in epitaxial growth in atomic layer units, and the adsorption does not proceed beyond one atomic layer. Raw materials that exhibit self-limiting effects are used.

With this method, it is possible to control the thickness of the semiconductor layer constituting the quantum well to the extent indicated by the number of atomic layers;
In order to control the width and length with the same precision, a different control method must be used. Conventionally known methods for controlling the width and length include methods that use focused ion beams. Confinement in the direction perpendicular to the growth direction is such that a quantum size effect is observed, and control of the dimensions of the quantum wire or quantum box is insufficient.

An object of the present invention is to provide a processing method for forming an epitaxially grown quantum well semiconductor layer by controlling its thickness and width to be smaller than the de Broglie wavelength, thereby providing a method for forming quantum wires with high precision. It is to provide.

(Means for Solving II!fl) In order to achieve the above object, the quantum wire forming method of the present invention has a growth rate of is present on the main surface of the semiconductor substrate surface on which the first semiconductor layer is formed; A step of depositing a second semiconductor having a narrower forbidden band width than the first semiconductor in an amount indicated by the number of atomic columns on a step portion of a crystal plane, and selectively depositing the second semiconductor. forming the first semiconductor layer on the surface of the semiconductor substrate using a growth method in which the growth rate does not depend on the underlying crystal orientation and the growth thickness can be controlled on an atomic layer basis.

In other words, this is a step of forming a first semiconductor layer with a wider forbidden band width by isotropic atomic layer epitaxy on the surface of a semiconductor substrate having a step difference in crystal planes, and a step of forming a first semiconductor layer with a wider forbidden band width on the surface of a semiconductor substrate having steps in the crystal plane. A second band with a narrower forbidden band width exists in the crystal plane step part that exists in the
forming the first semiconductor layer on the surface of the substrate on which the second semiconductor is deposited by isotropic atomic layer epitaxy; It is to include the process.

Through the above steps, a carrier confinement layer is formed that is surrounded by a semiconductor layer that serves as a barrier for the quantum well and has a thickness corresponding to the step of the crystal plane and a width as indicated by the number of atoms arranged.

[Function] By making the substrate crystal plane three (111) planes tilted in the <110> direction, the substrate surface has periodic steps (111).
) The side surface that makes up the 0 step difference that is the s-plane is (110)
It is a surface.

In the first atomic layer epitaxy of the above steps, a semiconductor layer with a wide forbidden band width is deposited as a barrier for the quantum well, but since it is an isotropic growth method, the steps in the substrate crystal plane are accepted as they are. will be inherited.

When a semiconductor to be used as a confinement layer is deposited on this using an anisotropic crystal growth method, crystal growth does not proceed on the (111) s plane, but only on the (110) plane at the stepped portion. , a confinement layer is formed with the same thickness as the step and a controlled number of atomic columns in the lateral direction.

In the subsequent atomic layer epitaxy, a quantum well barrier layer is formed to surround the carrier confinement layer formed in the previous step, and a quantum wire is formed.

According to the above process, the carrier confinement layer is formed as a layer having the same thickness as the steps of the crystal plane and a width of several atomic layers,
Furthermore, a barrier layer surrounding it is also formed to a predetermined thickness.

〔Example〕

FIGS. 1-(e) are schematic cross-sectional views showing the steps of an embodiment of the present invention. Hereinafter, explanation will be given with reference to the drawings.

Figure (a) shows a vertical cross section of the GaAs single crystal substrate 1, and the surface is a plane inclined 4' in the <110> direction from (111L).With this inclination, one beam is produced for every 40 people. There is a step 7 in the atomic plane due to the density, and the substrate surface is as shown in the figure.
It has a staircase shape composed of 111)l and (110).

Aj! on this board surface by ALE! Grow GaAs. In ALE, growth proceeds isotropically regardless of the crystal plane, so the AffiGaAs layer 2 is formed in a shape that continues the step shape of the substrate as shown in FIG. 1 (Φ).

0M0VPE to grow CaAs on this using MOVPE
is a crystal growth method that uses a metal organic compound as a raw material for a metal element among the elements constituting a semiconductor, but it is an anisotropic epitaxial growth method that hardly grows on a specific crystal plane.

In the case of this example, the growth rate on the (111) s-plane is almost zero, and growth progresses only on the (110) plane, so lateral growth progresses only on the stepped portion of the substrate surface, and the growth rate on the (111) s-plane is almost zero. 1
As shown in Figure (C), a GaAs layer is formed. By controlling the rate and time of raw material supply, a GaAs layer 3 having a width shown as d in the figure is formed.

Subsequently, Al1Ga covering GaAs1ii3 is formed by the same process as the initial A I Ga As N 2 formation.
A5j14 is grown epitaxially. When this step is completed, parallel rows of quantum wires are formed that are arranged on the substrate surface close to the (111) plane. This state is shown in FIG. 1(d).

If necessary, the above process is repeated and the process shown in FIG. 1 (e
) (forms a structure in which quantum wires are arranged in multiple stages. In the figure, 5 is a quantum wire of lCaAs, and 6 is an Aj!Ga quantum wire.
It is As.

As already mentioned, a semiconductor laser is an example of a semiconductor device in which quantum wires are formed by the above method and excellent functions are realized thereby. It is known that quantum conversion efficiency can be increased by forming the active layer, which is the recombination oscillation region, into a quantum well structure. It is thought that quantum conversion efficiency can be further improved by changing to a quantum wire, which has a confinement structure.

In addition, devices such as Fabry-Bello interferometers in optical devices that utilize the resonance of the electron wave function in a quantum well to transmit only electrons with a specific energy can be used to change the quantum well structure from a one-dimensional confinement structure to a two-dimensional structure. By creating a dimensional confinement structure, it is possible to improve the transmittance distribution.

〔Effect of the invention〕

As explained above, according to the present invention, an array of quantum wires having the same thickness as the step of the crystal plane and the width of several atomic layers can be formed with high precision. The distance between the quantum wires can be adjusted by adjusting the inclination of the substrate surface.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view showing the process of the example, in which 1 is a GaAs substrate, 2.4.6 is the first semiconductor layer formed by an isotropic growth method, Aj! GaAs. 3.5 is GaAs, which is a second semiconductor formed by an anisotropic growth method. 7 is a crystal plane step. l Schematic cross-sectional diagram showing the steps of the GaAs substrate example Figure 1 (Part 1)

Claims (1)

[Claims] A semiconductor substrate (1) having a (111)_s plane tilted in the <110> direction as its main surface and a step (7) formed by the (111)_s plane and the (110) plane. a step of forming a first semiconductor layer by a growth method in which the growth rate does not depend on the underlying crystal orientation and the growth thickness can be controlled on an atomic layer basis; a semiconductor substrate on which the first semiconductor layer (2) is formed; The (110) plane forming the step (7) on the main surface of the plane is grown using a growth method that has a growth rate that depends on the underlying crystal orientation and can control the growth thickness on an atomic layer basis, which is more prohibitive than the first semiconductor. A step of depositing a second semiconductor (3) having a narrow band width in an amount indicated by the number of atomic rows, and a step of depositing a second semiconductor (3) having a narrow band width in an amount indicated by the number of atomic rows, and a step of depositing a second semiconductor (3) having a narrow band width on the semiconductor substrate surface on which the second semiconductor is selectively deposited; A growth method that does not depend on
A method for forming a quantum wire, comprising the step of forming the first semiconductor layer (4).