JPH0423471A - Manufacture of vertical superplattice element - Google Patents

Abstract

PURPOSE:To manufacture a vertical superlattice element by using an impurity doped layer by thermally selectively etching two undoped layers by using a difference in vapor pressures between materials. CONSTITUTION:A step of crystalline growing a vertical superlattice structure 13 using an atomic step on the surface of a compound semiconductor substrate 11 in which its main surface is inclined from a low index surface, a step, subsequent to the previous step, of once exposing the substrate 11 with the atmosphere and then thermally selectively etching one forming layer 13' a for forming the superlattice 13 by using a difference in vapor pressures between materials, and a step, subsequent thereto, of again growing a semiconductor layer are provided. As the two forming layers of the vertical superlattice, undoped two-dimensional compound semiconductor such as (AIAs)1/2(GaAs)1/2 can be included. Thus, the vertical superlattice including an impurity doped layer is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Industrial Application Field The present invention relates to a method for manufacturing a vertical superlattice element.
The present invention relates to a method for manufacturing a vertical grating element including an impurity-doped layer made of a compound semiconductor, which is extremely useful for application to electrical or optical elements.

(b) Conventional technology A conventional method for creating a vertical superlattice using a thin film growth method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) will be explained.

When there are atomic steps on the crystal surface, atoms supplied from the source diffuse across the surface and are preferentially adsorbed to the steps. Therefore, if a semiconductor substrate (off-substrate) having a plane slightly inclined from the low-index plane is used, crystal growth proceeds in the in-plane drawing direction starting from the step. The growth of vertical superlattices is based on this principle.

Figure 5 shows an off-substrate 21'' grown (GaAs) tv.
(A'l A S ) 1/2 vertical type super(8 children and a diagram schematically showing their growth process.

As shown in Figure 5(a), GaAs f is placed on each terrace.
424 and AlAslAs layers 5 are stacked to form a superlattice in a direction parallel to the substrate surface. For example, when the off angle is lo, the period of the superlattice is about 16 nm, and when it is 12°, it is about 8 nm.
It is m.

Next, the growth process will be explained with reference to FIGS. 5(b) and 5(c). When a 1/2 atomic layer of GaAs raw material is supplied to the substrate surface, a GaAs monoatomic layer is formed starting from each step 50a, 50b forming each crystal growth surface, as shown in FIG. 5(b). 22 grows on 1/2 of the terrace. Next, when Δ18S is supplied for 1/2 atomic layer, a GaAs monoatomic layer 22 grows on 1/2 of the terrace starting from the step, as shown in FIG. 5(1)). do. Subsequently, when 1/2 atomic layer of AlAs is supplied, an A1ΔS monoatomic layer 23 grows on the remaining 1/2 of the terrace as shown in FIG. 5(C). In this way, when the raw materials of GaAs and Δ1ΔS are alternately and accurately switched and supplied by 1/2 atomic layer, a vertical superlattice as shown in FIG. 5(a) is obtained.

(c) Problems to be Solved by the Invention However, there is a problem in that the periodicity of the superlattice is disturbed when impurities such as Si are doped in the "-described type superlattice growth, and a vertical superlattice containing a doped layer cannot be fabricated. could not. For this reason, until now, element structures using vertical superlattices have been limited to structures that can only use undoped superlattices.

The present invention (1,1) was made to solve such problems, and its purpose is to provide a method for manufacturing a vertical superlattice element including an impurity doped layer, and to provide a method for manufacturing a vertical superlattice element of various types. It is about making structure possible.

(d) Means for Solving the Problems This invention utilizes atomic steps on the surface of a compound semiconductor substrate whose main plane is tilted from a low-index plane to crystallize two constituent layers consisting of an undoped compound semiconductor + 71. Following this step, the compound semiconductor substrate is once exposed to the atmosphere to form a substantially thin oxide +1h on the surface of the substrate, and then the materials of the two constituent layers are Thermal selective etching of one of the constituent layers using the vapor pressure difference between
1′.

The present invention provides a method for manufacturing a vertical superlattice element characterized by including a step of selectively growing a conductor layer again.

However, the method for manufacturing a vertical superlattice element of the present invention includes a delivery growth process of a vertical superlattice structure using atomic steps on the surface of a compound semiconductor substrate whose main plane is inclined with respect to a low-index plane, and a subsequent growth process. After once exposing the substrate to the atmosphere, a step of thermally selectively etching the constituent layer of the layer 111 using the difference in vapor pressure between the holes 111 and subsequent steps are performed. The method is characterized in that it includes a step of growing the semi-rod layer again.

The two constituent layers of the vertical superlattice in this invention are:
For example, it is made by combining ΔIAs and GaAs (A
Examples include amplified binary compound semiconductors such as lA s ) 172 (GaΔS)l/2.

In addition, the semiconductor side tree: 1 is the II+- group compound semiconductor side'1
: “It is not limited to 1.

In this invention, forming a substantially thin oxide film on the surface of a compound semiconductor substrate by exposing it to -11 atmosphere means, for example, (ΔIAs)l/2(GaAs)l/2
In the superlattice, there is a layer of about 5 nm on the surface of these two constituent layers.
By forming an oxide film of
While growing the Baidu 1ζ-pink layer on the tink removal area, grow the above doping layer on the other A1A3 layer.
It means no.

At this time, it is preferable to grow the doped layer by MOCVI method rather than MBE (Molecular Beam Evital Method).

As mentioned above, the greatest feature of this invention is that the two undoped constituent layers are thermally selectively etched (sublimation etching) by utilizing the difference in vapor pressure between the materials. 1.

Therefore, for example, if a doping layer is previously provided between a compound semiconductor substrate and two constituent layers, it is also possible to fabricate a vertical pn-doped superlattice. , as a second embodiment of this invention (n-GaAs)
A l/2(p GaAs) I/l vertical superlattice 14 is shown.

With this invention, it is possible to fabricate a wide variety of device structures by changing the configurations of the two undoped layers and the regrown film.

In this invention, each grown film is formed using a well-known growth technique such as the MBIE method or the MOCV l) method.

(e) Effect The present invention consists of three consecutive steps.

The first step is the same undoped vertical superlattice growth step as in the prior art, the second step is a thermal selective etching step, and the third step (J growth step). However, in the second step, the substrate is After forming a thin oxide film on the surface of the substrate by exposing it to the atmosphere, it is returned to the growth chamber and thermally etched.This is the third step to enable selective growth.
OCV I) takes advantage of the fact that the oxide film does not grow.

According to the present invention, the two constituting the superlattice obtained in the first step
The semiconductor layer on one side of the material is selectively etched by sublimation using the difference in vapor pressure, and a semiconductor layer doped with impurities (1ζ-) can be grown in the etched areas, resulting in impurities (1ζ-). It becomes possible to create a vertical superlattice containing layers. In addition, a doping layer is preliminarily provided under the vertical superlattice (for example, vertical LX'!p n l'
-It becomes possible to create a ping superlattice. Furthermore, by changing the configuration of the vertical superlattice and the (11η) configuration of the regrown film, various device structures can be manufactured.

(F) EXAMPLES The present invention will be described in detail below with reference to examples shown in the drawings. Note that this invention is not limited by this. In addition, in FIGS. 1 to 4, the steps of the growth plane where the crystal grows are omitted, and the growth planes are all drawn on the same line.

FIG. 1 shows one lily produced by the manufacturing method of the first embodiment of the present invention (Δ1ΔS) I/? (S i lζ-buG1
ΔS)I/l vertical superlattice.

In FIG. 1, an undoped GaΔS buffer layer +2, (Δ1ΔS)z, (Si
Doped GaAs)l/, vertical superlattices 13 are stacked.

Figures 2 (a) and (b) i;J illustrate the manufacturing process.

As shown in FIG. 2(a), a (001) GaAs substrate +1. J
2I Cointève GaΔS bath layer 12 5Onm
grow up. In the growth of the upper layer vertical superlattice 13', the growth rate +; l: 0.047 nm/s e'c, and l
l11 sources G a (C, H5) a, Δl (C,
I-13: The supply of Ll was alternately switched for 3 sec-4'. The superlattice layer 13' is 0.2 μm
After the growth and exposure to the atmosphere, GaA, which is one of the constituent layers of the superlattice layer 13°, is removed as shown in Figure 2(b).
S layer 13゛a ΔゎH31! ! ' and heat-etch it. In this case, the sublimation temperature of the Δ1ΔS layer is G1ΔS
For example, if the substrate temperature is set to 650°C, only GaAsIi'l'i13°1 will be etched. After that, when a Si-doped CaAs layer is further grown, as shown in FIG.
A doped GλΔS layer 132L is selectively grown with the desired (Δl A s )+z, (aAs on the S i tope).
+tt vertical superlattice I3 is obtained. The reason why GaAs does not grow to Δ1Δsl after thermal etching is as follows.
This is because the extremely thin oxide film on the surface of Δ1ΔS suppresses growth.

FIG. 3 (J (n-GaΔS) 1.1 (p, GaΔS) produced by the manufacturing method of the second embodiment of the present invention
), which is a two-vertical superlattice.

FIG. 4 shows the manufacturing process.

As shown in FIG. 4(a), an S1-doped n-GaAs layer 14° was grown to a thickness of 0.2 μm on the off-tin plate 11, and then
) Grow a two-band single-wave GaAs layer 12 to a thickness of 20 nm. The purpose of growing the undoped layer is to adjust the atomic steps disturbed by the growth of the doped layer. Also, for the purpose of adjusting the disordered atomic steps, about 10
Annealing for 600 min (under 13 sl irradiation)
(left at ℃). Furthermore, (ΔlΔs)l/l(G
a A S ) l/2 vertical superlattice layer 13° with a thickness of 20 nm
grown. Next, after being exposed to the atmosphere for -10 minutes, as shown in Figure 4(b).
As shown in FIG. 3, using the AlAs layer 13b of the superlattice layer as a mask, the GaAs layer is selectively removed by thermal etching down to the underlying n-GaΔ5l14°. Then, as shown in FIG. 3, a desired vertical pn-doped superlattice 14 is produced by growing the entire pGaAS layer 14a in the removed portion.

(G) As described in detail, according to the present invention, a vertical superlattice including an impurity 1-layer can be realized, and devices having various vertical superlattices can be fabricated. It has two great advantages for the industry.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the structure of a vertical superlattice manufactured according to the first embodiment of the present invention, FIGS. 2(a) and (b) are manufacturing process diagrams, and FIG. 3 is a diagram of the present invention An explanatory diagram of the structure of the vertical superlattice created according to the second embodiment of FIG. 2 is an explanatory diagram of a superlattice and its growth process. ++ 12...GyuΔS off crystal plate, 12 Undoped GaAsB. 13-(n-GaΔ5)172(AlΔS)l/
2 vertical superlattice, 13゛ undoped (G2LΔS)
l/II(△lΔS)+zt vertical superlattice, 13a...n-GaΔS superlattice constituent layer, 13゛1.
...Undoped GaAs superlattice constituent layer, +3b...
... Undoped AtΔS superlattice structure layer, 14 ... Vertical pn-doped GaAS superlattice, 14'-n-Ga
As layer. (a)

Claims (1)

[Claims] 1. A vertical superlattice structure is created by crystal-growing two constituent layers made of undoped compound semiconductor material using atomic steps on the surface of a compound semiconductor substrate whose main plane is tilted with respect to a low-index plane. After the compound semiconductor substrate is once exposed to the atmosphere to form a substantially thin oxide film on the surface of the substrate, the vapor pressure difference between the materials of the two constituent layers is reduced. The method is characterized by comprising a step of thermally selectively etching one of the constituent layers by using the method, and a step of selectively growing again a compound semiconductor layer doped with an impurity in the region removed by etching. A method for manufacturing vertical superlattice elements. 2. Utilizing the atomic steps on the surface of a compound semiconductor substrate whose main plane is tilted from the low-index plane, two constituent layers made of an undoped compound semiconductor material are formed on the substrate via a doped layer made of a compound semiconductor. Following the step of crystal growth, the compound semiconductor substrate is once exposed to the atmosphere to form a substantially thin oxide film on the surface of the substrate;
A step of thermally selectively etching one of the constituent layers using the difference in vapor pressure between the materials of the two constituent layers, and further removing the doped layer under the one constituent layer by performing selective thermal etching. A method for manufacturing a vertical superlattice element, comprising the steps of: and subsequently, selectively growing a doping layer different from the doping layer in the doping layer region of the lower layer that has been etched away.