JPH02161513A - Double access controller for magnetic disk device - Google Patents

Abstract

PURPOSE:To obtain a small-scale hardware to be used also for a microcomputer by combining write-only and read-only memory means or the like to be respectively controlled by a master device and a magnetic disk control means to control double access. CONSTITUTION:When a unit address for a magnetic disk device 70 written from the master device 62 to a write-only circuit 2 together with a processing command coincides with a unit address outputted from the magnetic disk control means 1 through a unit address storage means 4, a unit select signal generating means 6 outputs a unit select signal corresponding to the unit address through a unit address comparing means 5. On the other hand, a timing signal is supplied from a tag signal generating means 7 synchronizing with the poling of the device 62 from a receiving means 9 corresponding to the means 1, the read-only memory means 3 for selecting a processing bit and the device 70 to a driving means 13 and a bit signal generating means 8 and a bus bit signal is outputted from the means 8. Thus, the double access control can be attained by the small- scale hardware to be also used for a microcomputer.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a magnetic disk control device, and particularly to a control device for accessing a magnetic disk device that is accessible from two control devices.

(Prior art) Conventionally, as a document regarding this type of device, C0C5TOR
AGE MODULE DRIVE Pub, No.
83322320 (published by Nippon Sheep Easy Co., Ltd.). The case where dual access control systems compete will be described below with reference to this document. As a means for controlling one magnetic disk drive by two magnetic disk control devices, there is a usage right acquisition process (hereinafter referred to as "reservation") for acquiring the usage right of the magnetic disk drive, and a usage right acquisition state. There is a process for releasing usage rights (hereinafter referred to as release) and a process for forcibly acquiring usage rights (hereinafter referred to as priority select) for forcibly acquiring usage rights. The reserve, release, and priority select processes are performed using the interface signals between the magnetic disk device and the magnetic disk control 71 device.
It is controlled by a combination of a unit select signal, a bus bit signal, and a tag signal.

FIG. 14 is a system configuration diagram using a conventional dual access control device for a magnetic disk device. line 7
4.80 respectively have a central processing unit (hereinafter referred to as CPU) 64.66 and a main memory unit (hereinafter referred to as MEM) 65.
67 and magnetic disk controllers 68 and 69 are connected to line 71.
It is connected through ~73.77~79. Further, the magnetic disk control devices 68 and 69 are connected to the magnetic disk device 70 through lines 75 and 76.

FIG. 15 is a block diagram of the magnetic disk control device of FIG. 14. A line 7 connecting the host device 62 consisting of the CPU 64 and MEM 65 and the magnetic disk control device 68
3 is connected to a processing unit 81 for controlling magnetic disks, a control memory 82 for stored microprograms incorporating magnetic disk control procedures, and a magnetic disk device control section 83. Also, between the magnetic disk control device 68 and the magnetic disk device 70, an interface control signal consisting of a unit select tag signal (hereinafter referred to as a USTG signal) that connects the magnetic disk device control unit 83 and the magnetic disk device 70 is sent and received. There is an interface signal line 75 for

Next, the operation will be explained. Reserved and released from the CPU 64 to the magnetic disk control device 68.

When any priority select command is issued, the magnetic disk control device 68 outputs a control signal to the magnetic disk device 70 through the interface signal line 75. Each control signal is directly related to dual access control, the IJsTG signal is a magnetic disk device selection signal, and the unit select 2°~2 is a tag signal of the signal (hereinafter referred to as UNIT 5IELECT26~22 signal). It has become.

UNIT 5ELECT 2° to 22 are signals that designate the magnetic disk device number and have meaning only when the IJsTG signal is valid. The tag 3 signal (hereinafter referred to as TAG3 signal) is the bus bit 9 signal (hereinafter referred to as BIIS BIT 9
The Bus BIT 9 signal specifies a release operation when the TAG3 signal is valid. Unit selected signal (hereinafter UNITSELEC)
The TED signal (hereinafter referred to as the BUSY signal) and the busy signal (hereinafter referred to as the BUSY signal) are used by the magnetic disk device 70 for the USTG signal.
This is the response signal from

FIG. 16 is a time chart showing the reserve and priority select sequence.
There are two cases: the ED signal becomes "1°", that is, the reservation is successful, and the BtlSY signal becomes "11", that is, the magnetic disc device cannot be reserved because it is reserved by another control device. In response to the priority select command, the magnetic disk device is forcibly reserved even if it is reserved by another control device.

FIG. 17 is a time chart showing the release sequence. As shown in this time chart, when the TGA3 signal and BtlS BIT 9 signal are output in response to a release command, the magnetic disk device that has been reserved until now enters the release state. becomes. The reserve, release, and priority select processes described above are functions that are not included in hard disk controller LSIs currently on the market. It was controlled by a microprogram with memory, a control processor, and a sequencer.

(Problems to be Solved by the Invention) However, the device with the above configuration requires firmware control circuits such as a control processor, a sequencer, and a control memory within the magnetic disk control device. However, in a microcomputer system, which is characterized by minimizing the hardware scale and performing most of the control by software, providing a separate firmware control circuit would be beyond the scope of the microcomputer system. Therefore, there is a problem in that a dual access control system for a magnetic disk drive cannot be easily constructed using a microcomputer system.

The present invention eliminates the above-mentioned problem of increased hardware scale, and provides dual access control even for novel combiator systems such as microcomputer systems without providing a firmware control circuit. The purpose of the present invention is to provide a dual access control system for magnetic disk devices that can perform the following functions.

(Means for Solving the Problems) In order to achieve the above object, the dual access control device for a magnetic disk device of the present invention includes a polling signal to the magnetic disk device and a control signal for validating a processing command. a magnetic disk control means that generates a response signal from the magnetic disk device, processes it, and sends it to the host device; and a write-only storage device that stores each code of the processing command and unit address using the timing signal of the host device. , 6) a unit address storage means for storing a unit address spontaneously generated by polling by the disk control means; a unit address comparison means for comparing the unit address from the unit address storage means and the write-only storage means; and a unit address comparison means. a unit select tag signal generating means for outputting a tag signal for validating the unit address when the contents match with the write-only storage means; a receiving means for receiving a response signal from the magnetic disk device; a magnetic disk control means; Tag signal generation means for generating a tag signal from output signals from the dedicated storage means and the reception means; and bus bit signal generation means for generating a bus bit signal from the magnetic disk control means, the write-only storage means, and the tag signal generation means. and a reset signal generating means for resetting the write-only storage means based on the output from the tag signal generation means, and a selection signal for setting a bit indicating whether selection is possible in a predetermined bit of the read-only storage means based on the output signal from the receiving means. generating means; read-only storage means for storing output signals from the write-only storage means and the selection signal generation means; and sampling into the read-only storage means from the output signals of the tag signal generation means and the control signals of the magnetic disk control means. The apparatus includes a sampling signal generation means for generating a signal, and a drive means for generating a drive signal based on the output signals of the unit address storage means, the unit select tag signal generation means, the tag signal generation means, and the bus bit signal generation means. be.

Also, for the same purpose, a magnetic disk control means generates a polling signal to the magnetic disk device and a control signal to enable a processing command, receives a response signal from the magnetic disk device, processes it, and sends it to the host device. a write-only storage means for storing each code of a processing command and a unit address for each unit address using a timing signal from a host device; a unit address storage means for storing a unit address spontaneously generated by polling by the magnetic disk control means; and a unit address. unit select tag signal generating means for outputting a tag signal for validating a unit address according to the contents of the write-only storage means selected by the storage means; receiving means for receiving a response signal from a magnetic disk device; and magnetic disk control means. tag signal generating means for generating a tag signal from the output signals from the write-only storage means and the receiving means; and a bus bit signal for generating a bus bit signal from the magnetic disk control means, the write-only storage means and the tag signal generation means. generating means; reset signal generating means for resetting the write-only storage means based on the output from the tag signal generating means; and setting a bit indicating whether selection is possible in a predetermined bit of the read-only storage means based on the output signal from the receiving means. a selection signal generation means; a read-only storage means for storing output signals from the write-only storage means and the selection signal generation means for each unit address; and an output signal of the tag signal generation means and a control signal of the magnetic disk control means. Sampling signal generation means for generating a sampling signal in the read-only storage means; Driving means for generating a drive signal based on the output signals of the unit address storage means, the unit select tag signal generation means, the tag signal generation means, and the bus bit signal generation means. It is equipped with the following.

(Function) Receives a processing command and a unit address of a magnetic disk device from a host device, stores it in a write-only storage means,
Further, the unit address from the magnetic disk control means is stored in the unit address storage means, and when the unit address in the re-storage means matches, the unit select tag signal generation means generates a unit select tag signal that makes this unit address valid. , the tag signal generation means generates a tag signal from the contents of the magnetic disk control means, the write-only storage means, and the reception means for receiving the response signal of the magnetic disk device, and the magnetic disk control means, the write-only storage means, and the tag signal generation A bus bit is generated by the bus bit signal generation means from each content of the means, and a bus bit is generated by the drive means from the contents of the unit address storage means, unit select tag signal generation means, tag signal generation means, and bus bit signal generation means. Generates a drive signal.

It also receives a processing command and a unit address of the magnetic disk device from the host device and stores them in a write-only storage means provided for each unit address, and stores the unit address from the magnetic disk control means in the unit address storage means. , each content of a receiving means that generates a unit select tag signal according to the contents of the write-only storage means selected by the unit address storage means, and receives response signals from the magnetic disk control means, the write-only storage means, and the magnetic disk device. A tag signal is generated by the tag signal generation means from the contents of the magnetic disk control means, the write-only storage means, and the tag signal generation means, a bus bit is generated by the bus bit signal generation means from the contents of the magnetic disk control means, the write-only storage means, and the tag signal generation means. If the drive means generates a drive signal for the magnetic disk device based on the contents of the signal generation means, the tag signal generation means, and the bus bit signal generation means, the versatility will be further increased.

(Example) Embodiments of the present invention will be described with reference to the drawings.

Note that elements common to each drawing are given the same reference numerals.

11th Pilgrimage ■ Fig. 1 is a block diagram of the dual access control device according to the first embodiment, and Fig. 2 is the first embodiment that exists inside the magnetic disk control device shown in Fig. 14. FIG. 2 is a circuit diagram of a dual access control device of FIG.

First, the correspondence between FIG. 1 and FIG. 2 will be explained.

The magnetic disk control means 1 consists of a hard disk controller LSI 14, and the write-only storage means 2 consists of 8
It consists of a control register 15 dedicated to bit writing. The read-only storage means 3 consists of an 8-bit read-only control register 16. The unit address storage means 4 consists of a 3-bit unit address register 17, and the unit address comparison means 5 consists of a comparator 18 and an inverter 19.
It consists of The unit select tag signal generation means 6 consists of a Nant gate 20 and a NOR gate 21, and the tag signal generation means 7 consists of AND gates 22 and 23 and an OR gate 2.
The bus bit signal generating means 8 consists of OR gates 25 and 26. The receiving means 9 for receiving signals from the magnetic disk includes a receiver 27. The sampling signal generation means 10 of the read-only storage means 3 consists of an AND gate 28, and the reset signal generation means 11 of the write-only storage means 2 consists of a post-differentiation pulse generation circuit 29. The selection signal generating means 12 for setting the fourth and fifth bits from the bottom of the read-only storage means 3 is composed of an AND gate 30 and an inverter 31. The driving means 13 consists of a driver 32.

The host device 62 and magnetic disk device 70 are the same as those in the prior art. In FIG. 2, the signal line 33 is an 8-bit host data bus and is connected to the hard disk controller LS.
I 14. Write-only control register 15. It is connected to a read-only control register 16. The output signal line 34 of the hard disk controller LS114 is connected to a unit address register 17. which holds the address of the magnetic disk device 70 (hereinafter referred to as unit address). Nantes Gate 20. connected to inverter 19, inverter 1
The output signal line 35 of 9 is connected to the comparator 1. The output signal line 36 of the comparator 18 is connected to the NOR game 1-21, and its output signal line 37 is connected to the input of the AND gate 28 and becomes a USTG signal via the driver 32, which is connected to the magnetic disk device 70. There is. The output signal line 3 of the hard disk controller LS114 is
The unit address register 17 consists of 3 bits.
The output signal line 39 of the address register 17 is connected to the comparator 18 and at the same time is connected to the output signal line 39 of the address register 17.
The two signals are connected to the magnetic disk device 70.

Output signal 40 of hard disk controller LS114
is connected to the OR gate 24, and its output signal line 41 is
It becomes a YAG3 signal via the driver 32 and is connected to the magnetic disk device 70.

The output signal line 42 is connected to the AND gates 22 and 28, the output signal line 43 of the AND gate 22 is input to the AND gate 23, and the output signal line 44 is connected to the OR gate 24.
26 and at the same time, the post-differential pulse generation circuit 29
is connected to the output signal line 4 of the post-differential pulse generation circuit 29.
5 is connected to the reset terminal of the control register 15. The output signal wA46 of the AND gate 28 is connected as a data sample clock for the control register 16. The output signal line 47 of the hard disk controller LS114 is connected to the OR gate 25.
8 is further input to the OR gate 26, and its output signal line 49 is connected to the magnetic disk device 70 as a Bus BIT 9 signal via the driver 32. Each bit b2 from bit 2 to bit 0 of control register 15
．．・bl.

The 3 bits of bo are connected to the comparator 1 and the control register 16, and the output signal line 50 of bit b7 is connected to the control register 1.
6 bit b' is connected to the NAND gate 20, and its output signal line 51 is connected to the NOR gate 21. Similarly, the output signal line 52 of bit b6 is connected to the control register I6.
is connected to bit b'4 and AND gate 23.

Further, the output signal line 53 of bit bs is connected to the control register 16.
bit b' of , and is connected to the OR gate 25.

A BUSY (N) signal (N indicates negative polarity) indicating that the magnetic disk device 70 is being used by another control device is received by the receiver 27, and its output signal line 54 is connected to the heart disk controller LS114 and AND gate 30, connected to inverter 31, AND gate 30,
The output signal lines 55 and 56 of the inverter 31 are bits b'4 and bl, respectively.

It is connected to the. Further, the 5ELECTED signal indicating that the magnetic disk device 70 has been selected is sent to the receiver 27.
receives the data, and its output signal line 57 is connected to the hard disk controller LS114 and the AND gates 22 and 30. The receiver 27 receives the READY signal indicating that the magnetic disk device 70 is available for use, and its output signal line 58 is connected to the hard disk controller LS I.
As a result, the output signal line 59 is input to the input side of the READY transition control unit 14a inside the LSI 14, and as a result, the output signal line 59 is connected to the C through the interface as an interrupt signal line to the host device 62.
Connected to PU.

Signal line 6 connected to the set terminal of control register 15
0 and the signal line 61 connected to the enable terminal of the control register 16 are both connected to the CPU.

Next, the meanings of the main structural blocks in the circuit diagram of FIG. 2 will be explained.

The control '8 register 15 is a control register that specifies commands for dual access control of the magnetic disk device 70, and is used by the hard disk controller LS114 to execute commands such as data writing and reading to the magnetic disk device 70. It is designed so that the host program can write commands at will in the so-called idle state.

FIG. 3 is an explanatory diagram of the bit combinations of the write-only control register, and in FIG. 3(a), the type of command is specified by a combination of three bits from bit b to bit b7. Reserve is a command to acquire the right to use a magnetic disk device, Release is a command to release the right to use a magnetic disk device, and Priority Select is a command to release the right to use a magnetic disk device, regardless of whether other control devices are using it. Abort, a command for forcibly acquiring, is a command used to abandon execution of the above three types of commands midway through.

The same figure (b) is UNIT SF! A combination of three bits from bit b0 to bit b2 corresponding to the LECT 2° to 22 signals specifies the device address of the magnetic disk device in which the command is to be executed. The device address that can be specified is #0
Eight types of addresses from ~#7 can be specified. In this example, b4. b3 is unused.

The control register 16 is a register that represents the execution result of the dual access control command of the magnetic disk device, and can be read by the host program when necessary.

FIG. 4 is an explanatory diagram of each bit of the read-only control register. Bits bt to b1° indicate what the executed command was, and the contents of bits b to b of the control register 15 are held immediately after the reserve command is executed. Bit bI4 indicates that the magnetic disk device was able to reserve by executing the reserve command.

Bit b' indicates the state in which the magnetic disk device is reserved by another control device as a result of executing the reserve command (
(also referred to as BUSY).

Bits l, /2 to b'. indicates the target magnetic disk device number of the command execution, and the contents of the control register 15 through b0 are held immediately after the reserve command is executed.

Next, detailed operation of the embodiment will be explained. Figure 5 shows the first
12 is a time chart for explaining the reserve operation of the embodiment, and is a time chart when a reserve command is issued to magnetic disk device number #l. The output signal A of the hard disk controller LS114 is a signal for selecting a magnetic disk device, and is polled at a cycle T when this LSI is in an idle state. The output signal A of the hard disk controller LS114 is input to the unit address register 17, the inverter 19, and the Nant gate 20. The output signal C of the inverter 19 is "0'°
When at level, it acts to enable comparator 18.

The output signal N of the hard disk controller LS114 is a magnetic disk device number designation bit indicating which magnetic disk device should be selected during polling, and consists of 3 bits, and the device number is as shown in FIG. 3 (b). It is encoded and represented in a code similar to the code. Output signal N is sampled at every rising edge of output signal A, held in unit address register 17, and output signal B
becomes. Output signal B is sent via the driver 32 to UNIT 5ELECT 2°~2 which indicates the magnetic disk device number.
It is sent to the magnetic disk device as a z signal.

However, the IINIT5ELECT2'~2'' signal has meaning only when the 115TG signal is valid, and the output signal B is also input to the comparator 18, and the control register 1
The comparator 18 is designed to output an "O" level only when the comparison result matches the contents of the 5th pip) bz-b. Output signals A and B explained above.

C is constantly output as shown in FIG. 5 when the hard disk controller LSI 4 is in an idle state. In such a state, the host program of the CPU controls the control register 15 via the host data bus 33 to output a reserve command for magnetic disk drive number #1 via the signal line 60 at set timing D. Bit b7 becomes °°1°, and the logical product of the Nant gate 20 shown in FIG. 2 is taken to obtain an output signal "0". Here, the set timing D is synchronized with the output signal A by a synchronization circuit (not shown). On the other hand, the output signal of the comparator 18 is also connected to the Nant gate 2.
A comparison match signal level "0" is output at the same timing as the output signal 0, and the AND output signal E of the NOR gate 21 becomes valid.The output signal E is sent to the US via the driver 32.
It becomes a TG signal and is sent to the magnetic disk device. ll5T
The G signal is a tag signal for selecting a magnetic disk device, and when this signal is valid [INIT 5ELECT
The 2° to 22 signals represent the magnetic disk device number. In this example, magnetic disk device number #1 is selected. When magnetic disk device #1 can be reserved, magnetic disk device #1 responds with a 5ELECTED signal, and when magnetic disk device #1 is reserved by another control device, it responds with a B ELECTED signal.
Respond with USY (N) signal. This state is sampled into the control register 16 by an output signal F, which is a sense status (hereinafter referred to as 5STS) signal output from the hard disk controller LSI 14. The meaning of each bit of the control register 16 is as explained in FIG. 3. Note that bit b'4 and focus b'3 are set to be mutually exclusive. On the other hand, at the timing of the output signal F, the hard disk controller LSI 14 has the REA
The DY signal is sampled and the READY transition control unit 14a
When a READY transition occurs, an interrupt signal G is sent to the CPU of the host device 62. In this example, the interrupt is a transition from NOT READY to READY.

After recognizing this interrupt, the CPU of the host device 62 can determine whether or not the magnetic disk device #1 has been reserved by issuing a command to read the contents of the control register 16. When the command to read the control register 16 is executed, the output signal K becomes the "0°" level, and the contents of the control register 16 are changed to the host 1-data bus 33.
is transferred to the CPU through After reserving the magnetic disk device #l through the above procedure, the host data bus 33 is connected to the hard disk controller LS114.
By issuing commands arbitrarily through the magnetic disk device #l, data writing and reading operations can be executed in the magnetic disk device #l.

FIG. 6 is a time chart illustrating the release operation of the first embodiment, and is a time chart when a release command is issued to the magnetic disk drive number #l that is already in the reserved state. When a release command is issued at timing D in the same way as when a reserve command is issued, bit b of the control register 15 changes to level °“l 11
However, bit bh becomes “I 11”,
The logical AND of the AND gate 23 is taken, and the output signal P goes through the OR gate 24 to the "1' degree level and is sent to the magnetic disk drive #1 as the TAG3 signal through the driver 32. Here, the other input signal of the OR gate 24 is One input signal M of the OR gate 25 is always at the "0" level when the hard disk controller LSI 14 is idle.

Similarly, since bit b of the control register 15 is at the "Oo" level, the output signal of the OR gate 25 is at the "0" level, and the output signal from the OR gate 26 is determined from the "I" level of the output signal R of the AND gate 23. The signal ○ becomes “1 ++ level.The output signal O of the OR gate 26 is the driver 3
2 to the 6n disk device #1 as an 8115 BIT 9 signal. As described above, when the TAG3 signal is valid and the BLIS BIT 9 signal is II I 11, the magnetic disk device executes the release operation. At this time, since the response signal for the release operation is not particularly specified, the output signal R of the AND gate 23 is differentiated and the output signal S is generated by the pulse generation circuit 29, and the control register 15 is reset at this timing. As a result, bit b of the control register 15 goes to the "O" level, so that the logical product of the Nant gate 20 cannot be obtained, and as a result, the USTG signal is not output. When the USTG signal is no longer output to the magnetic disk drive, the RIEADY signal is no longer input (not shown here) (and eventually the I?EADY signal changes from READY to NOT READY).
A transition interrupt signal G is generated, and the host program of the CPU can recognize that execution of the release command has been completed.

FIG. 7 is a time chart illustrating the priority select operation of the first embodiment, when a priority select command is issued to a device with a magnetic disk device number #l that has already been reserved by another control device. This is a time chart.

Basically, the function is the same as that of the reserve command, but since bits b and , of the control register 15 are at the “I II level,” the output signal 0 becomes the “1°° level” through the OR gates 25 and 26, and the driver 32 is activated. via Bus B
It is sent to magnetic disk device #1 as an IT9 signal.

When the tlsTG signal is valid and the Bus BIT9 signal is valid, magnetic disk device #1 executes a priority select operation and is reserved for this control device regardless of whether it is used by another control device.

The procedure by which the execution result of the priority select command can be recognized by the host program of the CPU is exactly the same as the procedure described for the reserve command.

Although the abort command is not shown on the time chart, it is issued when giving up without waiting for the execution of the reserve, release, and priority select commands explained above to be completed, or when the command execution does not complete no matter how long. be. Note that the host program is not particularly notified of the execution result of the abort command.

As explained above, by adding a competition circuit with the control B registers 15 and 16 and the hard disk controller LS 114, dual access control of the magnetic disk device becomes possible.

FIG. 8 is a block diagram of the dual access control device according to the second embodiment, and FIG. 9 is a block diagram of the second embodiment, which is present inside the magnetic disk control device shown in FIG. FIG. 2 is a circuit diagram of an example dual access control device.

First, the correspondence between FIG. 8 and FIG. 9 will be explained.

The magnetic disk control means 1 consists of a hard disk controller LSI 14, and the write-only storage means 2 consists of a plurality of 8-bit write-only control registers 15 provided for each unit to be controlled. The read-only storage means 3 comprises a plurality of 8-bit read-only control registers 16 provided for each unit to be controlled. FIG. 10 is a diagram showing the correspondence between unit addresses of the magnetic disk and control registers for writing and reading only. For example, in the case of unit address #0, the corresponding write-only control register is 15a, and the corresponding read-only control register is 16a. The unit address storage means 4 consists of a 3-bit unit address register 17, and the unit select tag signal generation means 6 consists of an AND gate 20. The tag signal generating means 7 is an AND gate 2
The bus bit signal generating means 8 consists of OR gates 25 and 26.

The receiving means 9 for receiving signals from the magnetic disk includes a receiver 27. The sampling signal generation means 10 of the read-only storage means 3 consists of an AND gate 28, and the reset signal generation means 11 of the write-only storage means 2 consists of a post-differentiation pulse generation circuit 29. The selection signal generating means 12 for setting the fourth and fifth bits from the bottom of the read-only storage means 3 consists of an AND gate 30 and an inverter 31. The driving means 13 consists of a driver 32.

Upper device 62. The magnetic disk device 70 is similar to the prior art. In FIG. 9, the signal line 33 is an 8-bit host data bus and is connected to the hard disk controller LS.
I 14. A write-only control register 15 is connected to a read-only control register 16. The output signal line 34 of the hard disk controller LS114 is connected to a unit address register 17. which holds the address of the magnetic disk device 70 (hereinafter referred to as unit address). The output signal line 37 is connected to the AND gate 20, and its output signal line 37 is connected to the input of the AND gate 28, and becomes an ustc signal via the driver 32, and is connected to the magnetic disk device 70. The output signal line 38 of the hard disk controller LS114 is composed of 3 bits and is connected to the unit address register 17, and the output signal line 39 of the address register 17 is connected to each of the write-only control register 15 and the read-only control register 16. At the same time as being connected to the address selector circuit not shown, driver 3
Consists of 3 bits via 2 (INIT 5ELEC↑
2° to 2 becomes a signal and is connected to the magnetic disk device 70.

Output signal line 4 of hard disk controller LS114
0 is connected to the OR gate 24, and its output signal line 41 becomes the TAG3 signal and is connected to the magnetic disk device 70 via the driver 32. The output signal line 42 is connected to the AND gates 22 and 28, the output signal line 43 of the AND gate 22 is input to the AND gate 23, and the output signal line 44 is connected to the OR game 1-24.26. The output signal line 45 of the post-differential pulse generation circuit 29 is connected to the control register 15.
are connected to the reset terminals of the respective control registers 15a to 15h. Output signal line 4 of AND gate 28
6 is connected as a data sample clock for each of the fDII i output registers 16a-16h of the control register 16.

The output signal line 47 of the hard disk controller LSI 14 is connected to the OR gate 25, its output signal line 48 is further input to the OR gate 26, and its output signal line 49 is connected to the Bus BIT 9 via the driver 32.
It is connected to the magnetic disk device 70 as a signal. The output signal line 50 of bit b of control register 15 is bit bJ of control register 16.

and is connected to the AND gate 20. Similarly bit b
, the output signal line 52 of the control l register 16 bit b
'6 and the AND gate 23. Also, beep)
The output signal line 53 of bs is the bit b of the control register 16.
', and are connected to the OR gate 25.

A BUSY (N) signal (N indicates negative polarity) indicating that the magnetic disk device 70 is being used by another control device is received by the receiver 27, and its output signal line 54 is connected to the hard disk controller LSI 14 and the AND gate. 30, connected to the inverter 31, AND gate 30
, output signal lines 55, 56 of inverter 31 are connected to bits b'4 and b'3, respectively. Further, 5ELECTED indicates that the magnetic disk device 70 has been selected.
The signal is received by the receiver 27, whose output signal line 57 is connected to the hard disk controller LSI 14 and the AND gates 22, 30. The receiver 27 receives the READY signal indicating that the magnetic disk drive 70 is available, and its output signal line 58 is connected to the RE! signal inside the LSI of the hard disk controller LS r 14 . A
The signal is input to the input side of the DY transition control unit 14a, and as a result, the output signal line 59 is connected to the CPU via an interface as an interrupt signal line to the host device 62.

Signal line 6 connected to the set terminal of control register 15
0 and the signal line 61 connected to the enable terminal of the control register 16 are both connected to the CPU.

Next, the meanings of the main structural blocks in the circuit diagram of FIG. 9 will be explained.

The control register 15 is a control register that specifies commands for dual access control of the magnetic disk device 70, and the hard disk controller LS114 is not executing commands such as data writing or reading with respect to the magnetic disk device 70. It is designed so that the host program can arbitrarily write commands according to the unit address in the so-called idle state. The combinations of bits written into each of the control registers 15a to 15h of the control register 15 are the same as those shown in FIG.

The control register 16 is a register representing the execution result of the dual access control command of the magnetic disk device, and can be read by the host program when necessary according to the unit address. The explanation of each bit of each control register 16a to 16h of the control register 16 is the same as that shown in FIG.

Next, detailed operation of the embodiment will be explained. Figure 11 shows the second
12 is a time chart for explaining the reserve operation of the embodiment, and is a time chart when a reserve command is issued to magnetic disk device number #l. The output signal A of the hard disk controller LS114 is a signal for selecting a magnetic disk device, and is polled in cycle B, 117 when this LSI is in an idle state. The output signal A of the hard disk controller LS114 is input to the unit address register 17 and the AND gate 20.

The output signal N of the hard disk controller LSI 14 is a magnetic disk device number designation pin indicating which magnetic disk device should be selected during polling;
It consists of 3 bits, and the device number is encoded and expressed in a code similar to the code shown in FIG. 3(b). Output signal N is sampled at every rising edge of output signal A, is held in unit address register 17, and becomes output signal B. Output signal B is sent via the driver 32 to tlNIT5ELHCT, which indicates the magnetic disk device number.
2° to 2 is sent to the magnetic disk device as a signal.

But υ old T 5ELECT 2" ~ 2" signal is U
It has meaning only when the STG signal is valid. Further, the output signal B is input to the control registers 15 and 16, and the control register corresponding to the unit address is selected. Bit b of the selected control register is input to AND gate 20;
When the logic value is "lo", the AND gate 20 outputs the "1" level, that is, the USTG signal. The output signals A and B described above are always output as shown in FIG. 11 when the hard disk controller LS114 is in an idle state. In this situation, CP
When the host program of U outputs a reserve command for magnetic disk device number #l to the control register 15 via the host data bus 33 at set timing D via the signal line 60, the bit of the control register 15b of unit address #1 b.

becomes "1'," and the AND gate 20 shown in FIG. It is synchronized with output signal A. In addition, the unit address specification to the control register 15 of the host and the selection of control registers 15 and 16 by the output signal B of the unit address register 17 are controlled by a competition control circuit (not shown). The output signal E is controlled by the driver 3.
2, it becomes a USTG signal and is sent to the magnetic disk device. The USTG signal is a tag signal for selecting a magnetic disk device, and when this signal is valid, υNIT 5E
The LECT 2° to 22 signals represent the magnetic disk device number. In this example, magnetic disk device number #1 is selected. When magnetic disk device #1 is able to reserve, magnetic disk device #1 responds with a 5ELIICTED signal,
Also, when the magnetic disk device #l is reserved by another control device, it responds with the BIISY (N) signal. This state is sampled in the control register 16b of the unit address #l by the output signal F, which is a sense status (hereinafter referred to as 5STS) signal output from the hard disk controller LS114. The meaning of each bit of the control register 16b is as explained in FIG. 3.

Note that bit b14 and bit b1. is set to be exclusive. On the other hand, in the hard disk controller LSI 14 at the timing of the output signal F, the READY signal is sampled and input to the READY transition control unit 14a, and the RE
If there is an ADY transition, the interrupt signal G is sent to the host device 6.
2 CPLI. In this example, NOT R
This is a transition interrupt from EADY to READY.

After recognizing this interrupt, the CPU of the host device 62 can determine whether or not the magnetic disk device #1 has been reserved by issuing a command to read the contents of the control register 16b.

When the command to read the control register 16b is executed, the output signal K becomes "0" level, and the control register 16b is read.
The contents of the host data bus 33 are transferred to the CPU. After reserving magnetic disk device #l through the above procedure, the hard disk controller LS114
By issuing arbitrary commands to the magnetic disk device #1 via the host data bus 33, data writing and reading operations of the magnetic disk device #l can be executed.

FIG. 12 is a time chart illustrating the release operation of the second embodiment, and is a time chart when a release command is issued to magnetic disk drive number #1 which is already in a reserved state.

When a release command is issued at timing D in the same way as when a reserve command is issued, bit b of the control register 15b remains at level 1'';
becomes "l", the AND gate 23 performs a logical AND operation, and the output signal P goes through the OR gate 24, becomes "1" level, and is sent to the magnetic disk drive #1 as a TAG3 signal through the driver 32. The other input signal of the OR gate 24 and the one input signal M of the OR gate 25 are always at the "0" level when the hard disk controller LS114 is idle. Similarly,
Bit b of control register 15b.

Since the level is "0'", the output signal of the OR gate 25 is u
The output signal O of the OR gate 26 becomes "1" level from the "1" level of the output signal R of the AND gate 23.
1" level. The output signal O of the Aogate 2G is sent to the magnetic disk drive #1 as the Bus BIT 9 signal via the driver 32. In this way, the TAG3 signal is valid and the Bus BIT 9 signal is "l'". When , the magnetic disk drive executes a release operation. At this time, the response signal for the release operation is not particularly specified, so the output signal R of the AND gate 23 is converted into an output signal S by the differential pulse generation circuit 29. At this timing, the control register 15b is reset.As a result, bit b of the control register 15b goes to the "0°° level, so the AND gate 20 cannot perform the logical product, and as a result, the USTG signal is not output."

When the υSTG signal is no longer output to the magnetic disk device, the READY signal is no longer input, although it is not shown here, and eventually the I? EADY to NOT l? EAI
) Y to READY transition interrupt signal G is generated, and the CPU
The host program can recognize that execution of the release command is complete.

FIG. 13 is a time chart illustrating the priority select operation of the second embodiment, when a priority select command is issued to a device with a magnetic disk device number #l that has already been reserved by another control device. This is a time chart. Basically, the function is the same as that of the reserve command, but bit b of the control register 15b is "1".

As a result, the output signal O goes through the OR gates 25 and 26 to the l II level, and goes through the driver 32 as the BIJS BIT 9 signal to the magnetic disk drive #.
sent to l. USTG signal is valid and BIIS
When the BIT 9 signal is valid, magnetic disk device #l executes a priority select operation and is reserved as a zero control n device regardless of whether other control B devices are used. The procedure by which the execution result of the priority select command can be recognized by the host program of the CPU is exactly the same as the procedure described for the reserve command.

Although the abort command is not shown on the time chart, it is issued when giving up without waiting for the execution of the reserve, release, and priority select commands explained above to be completed, or when the command execution does not complete no matter how long. be. Note that the host program is not particularly notified of the execution result of the abort command.

As explained above, by adding a competition circuit with the control registers 15 and 16 and the hard disk controller LS114, dual access control of the magnetic disk device becomes possible.

According to the second embodiment, by providing a control register for each magnetic disk device, command operations such as reserve, release, priority select, and abort can be executed independently for each magnetic disk device. Therefore, this embodiment has higher versatility than the first embodiment.

(Effects of the Invention) Since the present invention is configured as described above, it produces the effects described below.

Dual access control of the magnetic disk device was realized by a combination of a magnetic disk control means, a write-only storage means controlled by a host device, a read-only storage means, and a simple logic circuit, which is difficult to achieve due to hardware scale limitations. Even in small-scale computer systems such as microcomputer systems, shared control of magnetic disk devices can now be carried out cheaply and easily.

Furthermore, the software control method for the two added control registers can be performed in exactly the same format as the software control method for the hard disk controller LSI, so it can be easily applied to systems that do not have dual access control for magnetic disk devices.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of each bit of the double access control bag register according to the first embodiment, Fig. 4 is an explanatory diagram of each bit of the read-only control register, and Fig. 5 is an explanatory diagram of the reserve operation of the first embodiment. 6 is a time chart explaining the release operation of the first embodiment, and FIG. 7 is a time chart explaining the release operation of the first embodiment.
FIG. 8 is a block diagram of the dual access control device according to the second embodiment. FIG. 9 is a circuit diagram of the dual access control device according to the second embodiment. The figure shows the correspondence between unit addresses and write and read-only control registers, No. 11.
FIG. 12 is a time chart explaining the reserve operation of the second embodiment, FIG. 12 is a time chart explaining the release operation of the second embodiment, and FIG. 13 is a time chart explaining the priority select operation of the second embodiment. FIG. 14 is a system configuration diagram using a conventional dual access control device, FIG. 15 is a block diagram of the magnetic disk control device shown in FIG. 14, FIG. 16 is a time chart showing the reserve and priority selection sequence, and FIG. FIG. 17 is a time chart showing the release sequence. l...Magnetic disk control means, 2...Write-only storage means, 3...Read-only storage means, 14...
Hard disk controller LSI, 15... write-only control register, 16... read-only control register, 62.63... host device, 68.69...
- Magnetic disk control device, 70... magnetic disk device. Block diagram of the dual access control device according to the fourth embodiment (Figure 1) (Figure 3: An explanatory diagram of each bit of the ON write-only control renostar; Figure 3: An explanatory diagram of each focus of the read-only control renostar; Figure 1) Figure 5: A time chart explaining the reserve operation of the first embodiment; Figure 5: A time chart explaining the release operation of the first embodiment; Block diagram of the dual access control device according to the second embodiment; Figure 8: Explaining the priority selection operation of the first embodiment. do>
Imchart Correspondence between unit address and write and read-only control recorder Diagram 1o Figure 2 Embodiment Glue P! Time chart for explaining the operation of the second embodiment Time chart for explaining the IJ IJ-S operation of the second embodiment Figure 12 Time chart for explaining the priority select operation for the second embodiment figure

Claims (1)

[Claims] 1. Dual access control of a magnetic disk device in which a plurality of magnetic disk control devices receive processing commands and the unit address of the magnetic disk device from each host device and use the magnetic disk device competitively. In the device, a magnetic disk control device generates a polling signal to the magnetic disk device and a control signal to enable the processing command, receives a response signal from the magnetic disk device, processes it, and sends it to the host device. means; write-only storage means for storing each code of the processing command and unit address in accordance with a timing signal of the host device; unit address storage means for storing a unit address issued by the magnetic disk control means during polling; a unit address comparison means for comparing the unit address from the unit address storage means and the write-only storage means; and a tag for validating the unit address when the contents of the unit address comparison means and the write-only storage means match. unit select tag signal generating means for outputting a signal; receiving means for receiving a response signal from the magnetic disk device; and a tag signal from the output signals from the magnetic disk control means, the write-only storage means, and the receiving means. a bus bit signal generating means for generating a bus bit signal from the magnetic disk control means, the write-only storage means, and the tag signal generating means; and an output signal from the tag signal generating means. a reset signal generating means for resetting the write-only memory means; a selection signal generating means for setting a bit indicating whether selection is possible in a predetermined bit of the read-only memory means in response to an output signal from the receiving means; read-only storage means for storing output signals from the dedicated storage means and the selection signal generation means; sampling signals stored in the read-only storage means from the output signals of the tag signal generation means and the control signals of the magnetic disk control means; a sampling signal generating means for generating a signal; and a driving means for generating a driving signal based on the output signals of the unit address storage means, the unit select tag signal generating means, the tag signal generating means and the bus bit signal generating means. A dual access control device for a magnetic disk device, characterized in that: 2. In a dual access control device for a magnetic disk device in which a plurality of magnetic disk control devices receive processing commands and unit addresses of the magnetic disk device from each host device and use the magnetic disk device in competition, the above-mentioned magnetic disk a magnetic disk control means that generates a polling signal to the device and a control signal that enables the processing command, receives a response signal from the magnetic disk device, processes it, and sends it to the host device; and the processing command and a write-only storage means for storing each code of the unit address in accordance with the unit address of the magnetic disk device using a timing signal from the host device, and a unit address storage means for storing the unit address issued by the magnetic disk control means at the time of polling. unit select tag signal generating means for outputting a tag signal for validating the unit address according to the contents of the write-only storage means selected by the unit address storage means; and receiving a response signal from the magnetic disk device. a tag signal generation means for generating a tag signal from output signals from the magnetic disk control means, the write-only storage means, and the reception means; the magnetic disk control means, the write-only storage means, and the bus bit signal generating means for generating a bus bit signal from the tag signal generating means; reset signal generating means for resetting the write-only storage means from the output signal from the tag signal generating means; and an output signal from the receiving means. a selection signal generation means for setting a bit indicating whether or not selection is possible in a predetermined bit of the read-only storage means; and output signals from the write-only storage means and the selection signal generation means to a unit address of the magnetic disk device. a read-only storage means for storing data according to the unit address; a sampling signal generation means for generating a sampling signal in the read-only storage means from an output signal of the tag signal generation means and a control signal of the magnetic disk control means; A dual magnetic disk drive characterized in that it is provided with a storage means, a unit select tag signal generation means, a drive means for generating a drive signal based on the output signals of the tag signal generation means and the bus bit signal generation means. Access control device.