JP2539050B2 - Dual access control device for magnetic disk unit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a magnetic disk controller, and more particularly to a controller for accessing a magnetic disk device accessible from two controllers.

(Prior Art) Conventionally, CDC STORAGE has been used as a document regarding this type of device.
MODULE DRIVE Pub. No.83322320 (issued by Nippon CDC Co., Ltd.) is available. The case where the dual access control systems compete will be described below with reference to this document. As means for controlling one magnetic disk device by two magnetic disk control devices, a usage right acquisition process for acquiring the usage right of the magnetized disk device (hereinafter referred to as reserve), and release of the usage right acquisition state There is a usage right release process (hereinafter referred to as a release) for performing a forced usage right acquisition process (hereinafter referred to as a priority select). Each process of reserve, release, and priority select is controlled by a combination of a unit select signal, a bus bit signal, and a tag signal among interface signals between the magnetic disk device and the magnetic disk control device.

FIG. 14 is a system configuration diagram using a dual access control device of a magnetic disk device according to the prior art. Line 7
Central processing units (hereinafter referred to as CPUs) 64 and 66 are provided in 4,80, respectively.
Main memory devices (hereinafter referred to as MEM) 65 and 67 and magnetic disk control devices 68 and 69 are connected through lines 71 to 73 and 77 to 79. The magnetic disk control devices 68 and 69 are connected to the magnetic disk device 70 by lines 75 and 76.

FIG. 15 is a block diagram of a control device for the magnetic disk of FIG. A line 73 connecting the host device 62 including the CPU 64 and MEM 65 and the magnetic disk control device 68 has a processing unit 81 for controlling the magnetic disk, a stored microprogram control memory 82 incorporating a magnetic disk control procedure, and a magnetic disk device. It is connected to the control unit 83. Further, the magnetic disk control device 68 and the magnetic disk device 70
There is an interface signal line 75 for transmitting and receiving an interface control signal such as a unit select tag signal (hereinafter referred to as a USTG signal) connecting the magnetic disk device control unit 83 and the magnetic disk device 70.

Next, the operation will be described. When the CPU 64 issues a reserve release command or a priority select command to the magnetic disk controller 68, the magnetic disk controller 68 outputs a control signal to the magnetic disk device 70 through the interface signal line 75. Each control signal is a signal directly related to dual access control,
TG signal is a magnetic disk device selection signals, and has a tag signal units select 2 ^{0-2 2} signal (hereinafter referred to as UNIT SELECT2 ^{0-2 2} signal). UNIT SELECT2 ⁰ to 2 ² is meaningful only when a USTG signal is valid by a signal designating the magnetic disk device number. The tag 3 signal (hereinafter referred to as TAG3 signal) is a tag signal of a bus bit 9 signal (hereinafter referred to as BUS BIT 9 signal), and the BUS BIT 9 signal specifies a release operation when the TAG 3 signal is valid. The unit selected signal (hereinafter referred to as UNIT SELECTED signal) and the busy signal (hereinafter referred to as BUSY signal) are response signals from the magnetic disk device 70 to the USTG signal.

FIG. 16 is a time chart showing the reserve and priority select sequences. For the reserve command, when the SELECTED signal becomes “1” depending on the state of the magnetic disk device, that is, when reserve is possible and when BUSY
There is a case where the signal becomes "1", that is, a case where the magnetic disk device cannot be reserved because it is reserved by another control device. The priority select command is forcibly reserved even if the magnetic disk device is reserved by another control device.

Fig. 17 is a time chart showing the release sequence. When the TGA3 signal and BUS BIT 9 signal are output in response to the release command as shown in this time chart, the magnetic disk device that had been reserved until now is in the released state. Becomes Each of the reserve, release, and priority select processes described above is a function that is not provided in the hard disk controller LSI currently on the market at present, so conventionally it is controlled in the magnetic disk controller as shown in FIG. It was performed by microprogram control with a memory, a control processor, and a sequencer.

(Problems to be Solved by the Invention) However, the apparatus having the above configuration requires a firmware control circuit such as a control processor, a sequencer, and a control memory in the magnetic disk control apparatus. By the way, in a microcomputer system characterized in that the hardware scale is minimized and most of the control is performed by software, providing a separate firmware control circuit goes beyond the area of the microcomputer system. Therefore, there is a problem that the dual access control system of the magnetic disk device cannot be easily constructed in the microcomputer system.

The present invention eliminates the above-mentioned problem of increasing the hardware scale, and enables dual access control even for a small computer system such as a microcomputer system without providing a firmware control circuit. An object of the present invention is to provide a dual access control system for a magnetic disk device.

(Means for Solving the Problems) In order to achieve the above object, in a dual access control device for a magnetic disk device of the present invention, a polling signal to the magnetic disk device and a control signal for validating a processing command are provided. A magnetic disk controller that receives a response signal from the magnetic disk device, processes it, and sends it to a higher-level device; stores the processing command and unit address received from the higher-level device; Storage means for storing, comparison means for comparing the unit address and the polled address stored in the storage means, and a unit select tag signal generation for generating a unit select free signal by the processing command indicating a match of the comparison result and a reserve request Means and the selected state and Tag signal generating means for generating a tag signal by the processing command indicating a release request, bus bit signal generating means for generating a bus bit signal from the processing command and tag signal generating means indicating a release request, and a unit select tag signal And a drive unit for generating a drive signal for reserving the magnetic disk device by a signal indicating a unit address and releasing the magnetic disk device by a tag signal and a bus bit signal.

(Operation) The processing command and the unit address of the magnetic disk device are received from the host device and stored in the storage means, and the unit address from the magnetic disk control means is stored in the unit address storage means. When they match, the unit select tag signal generating means generates a unit select tag signal for validating this unit address and reserves it, and when it is reserved, it receives a release request and generates a tag signal. A bus bit signal is generated based on the tag signal, and the tag signal and the bus bit signal are used for release.

(Example) An example of the present invention will be described with reference to the drawings. Elements common to the drawings are denoted by the same reference numerals.

First Embodiment FIG. 1 is a block diagram of a dual access control apparatus according to the first embodiment, and FIG. 2 is a first embodiment which exists inside the magnetic disk control apparatus shown in FIG. 3 is a circuit diagram of the dual access control device of FIG.

 First, the correspondence between FIG. 1 and FIG. 2 will be described.

The magnetic disk control means 1 comprises a hard disk controller LSI 14, and the write-only storage means 2 comprises an 8-bit write-only control register 15. The read-only storage means 3 comprises an 8-bit read-only control register 16. The unit address storage means 4 comprises a unit address register 17 for 3 bits, and the unit address comparison means 5 comprises a comparator 18 and an inverter 19. The unit select tag signal generating means 6 comprises a NAND gate 20 and a NOR gate 21, the tag signal generating means 7 comprises AND gates 22 and 23 and an OR gate 24, and the bus bit signal generating means 8 comprises OR gates 25 and 26. The receiving means 9 for receiving the signal from the magnetic disk comprises a receiver 27. The sampling signal generating means 10 of the read-only storage means 3 comprises an AND gate 28, and the reset signal generating means 11 of the write-only storage means 2 is a post-differential pulse generation circuit.
It consists of 29. The selection signal generating means 12 for setting the 4th and 5th bits from the bottom of the read-only storage means 3 comprises an AND gate 30 and an inverter 31. The driving means 13 comprises a driver 32. The host device 62 and the magnetic disk device 70 are similar to those of the conventional technique. In FIG. 2, the signal line 33 is an 8-bit host data bus and is connected to the hard disk controller LSI 14, the write-only control register 15, and the read-only control register 16. The output signal line 34 of the hard disk controller LSI 14 is the magnetic disk device 7
It is connected to a unit address register 17, which holds an address of 0 (hereinafter referred to as a unit address), a NAND gate 20, and an inverter 19, and an output signal line 35 of the inverter 19 is connected to a comparator 18. The output signal line 36 of the comparator 18 is connected to the NOR gate 21, and the output signal line 37 of the comparator 18 is connected to the input of the AND gate 28 and the US via the driver 32.
It becomes a TG signal and is connected to the magnetic disk device 70. The output signal line 38 of the hard disk controller LSI 14 is 3
It is composed of bits and is connected to the unit address register 17, and the output signal line 39 of the address register 17 is a comparator.
When connected to a 18 comprising three bits via a driver 32 simultaneously UNIT SELECT2 ⁰ to 2 ² signal becomes magnetic disk device 7
Connected to 0.

The output signal 40 of the hard disk controller LSI 14 is connected to the OR gate 24, and its output signal line 41 is a driver.
It becomes a YAG3 signal via 32 and is connected to the magnetic disk device 70. The output signal line 42 is connected to the AND gates 22 and 28, and the output signal line 43 of the AND gate 22 is an AND gate.
23, and its output signal line 44 is connected to the OR gates 24 and 26, and at the same time, connected to the post-differential pulse generation circuit 29, and the output signal line 45 of the post-differential pulse generation circuit 29 is the reset terminal of the control register 15. Connected to. And gate
28 output signal lines 46 are connected as the data sample clock of the control register 16. The output signal line 47 of the hard disk controller LSI 14 is connected to the OR gate 25, the output signal line 48 is further input to the OR gate 26, and the output signal line 49 is connected to the BUS BIT via the driver 32.
It is connected to the magnetic disk device 70 as 9 signals.
Bits 2 to 0 of control register 15
The three bits b ₂ , b ₁ and b ₀ are connected to the comparator 18 and the control register 16, and the output signal line 50 of b ₇ is connected to the bit b ′ ₇ of the control register 16 and the NAND gate 20 and its output signal line 51
Is connected to NOR gate 21. Output signal lines 52 of the bit b ₆ similarly is connected to a bit b _'6 and the AND gates 23 of the control register 16. Also, the output signal line of bit b ₅
53 is connected to a bit b _'5 and the OR gate 25 of the control register 16.

BUSY (N) signal indicating that the magnetic disk device 70 is being used by another control device (N indicates a negative polarity)
Receives the receiver 27, the output signal line 54 is connected to the hard disk controller LSI 14 and the AND gate 30, an inverter 31, AND gates 30, each output signal line 55, 56 of the inverter 31 bit b _'4 and b It is connected to ' ₃ . Further, the SELECTED signal indicating that the magnetic disk device 70 has been selected is received by the receiver 27, and its output signal line 57 is connected to the hard disk controller LSI 14 and the AND gates 22 and 30. Magnetic disk unit 70
Is received by the receiver 27, and its output signal line 58 is input to the input side of the READY transition control unit 14a inside the LSI of the hard disk controller LSI 14, and as a result, the output signal line 59 is higher. It is connected to the CPU via an interface as an interrupt signal line to the device 62.

Signal line 60 connected to the set terminal of control register 15
The signal line 61 connected to the enable terminal of the control register 16 is also connected to the CPU.

Next, the meaning of main constituent blocks of the circuit diagram of FIG. 2 will be described.

The control register 15 is a control register that specifies a command for dual access control of the magnetic disk device 70.
In the so-called idle state in which commands such as data writing and reading are not executed, the host program can arbitrarily write commands.

FIG. 3 is an explanatory diagram of bit combinations of the write-only control register. In FIG. 3 (a), the command type is designated by a combination of 3 bits from bit b ₅ to bit b ₇ . Reserve is a command for acquiring the right to use the magnetic disk device, Release is a command for releasing the right to use the magnetic disk device, and Priority Select is the right to use the magnetic disk device regardless of whether other control devices are used. The command for forcibly acquiring, abort is a command used when giving up the execution of the above-mentioned three types of commands on the way.

FIG (b) specifies the device address of the magnetic disk apparatus to execute a 3 bit combinations command from bits b ₀ that correspond to UNIT SELECT2 ⁰ to 2 ² signal to bit b _2. Eight types of addresses, # 0 to # 7, can be specified as device addresses. In this example b _4, b ₃ it is unused. The control register 16 is a register indicating the execution result of the dual access control command of the magnetic disk device, and can be read by the host program when necessary.

FIG. 4 is an explanatory diagram of each bit of the read-only control register. The _'7 bit b' bit b until ₅ indicates whether run command was doing, the contents of bit b ₇ ~b ₅ of the control register 15 immediately after execution reserve command is held. Bit b _'4 indicates that the magnetic disk device is able to reserve the execution of the reserve command. Bit b _'3 indicates that the magnetic disk apparatus which is a result of the execution of the reservation command, (also referred to in the BUSY) state are reserved for other control device. Bit b _'2 ~b'
₀ indicates the target magnetic disk device number for command execution, and b ₂ to b in the control register 15 immediately after executing the reserve command.
The contents of b ₀ are retained.

Next, the detailed operation of the embodiment will be described. FIG.
7 is a time chart for explaining a reserve operation of the embodiment, which is a time chart when a reserve command is issued to the magnetic disk device number # 1. The output signal A of the hard disk controller LSI 14 is a signal for selecting the magnetic disk device, and polls at a cycle T when the present LSI is in the idle state. The output signal A of the hard disk controller LSI 14 is input to the unit address register 17, the inverter 19, and the NAND gate 20.
When the output signal C of the inverter 19 is at "0" level, the comparator 18
Act to enable.

The output signal N of the hard disk controller LSI14 is
This is a magnetic disk device number designating bit indicating which magnetic disk device should be selected at the time of polling, and is composed of 3 bits. The device number is coded into a code similar to the code shown in FIG. It is represented. The output signal N is sampled at every rising edge of the output signal A,
It is held in the unit address register 17 and becomes the output signal B. The output signal B is sent to the magnetic disk device as a UNIT SELECT2 ⁰ to 2 ² signal indicating magnetic disk device number via the driver 32. However UNIT SELECT2 ⁰ to 2 ² signal is relevant only when USTG signal is active, and the output signal B is also input to the comparator 18, the bit of the control register 15
b ₂ ~b comparator 18 only when comparer results compared with the contents match ₀ and outputs a "0" level. The output signals A, B, C described above are always output as shown in FIG. 5 when the hard disk controller LSI 14 is in the idle state. In such a state, when the host program of the CPU outputs a reserve command for the magnetic disk device number # 1 to the control register 15 via the host data bus 33 at the set timing D through the signal line 60, the bit of the control register 15 is changed. b ₇ becomes “1” and second
Output signal “0” after logical product of NAND gate 20 shown
Get. Here, the set timing D is synchronized with the output signal A by a synchronizing circuit (not shown). On the other hand, the output signal of the comparator 18 also outputs the comparison match signal level "0" at the same timing as the output signal of the NAND gate 20, and the logical product output signal E of the NOR gate 21 becomes effective. The output signal E becomes a USTG signal via the driver 32 and is sent to the magnetic disk device. The USTG signal is a tag signal for selecting the magnetic disk device. UNIT SEL when this signal is valid
ECT2 ⁰ to 2 ² signal represents a magnetic disk device number. In the case of this example, the magnetic disk device number # 1 is selected. When the magnetic disk device # 1 can be reserved, the magnetic disk device # 1 responds with a SELECTED signal, and the magnetic disk device # 1
When 1 is reserved for other control devices, BUSY (N)
Respond with a signal. This state is the sense status (hereinafter SSTS) output from the hard disk controller LSI14.
The output signal F, which is a signal), is sampled in the control register 16. The meaning of each bit of the control register 16 is as described in FIG. Bit b '
₄ bit b _'3 is set at mutually exclusive. On the other hand, at the timing of the output signal F, the READY signal is sampled to the hard disk controller LSI 14 and input to the READY transition control unit 14a. When there is a READY transition, the interrupt signal G is sent to the CPU of the host device 62. . In this example, NOT REA
Transition interrupt from DY to READY.

The CPU of the host device 62 can recognize whether or not the magnetic disk device # 1 can be reserved by issuing a command for reading the contents of the control register 16 after recognizing this interrupt. When the command for reading the control register 16 is executed, the output signal K becomes "0" level, and the contents of the control register 16 are transferred to the CPU through the host data bus 33. After reserving the magnetic disk device # 1 by the above procedure, the hard disk controller LSI14
It is possible to execute the data writing and reading operations of the magnetic disk device # 1 by arbitrarily issuing a command via the host data bus 33.

FIG. 6 is a time chart for explaining the release operation of the first embodiment, and is a time chart when the release command is issued to the magnetic disk device number # 1 which is already in the reserved state. When a release command is issued at the timing D as in the case of issuing a reserve command, the level of bit b ₇ of the control register 15 remains “1”, but bit b ₆ is newly set to “1” and the AND gate 23 Is obtained and the output signal P becomes "1" level via the OR gate 24 and is sent to the magnetic disk device # 1 as the TAG3 signal via the driver 32. The other input signal L of the OR gate 24 and one input signal M of the OR gate 25 are always at "0" level when the hard disk controller LSI 14 is idle. Similarly, the control register
Since the bit b ₅ of 15 is “0” level, the output signal of the OR gate 25 becomes “0” level, and the output signal O of the OR gate 26 becomes “1” level from the “1” level of the output signal R of the AND gate 23. . The output signal O of the OR gate 26 is sent to the magnetic disk device # 1 as a BUS BIT 9 signal via the driver 32. Thus, when the TAG3 signal is valid and the BUS BIT 9 signal is "1", the magnetic disk device executes the release operation. At this time, since the response signal to the release operation is not specified in particular, the output signal S of the AND gate 23 is generated by the post-differential pulse generation circuit 29, and the control register 15 is reset at this timing. As a result, bit b ₇ of the control register 15 becomes the “0” level, and the logical product of the NAND gate 20 cannot be obtained.
The TG signal is no longer output. When the USTG signal is no longer output to the magnetic disk device, READ
Y signal is not input and finally READY to NOT READ
When the READY transition interrupt signal G to Y is generated, the host program of the CPU can recognize that the execution of the release command is completed.

FIG. 7 is a time chart for explaining the priority select operation of the first embodiment. In the case where the priority select command is issued to the device of the magnetic disk device number # 1, which is already reserved by another control device. It is a time chart. The function is basically the same as that of the reserve command, but since the bit b ₅ of the control register 15 is at “1” level, the output signal O becomes “1” level via the OR gates 25 and 26 and via the driver 32. BUS BIT
9 signals are sent to the magnetic disk device # 1. When the USTG signal is valid and the BUS BIT 9 signal is valid, the magnetic disk device # 1 executes the priority select operation, and is reserved by this control device regardless of whether or not another control device is used. The procedure by which the execution result of the priority select command can be recognized by the host program of the CPU is exactly the same as the procedure described for the reserve command.

Although the abort command is not shown in the time chart, it is issued when the execution of the reserve, release, or priority select command explained above is abandoned without waiting, or when the command execution is not completed forever. is there. The execution result of the abort command is not notified to the host program.

As described above, by adding a competing circuit with the control registers 15 and 16 and the hard disk controller LSI 14, double access control of the magnetic disk device becomes possible.

Second Embodiment FIG. 8 is a block diagram of a dual access control device according to the second embodiment, and FIG. 9 is a second embodiment which exists inside the magnetic disk control device shown in FIG. 3 is a circuit diagram of the dual access control device of FIG.

 First, the correspondence between FIG. 8 and FIG. 9 will be described.

The magnetic disk control means 1 comprises a hard disk controller LSI 14, and the write-only storage means 2 comprises a plurality of 8-bit write-only control registers 15 provided for each unit to be controlled. Read-only storage means 3
Is composed of a plurality of 8-bit read-only control registers 16 provided for each unit to be controlled. FIG. 10 is a correspondence diagram between the unit address of the magnetic disk and the write / read-only control register. For example, in the case of unit address # 0, the corresponding write-only control register is
15a, indicating that the read-only control register is 16a. The unit address storing means 4 comprises a unit address register 17 for 3 bits, and the unit select tag signal generating means 6 comprises an AND gate 20. The tag signal generating means 7 comprises AND gates 22 and 23 and an OR gate 24, and the bus bit signal generating means 8 comprises OR gates 25 and 26. The receiving means 9 for receiving the signal from the magnetic disk comprises a receiver 27. Read-only storage means 3
The sampling signal generating means 10 comprises an AND gate 28, and the reset signal generating means 11 of the write-only storage means 2
Is composed of a post-differential pulse generation circuit 29. The selection signal generating means 12 for setting the 4th and 5th bits from the bottom of the read-only storage means 3 comprises an AND gate 30 and an inverter 31. The driving means 13 comprises a driver 32. Host device 62,
The magnetic disk device 70 is similar to the conventional technique. In FIG. 9, the signal line 33 is an 8-bit host data bus and is connected to the hard disk controller LSI 14, the write-only control register 15 and the read-only control register 16. Output signal line 3 of hard disk controller LSI14
4 is a unit address register 17, which holds an address (hereinafter referred to as a unit address) of the magnetic disk device 70,
It is connected to the AND gate 20, and its output signal line 37 is connected to the input of the AND gate 28 and also becomes a USTG signal via the driver 32 and is connected to the magnetic disk device 70. Output signal line 38 of hard disk controller LSI 14
Is a unit address register consisting of 3 bits
The output signal line 39 of the address register 17 connected to
Magnetic disk drive 70 becomes UNIT SELECT2 ⁰ to 2 ² signal consisting of three bits via a write-only control registers 15 and read-only each when connected to not shown address selector circuit simultaneously driver 32 of the control register 16 of the
Connected to

The output signal line 40 of the hard disk controller LSI 14 is connected to the OR gate 24, and the output signal line 41 of the hard disk controller LSI 14 becomes a TAG3 signal via the driver 32 and is connected to the magnetic disk device 70. The output signal line 42 is connected to the AND gates 22 and 28, the output signal line 43 of the AND gate 22 is input to the AND gate 23, and the output signal line 44 is connected to the OR gates 24 and 26, and at the same time, the post-differentiation is performed. The output signal line 45 of the post-differential pulse generation circuit 29 is connected to the pulse generation circuit 29, and is connected to the reset terminals of the respective control registers 15a to 15h of the control register 15. Output signal line 46 of AND gate 28
Are control registers 16a to 16h of the control register 16 respectively.
Connected as the data sample clock of. The output signal line 47 of the hard disk controller LSI 14 is connected to the OR gate 25, the output signal line 48 thereof is further input to the OR gate 26, and the output signal line 49 thereof is passed through the driver 32 as a BUS BIT 9 signal to the magnetic disk device. Connected to 70. Control register 15 bit b ₇ output signal line
50 is connected to a bit b _'7 and the AND gates 20 of the control register 16. Similarly the output signal line 52 of the bit b ₆ to the now connected to the bit b _'6 and the AND gates 23 of the control register 16. The output signal line 53 of the bit b ₅ is connected to a bit b _'5 and the OR gate 25 of the control register 16.

BUSY (N) signal indicating that the magnetic disk device 70 is being used by another control device (N indicates a negative polarity)
Receives the receiver 27, the output signal line 54 is connected a hard disk controller LSI14 and AND gate 30, an inverter 31, AND gates 30, each output signal line 55 and 56 bits b of the inverter 31 _'4 and b' Connected to ₃ . Further, the SELECTED signal indicating that the magnetic disk device 70 has been selected is received by the receiver 27, and its output signal line 57 is connected to the hard disk controller LSI 14 and the AND gates 22 and 30. Magnetic disk unit 70
Is received by the receiver 27, and its output signal line 58 is input to the input side of the READY transition control unit 14a inside the LSI of the hard disk controller LSI 14, and as a result, the output signal line 59 is higher. It is connected to the CPU via an interface as an interrupt signal line to the device 62.

Signal line 60 connected to the set terminal of control register 15
The signal line 61 connected to the enable terminal of the control register 16 is also connected to the CPU.

Next, the meaning of main constituent blocks of the circuit diagram of FIG. 9 will be described.

The control register 15 is a control register that specifies a command for dual access control of the magnetic disk device 70.
In the so-called idle state in which commands such as data writing and reading are not executed, the host program can arbitrarily write commands according to the unit address. The combinations of bits written in the control registers 15a to 15h of the control register 15 are the same as those shown in FIG.

The control register 16 is a register indicating the execution result of the dual access control command of the magnetic disk device, and can be read by the host program when necessary according to the unit address. Each control register 16 of the control register 16
The description of each bit of a to 16h is the same as that shown in FIG.

Next, the detailed operation of the embodiment will be described. Figure 11 shows the second
7 is a time chart for explaining a reserve operation of the embodiment, which is a time chart when a reserve command is issued to the magnetic disk device number # 1. The output signal A of the hard disk controller LSI 14 is a signal for selecting the magnetic disk device, and polls at a cycle T when the present LSI is in the idle state. The output signal A of the hard disk controller LSI 14 is input to the unit address register 17 and the AND gate 20.

The output signal N of the hard disk controller LSI14 is
This is a magnetic disk device number designation bit indicating which magnetic disk device should be selected at the time of polling, and is composed of 3 bits. The device number is coded into a code similar to the code shown in FIG. It is represented. The output signal N is sampled at every rising edge of the output signal A,
It is held in the unit address register 17 and becomes the output signal B. The output signal B is sent to the magnetic disk device as a UNIT SELECT2 ⁰ to 2 ² signal indicating magnetic disk device number via the driver 32. However UNIT SELECT2 ⁰ ~2 ² signal has a meaning only when USTG signal is valid. The output signal B is also input to the control registers 15 and 16 to select the control register according to the unit address. Bit b ₇ of the selected control register is input to the AND gate 20, the AND gate 20 when the logical value "1" and outputs a "1" level i.e. USTG signal. Output signals A and B described above
Is always output as shown in FIG. 11 when the hard disk controller LSI 14 is in the idle state.
In such a state, when the CPU host program outputs a reserve command for the magnetic disk device number # 1 to the control register 15 through the host data bus 33 at the set timing D through the signal line 60, the unit address # 1 is output. bit b ₇ is "1" in the control register 15b, the first 13 logical product to obtain the output signal "1" Tore output signal of the aND gate 20 shown in Figure E becomes valid. Here, the set timing D is synchronized with the output signal A by a synchronizing circuit (not shown). The unit address designation to the control register 15 of the host and the selection of the control registers 15 and 16 by the output signal B of the unit address register 17 are controlled by a competition control circuit (not shown). The output signal E becomes a USTG signal via the driver 32 and is sent to the magnetic disk device. The USTG signal is a tag signal for selecting the magnetic disk device, and is the UN when this signal is valid.
IT SELECT2 ⁰ to 2 ² signal represents a magnetic disk device number. In the case of this example, the magnetic disk device number # 1 is selected. When the magnetic disk device # 1 can be reserved, the magnetic disk device # 1 responds with a SELECTED signal, and when the magnetic disk device # 1 is reserved by another control device,
Respond with BUSY (N) signal. This state is sampled in the control register 16b of the unit address # 1 by the output signal F which is a sense status (hereinafter referred to as SSTS) signal output from the hard disk controller LSI14.
The meaning of each bit of the control register 16b is as described in FIG. Incidentally bit b _'4 and bit b' ₃
Is set by ban. On the other hand, at the timing of the output signal F, the hard disk controller LSI 14 samples the READY signal and inputs it to the READY transition control unit 14a,
If there is a transition, the interrupt signal G is the CPU of the host device 62.
Sent to In the case of this example, it is a transition interrupt from NOT READY to READY.

After recognizing this interrupt, the CPU of the host device 62 can know whether or not the magnetic disk device # 1 can be reserved by issuing a command to read the contents of the control register 16b. When the command for reading the control register 16b is executed, the output signal K becomes "0" level, and the contents of the control register 16b are transferred to the CPU via the host data bus 33.
Transferred to According to the above procedure, the magnetic disk device #
After reserving 1, the hard disk controller LS
By arbitrarily issuing a command to I14 via the host data bus 33, it becomes possible to execute the data write / read operation of the magnetic disk device # 1.

FIG. 12 is a time chart for explaining the release operation of the second embodiment, and is a time chart when the release command is issued to the magnetic disk device number # 1 which is already in the reserved state. When a release command is issued at the timing D as in the case of issuing the reserve command, the level of the bit b ₇ of the control register 15b remains “1”, but the bit b ₆ is newly set to “1”, and the AND gate 23 Is obtained and the output signal P becomes "1" level via the OR gate 24 and is sent to the magnetic disk device # 1 as the TAG3 signal via the driver 32. The other input signal L of the OR gate 24 and one input signal M of the OR gate 25 are always at "0" level when the hard disk controller LSI 14 is idle. Similarly, since the bit b ₅ of the control register 15b is “0” level, the output signal of the OR gate 25 becomes “0” level, and the output signal O of the OR gate 26 becomes “1” level from the output signal R of the OR gate 26. 1 "
Level. The output signal O of the aogate 26 is the driver 32.
Magnetic disk device # 1 as BUS BIT 9 signal via
Sent to. In this way, the TAG3 signal is valid and the BUS BIT
When the 9 signal is "1", the magnetic disk device executes the release operation. At this time, the response signal to the release operation is not specified in particular, so that the output signal R of the AND gate 23 is output by the post differential pulse generation circuit 29.
Is generated and the control register 15b is reset at this timing. As a result, the bit b ₇ of the control register 15b becomes the "0" level, and the AND gate 20 cannot obtain the logical product. As a result, the USTG signal is not output. When the USTG signal is not output to the magnetic disk device, the READY signal is not input and the READY transition interrupt signal G from READY to NOT READY is finally generated, although not shown here, and the CPU
The host program can recognize that the release command has been executed.

FIG. 13 is a time chart for explaining the priority select operation of the second embodiment, in the case where the priority select command is issued to the device of the magnetic disk device number # 1, which is already reserved by another control device. It is a time chart. Bit b ₅ fundamentally but is the same as the action of the reserve command control register 15b is "1"
Since it is at the level, the output signal O becomes "1" level via the OR gates 25 and 26, and the BUS BIT goes through the driver 32.
9 signals are sent to the magnetic disk device # 1. USTG
When the signal is valid and the BUS BIT 9 signal is valid, the magnetic disk device # 1 executes the priority select operation, and is reserved by this control device regardless of whether or not another control device is used. The procedure by which the execution result of the priority select command can be recognized by the host program of the CPU is exactly the same as the procedure described for the reserve command.

Although the abort command is not shown in the time chart, it is issued when the execution of the reserve, release, or priority select command explained above is abandoned without waiting, or when the command execution is not completed forever. is there. The execution result of the abort command is not notified to the host program.

As described above, by adding a competing circuit with the control registers 15 and 16 and the hard disk controller LSI 14, double access control of the magnetic disk device becomes possible.

According to the second embodiment, by providing the control register for each magnetic disk device, the reserve, release, priority select, and abort command operations can be independently executed for each magnetic disk device. Therefore, the versatility is higher than that of the first embodiment.

(Effects of the Invention) Since the present invention is configured as described above, it has the effects described below.

Since the dual access control of the magnetic disk device was realized by the combination of the magnetic disk control means, the storage means controlled by the host device, and the simple logic circuit, it was difficult to realize it because of the limitation of the hardware scale. Even in a small-scale computer system, shared control of a magnetic disk device can be carried out inexpensively and easily.

Further, the software control method of the two added control registers can be performed in exactly the same format as the software control method of the hard disk controller LSI, so that it can be easily applied to a system having no dual access control of the magnetic disk device.

[Brief description of drawings]

FIG. 1 is a block diagram of a dual access control device according to the first embodiment, FIG. 2 is a circuit diagram of the dual access control device of the first embodiment, and FIG. 3 is an explanatory diagram of each bit of a write-only control register. 4 is an explanatory diagram of each bit of the read-only control register, FIG. 5 is a time chart explaining the reserve operation of the first embodiment, and FIG. 6 is a time chart explaining the release operation of the first embodiment. FIG. 7 is a time chart explaining the priority select operation of the first embodiment,
FIG. 8 is a block diagram of the dual access control device according to the second embodiment, FIG. 9 is a circuit diagram of the dual access control device of the second embodiment, and FIG. 10 is a unit address and write / read-only control register. FIG. 11 is a time chart explaining the reserve operation of the second embodiment, and FIG. 12 is a time chart explaining the release operation of the second embodiment.
FIG. 13 is a time chart for explaining the priority select operation of the second embodiment, FIG. 14 is a system configuration diagram using a dual access control device according to the prior art, and FIG. 15 is a block of the magnetic disk control device of FIG. FIG. 16 is a time chart showing a reserve and priority select sequence, and FIG. 17 is a time chart showing a release sequence. DESCRIPTION OF SYMBOLS 1 ... Magnetic disk control means, 2 ... Write-only storage means, 3 ... Read-only storage means, 14 ... Hard disk controller LSI, 15 ... Write-only control register, 16
… Read-only control register, 62, 63… Host device, 68,
69 ... Magnetic disk control device, 70 ... Magnetic disk device.

Claims (2)

(57) [Claims] 1. A dual access control device for a magnetic disk device, wherein a plurality of magnetic disk control devices receive a processing command and a unit address of the magnetic disk device from their respective upper-level devices and competingly use the magnetic disk device. A magnetic disk control means for generating a polling signal to the magnetic disk device and a control signal for validating a processing command, receiving a response signal from the magnetic disk device, processing it, and sending it to a host device; Storage means for storing the processing command and the unit address, and a comparison means for comparing the unit address and the polled address stored in the storage means with a storage means for storing the selection state of the magnetic disk device, and a request for coincidence and reservation of the comparison result. Unit select tag signal by the processing command indicating A unit select tag signal generating means for generating a tag signal, a tag signal generating means for generating a tag signal by the processing command indicating the selected state and a release request indicating reserved, and the processing command and tag indicating a release request The magnetic disk device is reserved by the signal generating means by the bus bit signal generating means for generating the bus bit signal, the unit select tag signal and the signal indicating the unit address, and the magnetic disk device is released by the tag signal and the bus bit signal. A dual access control device for a magnetic disk device, comprising: a drive unit that generates a drive signal to perform. 2. The magnetic disk device according to claim 1, wherein the storage means has a plurality of storage areas corresponding to the plurality of magnetic disk devices, and performs processing independently for each magnetic disk device. Dual access controller.